JPH0438289B2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive conversion device that detects a physical quantity such as a differential pressure by converting it into a change in capacitance. This invention relates to a capacitive conversion device that removes the influence.

<Prior Art> FIG. 4 is a block diagram showing the configuration of a conventional capacitive converter which is the basis for improvement.

The capacitive sensor 10 has a common electrode 11 and a first electrode 1.
2. The second electrodes 13 are arranged facing each other, and the first capacitance is
C _H and a second capacitor C _L are formed. The common electrode 11 is moved by a differential pressure or the like as shown by an arrow F, thereby differentially changing the first capacitance _CH and the second capacitance C _L.

The first electrode 12 and the second electrode 13 are connected to the input terminal of the inverter _G1 via switches _SW1 and _SW2 , respectively. A bidirectional constant current circuit _CC1 is connected between the input and output terminals of the inverter _G1 .

The output end of inverter _G1 is a flip-flop
Connected to FF input terminal CL. Switches SW ₁ and SW ₂ are switched depending on the voltage levels at the output end Q and the inverted output end of the flip-flop FF, and the voltage at the output end Q is further smoothed by the integrator 14 and output to the output end 15. .

Note that the flip-flop FF is energized by power supply voltages of + _Es and _-Es .

Next, the operation of the capacitive converter shown in FIG. 4 constructed as above will be explained using the waveform diagram shown in FIG. 5.

When the voltage level at the output terminal Q of the flip-flop FF is at a high level "H" (FIG. 5C), the switch _SW1 is on and the switch _SW2 is off. In this state, when the voltage at the output terminal of inverter G ₁ is at a high level "H" (Fig. 5 b), the first capacitor C _H is charged with a constant current i from the bidirectional constant current circuit CC ₁ , as shown in Fig. 5. Inverter G ₁ as shown in
The voltage at the input end of is a voltage waveform that increases at a constant rate. When the upper threshold voltage of the hysteresis of inverter _G1 is reached, the voltage level at the output terminal of inverter _G1 is inverted. In this inverted state, the electric charge stored in the first capacitor C _H is discharged by the constant current i from the bidirectional constant current circuit CC ₁ , so the voltage at the input terminal of the inverter G ₁ decreases as shown in Figure 5A. , when the lower threshold voltage of inverter _G1 is reached, the inverter
The voltage level at the output terminal of _G1 is reversed. In this inverted state, the voltage level at the output terminal Q of the flip-flop FF is inverted to low level "L" and the switch is turned off.
Since SW ₁ is off and switch SW ₂ is on, the output terminal of the flip-flop FF is at high level.
11 period t The second period of this low level as well as _H
Also at t _L, charging and discharging to the second capacitor C _L is repeated. Repeat this from now on.

Therefore, the voltage fluctuation at the input terminal of inverter _G1 is
If e _IN (Fig. 5 A), the first capacitance C _H and the second capacitance
Considering the charge fluctuation of C _L , the first period t _H and the second period
t _L becomes t _H =2·e _IN C _H /i (1) t _L =2·e _IN C _L /i (2). Further, if the gain of the integrator 14 is set to 1, the voltage V _p appearing at the output terminal 15 becomes V _p =-t _H E _s −t _L E _s /t _H +t _L (3). Substituting equations (1) and (2) into equation (3), we obtain V _p = E _{s CL} − _CL / _CL + C _H (4). Therefore, it is not affected by fluctuations in the threshold of inverter G ₁ , that is, fluctuations in amplitude of e _IN , or fluctuations in current i of CC ₁ of the bidirectional constant current circuit, and responds to changes in capacitance corresponding to displacement of common electrode 11. voltage V _p is obtained.

<Problems to be Solved by the Invention> However, such a conventional capacitive conversion device has a distributed capacitance C _s between the electrodes of the capacitive sensor 10, a distributed capacitance C c1 at the input end of the inverter G 1 , and a distributed capacitance C _c1 at the input end of the inverter G ₁ . ₁
There is a problem in that nonlinearity occurs in the input/output characteristics due to propagation delays and the like.

Of these, the propagation delay of inverter _G1 is caused by the fact that the point at which the input voltage exceeds the threshold and the output level is inverted varies due to the influence of temperature. For example, as shown in Figure 6A, the voltage at the input terminal of inverter _G1 should correctly be folded back as shown by the dotted line, but if the threshold changes due to the influence of temperature and folded back as shown in the solid line as shown in the figure, Δe _L , Δe _H occur, and as a result, the voltage at the output terminal of the inverter G ₁ lags by Δt _L and Δt _H as shown in FIG. 6B.

The influence of the propagation delay and distributed capacitance of inverter _G1 both work in the same direction, giving nonlinear characteristics to the relationship in equation (4).

<Means for Solving the Problems> In order to solve the above problems, the present invention provides a first capacitance and a first capacitance between a first electrode and a second electrode for a common electrode that moves in response to physical displacement. a capacitive sensor in which two capacitors are formed; a voltage operating means having a first and second output terminal that outputs an operating voltage that is increased or decreased according to an operating signal and an inverted operating voltage having a polarity opposite to the operating signal; a measuring end to which electrodes are connected alternately;
a selection means for alternately switching the first electrode to the first output terminal and the measurement terminal, and the second electrode to the measurement terminal and the second output terminal, respectively, in this order; and a reference voltage source that generates a reference voltage at the first input terminal. The measuring terminals are respectively connected to the second input terminals, the first fixed capacitor is connected between the output terminal and the second input terminal, and the main charging means maintains the voltage of the measuring terminals at the reference voltage, and the main charging means supplies a constant current to the measuring terminals. a discharging means for supplying, and an auxiliary charging means for charging the measurement end via the second fixed capacitor by switching between the operating voltage and the predetermined voltage;
The present invention includes bistable means that inverts the state in response to the output level of the main charging means to switch between the selection means and the auxiliary charging means and outputs an operation signal.

<Example> Hereinafter, an example of the present invention will be described based on the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. Components having the same functions as those shown in FIG. 4 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate.

Reference numeral 16 denotes a selection circuit, which is composed of CMOS transistor switches SW ₃ and SW ₄ . The first electrode 12 is connected to the measurement end 1 through one end of the switch SW ₃ , and the second electrode is connected to the measurement end 1 through one end of the switch SW ₄ .
7 is connected. Switch SW ₃ is a P channel and N channel field effect transistor.
Q ₆ , Q ₇ , and the switch SW ₄ are respectively composed of P-channel and N-channel field effect transistors Q ₈ and Q ₉ .

The main charging circuit 18 includes a fixed capacitor C _K1 and a differential amplifier Q ₅
consists of the inverting input terminal (−) of the differential amplifier _Q5
are connected to the measuring terminal 17, and the non-inverting input terminals (+) are respectively connected to a reference voltage source _EBR having a reference voltage _ER . Inverting input terminal (−) of differential amplifier _Q5
A fixed capacitor C _K1 is connected between the output terminal and the output terminal.

The output terminal of the differential amplifier _Q5 is connected to the input terminal C _L of the flip-flop FF as a bistable means,
Switches SW ₃ and SW ₄ are controlled by the voltage level of the operating signal at the output terminal Q of the flip-flop FF.

19 is a voltage manipulation circuit, which is composed of an integrator Q ₁₀ and an inverting amplifier Q ₁₁ that inverts this output voltage,
The output voltage +V of the integrator _Q10 is connected to the other end of the switch _SW3 , and the output voltage -V of the inverting amplifier _Q11 is connected to the other end of the switch SW3.
is applied to the other end of SW ₄ , respectively.

20 is an auxiliary charging circuit, which is composed of a switch SW ₅ composed of a CMOS transistor and a fixed capacitor C _K2 , and one end of the switch SW ₅ is connected to a common potential point.
COM, and the other end is connected to the output end of the integrator _Q10 . Switch SW ₅ is P channel and N
Channel field effect transistor Q ₁₂ ,
Q Consists of ₁₃ . The switch _SW5 is controlled by the voltage level of the output terminal Q of the flip-flop FF, and applies the voltage +V at the output terminal of the integrator _Q10 or the voltage at the common potential point COM to the measuring terminal 17 via the fixed capacitor C _K2 . .

Further, a current i obtained by making the power supply voltage +E _s constant by a constant current circuit CC ₂ is applied to the measuring end 17 to form a discharge means.

Next, the embodiment shown in FIG. 1 constructed as described above will be explained with reference to the waveform diagram shown in FIG. 2.

At the point when the voltage level at the output terminal Q of the flip-flop FF changes from -E _s to +E _s (Fig. 2 H), transistors Q ₆ and Q ₈ are turned off (Fig. 2 H and C).
Then, transistors Q ₇ and Q ₉ are turned on (Figure 2).
becomes. Therefore, the voltage +V of the first capacitance C _H between the first electrode 12 and the common electrode 11 is applied to the measurement end 17.
(FIG. 2B) is applied, and the measuring terminal 17 is charged via the fixed capacitor C _K1 by controlling the potential of the measuring terminal 17 of the differential amplifier _Q5 to be maintained at the reference voltage _ER . On the other hand, although the potential of the measuring terminal 17 is about to be changed by the current i generated by the constant current circuit _CC2 , the differential amplifier _Q5 maintains the potential of the measuring terminal 17 constant to the reference voltage _ER (see Fig. 2). A), so the current i is absorbed by the fixed capacitor C _K1 , and the amount of charge at the point in time is gradually erased by the current i (the second
The flip-flop FF is inverted at the point in time (D) in Figure 2 (E) in Figure 2.

If the voltage change at the output terminal of the differential amplifier _Q5 at this point is _eH , and the period _tH for absorbing this voltage change _eH , then the following equation holds true considering the amount of charge fluctuation in the fixed capacitor _CK1 . do.

(C _H +C _s ) ( _ER −V) + C _K2 (V−O) = C _K1 e _H (5) C _K1・e _H = it _H (6) Next, at the time of , transistors Q ₆ , Q ₈ is on (FIG. 2, F and H), and transistors Q ₇ and Q ₈ are ON (FIG. 2, G and R). Therefore, measurement end 1
7 is applied with the voltage _{-V ( Fig} . Due to the maintenance control action, the measuring terminal 17 is charged via the fixed capacitor C _K1 , and the potential of the measuring terminal 17 is maintained at the reference voltage E _R (Fig. 2 A). The output voltage e _L of the dynamic amplifier Q ₅ increases (Fig. 2 D).The charging current to the measuring terminal 17 via the fixed capacitor C K1 is increased by the second capacitor C _K1 .
Flows into C _L. Further, since the potential of the measuring terminal 17 is maintained at the reference voltage _ER , the current i from the constant current circuit _CC2 does not flow into the second capacitor _CL , but is entirely absorbed by the fixed capacitor _CK1 . As a result of the absorption of the current i into the fixed capacitor C _K1 , the output voltage of the differential amplifier _Q5 gradually decreases (Fig. 2 D), and at the point when the flip-flop FF
is reversed.

Period circle t _L that absorbs this voltage change e _L (Figure 2 D)
Then, taking into account the amount of charge fluctuation in the fixed capacitor C _K1 , the following equation holds true.

( _CL + C _s ) (E _HR ) - (-V)) + C _K2 (O-V) = C _K
1
e _L (7) C _K1・e _L ＝it _L (8) In the conditions shown in Figure 2 I to H, the voltage operation circuit 1
As shown in FIG. 2H, the operating signal to Q9 is larger in period _tL than in period _tH , so integrator _Q10 gradually lowers the +V voltage. As a result, the voltages _{+ V and -V} are changed as indicated by the arrows in FIG.
This becomes e _L = e _H from equations (6) and (8). Therefore, e _L =
From the relationship e _H and equations (5) and (7), (C _H +C _s ) (E _R −V) + C _K2 V=(C _H +C _s ) (E _R +
V) −C _K2 V (9) is obtained.

Note that the distributed capacitance C _c1 formed between the measuring end 17 and the common potential point COM is the same as when the potential of the measuring end 17 is always maintained at the reference voltage E _R (Fig. 2 A).
No charge transfer occurs in the distributed capacitance C _c1 , so its existence can be ignored, but this point is significantly different from the conventional capacitive converter shown in FIG.

The influence of distributed capacitance C _s can be removed by selecting C _K2 =C _s . That is, in equation (9), if C _K2 =C _s , then V=E _R C _H −C _L /C _H +C _L (10), and the distributed capacitance C _s does not appear. Note that the distributed capacitance C _s formed between the first electrode 12 and the second electrode 13 with respect to the common electrode 11 can be formed equally by making the structure symmetrical. From the output terminal 15, a voltage V proportional to the difference in the sum of capacitances can be obtained as in the conventional case.

FIG. 3 is a partial block diagram showing another embodiment of the present invention. In this embodiment, when the capacitive sensor 10 and the conversion circuit 21 are separated, a cable connecting them is used.
Although distributed capacitance is formed between CB _H (CB _L ) and the common potential point COM, a configuration is shown in which this effect is removed.

Cable CB _H (CB _L ) is composed of core wire 22H (22L) and guard 23H (23L), etc.
Between the core wire 22H (22L) and the guard 23H (23L), there is a distributed capacitance C _GH (C _GL ) and a guard 23H (23L).
There is a distributed capacitance C _OH between L) and the common potential point COM.
( _COL ) is formed.

24 is a guard circuit, which is composed of CMOS transistor switches SW ₆ and SW ₇ . Switch SW ₆ has P channel and N channel field effect transistors Q ₁₄ , Q ₁₅ , and switch SW ₇ has P channel and N channel field effect transistors Q 14 , Q 15 .
It is composed of channel and N-channel field effect transistors Q ₁₆ and Q ₁₇ , respectively.

One end of transistor Q ₁₄ and one end of transistor Q ₁₇ are connected to the output end of integrating circuit Q ₁₀ and the output end of inverting amplifier Q ₁₁ , respectively. the other end of transistor Q ₁₄ ,
The other ends of Q ₁₇ are connected to guards 23H and 23L, respectively. Switch SW ₆ (SW ₇ ) is a switch
It is controlled by the voltage level of the Q terminal of the flip-flop FF in conjunction with SW ₃ (SW ₄ ).

In Fig. 3, the potential at the measuring end 17 is the reference voltage.
Always held in _FR , but with switch SW ₃ (SW ₈ )
Since SW ₆ (SW ₇ ) operates in conjunction with each other, the distributed capacitance C _GH
The charge of (C _GL ) is always maintained at zero and is guarded.
Charges enter and exit the distributed capacitance C _OH (C _OL ), but
This does not affect the measuring end 17. This guard circuit 24 limits the distributed capacitance to a very small distributed capacitance C _s within the capacitive sensor 10 .

Note that it is sufficient that a voltage related to the voltage V is applied to the fixed capacitance C _K2 that compensates for the distributed capacitance C _s every time the switch SW ₅ is switched. For example, the transistor Q ₁₃ may be set at -V instead of the common potential point COM. . When switching between (+V) and (-V) instead of switching between +V and zero, the value of fixed capacitance C _K2 is halved. Also, instead of (+V) to 0, it may be 0 to (-V).

The voltage operation circuit 19 reads, for example, a duty cycle value with a microcomputer, determines the operation amount with the microcomputer, and outputs a voltage (+) via a digital/analog converter and an output multiplexer.
By supplying V) and (-V) and possessing the operating amount to the digital/analog converter at that time as internal data, a digital amount equivalent to the voltage (+V) and (-V) is obtained, and this is It can also be transferred or displayed externally.

The switches SW ₁ to _{SW 7} are not limited to P-channel and N-channel MOS/FETs, and any element can be used as long as they can be switched.

In the embodiment shown in FIG. 1, a constant current i was obtained from the power supply voltage + E _s through the constant current circuit CO ₂ , but since the potential at the measuring end 17 is controlled to be maintained at the reference voltage E _R , a simple resistor It is also possible to supply a constant current i using

Further, it is preferable to interpose a comparator with one end of its input connected to a common potential point between the input terminal CL of the flip-flop FF and the main charging circuit 18 to stabilize the threshold at the time of inversion. In this case, the comparator or flip-flop
If the total delay time when FF is reversed is t _d , then the second
The periods t _L and t _H shown in the figure include this t _d , and (6), (8)
The equations are the following equations (11) and (12).

C _K1 e _H = i (t _H - t _d ) (11) C _K1 e _L = i (t _L - t _d ) (12) In this case, in the example shown in Figure 1, equilibrium is reached at t _H = t _L. However, by substituting this condition into equations (5), (7), (11), and (12) and rearranging the equations, we obtain equation (9). Therefore, from equation (9),
Just as when formula (10) was obtained, this effect of t _d does not occur.

Furthermore, the potential at the measuring terminal 17 for each state reversal fluctuates instantaneously due to insufficient charging capacity or a delay in the differential amplifier _Q5 , but it is attracted to an equilibrium with the same waveform for each period t _H and t _L. Therefore, similarly to this t _d, no waveform distortion occurs due to the ability of the differential amplifier _Q5 .

<Effects of the Invention> As described above in detail with the embodiments, according to the present invention, the potential at the measurement end is adjusted by applying an initialization voltage to the first electrode or the second electrode and resetting by constant current discharge. Since it is fixed to the reference voltage, it is possible to avoid being affected by the distributed capacitance at the measuring end. Furthermore, since a simple binary voltage is repeatedly applied to the first electrode and the second electrode, the cable can be easily guarded. Furthermore, since a simpler guard configuration can be used, only the distributed capacitance C _s within the capacitive sensor needs to be compensated, and the amount of compensation can be minimized. In addition, the influence of the delay time from completion of discharge to reversal of the output of the bistable means can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a waveform diagram showing waveforms of various parts of the embodiment shown in FIG. 1, FIG. 3 is a partial block diagram showing another embodiment of the present invention, and FIG. 4 shows the configuration of a conventional capacitive converter. 5 is a waveform diagram showing the waveforms of each part of the capacitive converter shown in FIG. 4, and FIG. 6 is a waveform diagram illustrating the problems of the conventional capacitive converter shown in FIG. 4. be. 10...Capacitance sensor, 11...Common electrode, 12...
First electrode, 13... Second electrode, 14... Integrator, 16
...Selection circuit, 17...Measuring end, 18...Main charging circuit,
19... Voltage operation circuit, 20... Auxiliary charging circuit, 21
... conversion circuit, 24 ... guard circuit, C _H ... first capacitor,
C _L ...Second capacitor, CC ₁ ...Bidirectional constant current circuit, CC ₂ ...
Constant current circuit, _ER ...Reference voltage, FF...Flip-flop.

Claims (1)

[Claims] 1. A capacitive sensor in which a first capacitance and a second capacitance are formed by a first electrode and a second electrode for a common electrode that moves according to physical displacement, and an operating voltage that is increased or decreased by an operating signal. a voltage operating means having a first and second output end that outputs an inverted operating voltage of opposite polarity; a measuring end to which the first electrode and the second electrode are alternately connected; and a selection means for alternately switching the second electrode to the measurement end and the second output end in this order, respectively, and a reference voltage source for generating a reference voltage to the first input end to the second input end. a main charging means connected to each of the measurement terminals and having a first fixed capacitor connected between the output terminal and the second input terminal to maintain the voltage of the measurement terminal at the reference voltage; and main charging means for supplying a constant current to the measurement terminal. a discharging means for supplying; an auxiliary charging means for switching between the operating voltage and a predetermined voltage to charge the measuring end via a second fixed capacitor; 1. A capacitive conversion device comprising bistable means for switching the auxiliary charging means and the auxiliary charging means and outputting the operation signal.