JPS62180214A - Capacity type conversion device - Google Patents

Abstract

PURPOSE:To fix the potential at a measurement terminal to a reference voltage and to eliminate the influence of the distributed capacity at the measurement terminal by impressing an initializing voltage to the 1st or 2nd electrode and resetting it by constant-current discharging. CONSTITUTION:When the voltage level at the output terminal Q of an FF varies from -Es to +Es, a transistor (TR) Q6 turns off and TRs Q7 and Q9 turn on to initiate charging to the measurement terminal through a fixed capacitor Ck1 under the control of a differential amplifier Q5. Then, the current quantity of the charging decreases gradually and the FF is inverted at the next point of time. Namely, a selecting circuit 16 switches the 1st electrode 12 to the 1st output terminal SW3 and measurement terminal 17 and the 2nd electrode 13 to the measurement terminal 17 and the 2nd output terminal SW4 alternately to hold the measurement terminal 17 at the reference voltage ER. An operating voltage and a specific voltage, on the other hand, are switched by an auxiliary charging circuit 20 to charge the measurement terminal 17 through the 2nd capacitor CL. The FF as a bistable means is inverted in state in response to the output level of the circuit 17 and the selecting means and auxiliary charging means are switched to output an operation signal.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a capacitive conversion device that detects a physical quantity such as a differential pressure by converting it into a change in capacitance. This invention relates to a capacitive conversion device that eliminates Shokyo.

<Prior Art> FIG. 4 is a block diagram showing the configuration of a conventional capacitive conversion device, which is the basis for improvement.

The capacitive sensor 10 has a common electrode 11 and a first electrode 12 . Second
Electrical containers 13 are arranged facing each other, and have a first volume fcH and a second volume f.
OL is formed. The common electrode 11 is moved by differential pressure or the like as shown by an arrow F, thereby differentially changing the first capacitance fCH and the second capacitance OL.

The first electric pole 12 and i2*Sagi 13 are respectively switch SWs.
1, and is connected to the input terminal of the inverter G1 via SW2. A bidirectional constant current circuit CC1 is connected between the input and output terminals of the inverter G1.

The output terminal of inverter G1 is connected to the input terminal OL of flip-flop FF. Switches SW1 and 8w2 are switched depending on the voltage levels at the output terminal Q and the inverted output terminal Q of the clip-flop FF, respectively, and the voltage at the output terminal Q is further flattened by the integrator 14 and outputted to the output terminal 15.

In addition, S of flip-flop FF +E, -E Powered by mains voltage.

Next, the operation of the capacitive converter shown in FIG. 4 constructed as above will be explained using the waveform diagram shown in FIG. 5.

The voltage level at the output terminal Q of the flip-flop FF is high level wH1! (FIG. S(C)) Fi, switch SW1 is on and switch SW2 is off. In this state, the voltage at the output terminal of inverter G1 is at high level I.
When H1 (Figure 5 (b)), bidirectional constant current circuit CC1
Since the first capacitor CH is charged with a constant current 1, as shown in Fig. 5 (
As shown in a), the voltage at the input terminal of the inverter G1 has a voltage waveform that increases at a constant rate.

When the upper limit threshold voltage of the hysteresis of inverter G1 is reached, the voltage level at the output terminal of inverter G1 is inverted. In this inverted state.

The first capacity CH with a constant current i from the bidirectional constant current circuit co1
Since the charge charged in the inverter G1 is discharged, the voltage at the input terminal of the inverter G1 decreases as shown in Fig. M5 (a).

When the lower threshold voltage of inverter Gl is reached, the voltage level at the output terminal of inverter G1 is inverted. In this inverted state, the voltage level of the output iQ of the clip 70-tube FF is inverted to the low level IL'', the switch SW1 is turned off, and the switch sW2 is turned on, so that the output of the flip-flop FF is repeated. repeat.

Therefore, if the voltage fluctuation at the input end of the inverter G1 is eIN (Fig. 5 (a)), the first period tH and the second period tL are・It becomes. Further, if the gain of the divider 14 is set to 1, the voltage V appearing at the output terminal 15 will be as follows. (3) In the formula! Substituting equations 1) and (2), we get

get. Therefore, fluctuations in the threshold of inverter G1, that is, amplitude fluctuations in the bidirectional constant current circuit CC1
A voltage V corresponding to a change in capacitance corresponding to a displacement of the common electrode 11 can be obtained without being affected by a change in the current 1 .

<Problems to be Solved by the Invention> However, such a conventional capacitive conversion device has a distributed capacitance XC3 between the electrodes of the capacitive sensor 0, a distributed capacitance 0°1 at the input end of the inverter G1, and a propagation of the inverter Gl. There is a problem in that nonlinearity occurs in the input/output characteristics due to delays and the like.

Of these, the propagation delay of inverter G1 is caused by the fact that the point at which the input voltage exceeds the threshold and the output level is inverted varies due to the influence of temperature. For example, the 6th
As shown in Figure (A), the voltage at the input terminal of inverter G1 should be folded back as shown by the dotted line, but as shown in Figure 1, the threshold changes due to the influence of temperature and it is folded back as shown in the solid line, ΔeL, ΔeH An excess of
Eventually, the voltage at the output terminal of inverter G1 becomes ΔtL as shown in FIG. 6 (b).

This causes a delay of ΔtH.

The influence of the propagation delay 1 distributed capacitance of inverter G1 both works in the same direction and gives a nonlinear characteristic to the relationship in equation (4).

Means 2 for Solving the Problems This invention solves one or more problems by using a common 1! that moves in response to physical displacement! A capacitive sensor in which a first capacitance and a second capacitance are formed by a first T11 pole and a second M pole with respect to a pole, and it outputs an operating voltage that is increased or decreased in response to an operating signal and an inverted operating voltage that has the opposite polarity. Voltage operating means having a second output terminal, a first electric sign and a twenty-first! a measuring end to which poles are alternately connected; a selection means for alternately switching the first electrode to the first output end and the measuring end; the second electrode to all the constant temperature two output ends; A reference voltage source that generates a reference voltage is connected to one input terminal, a measurement terminal is connected to a second input terminal, and a first fixed capacitor 1 is connected between the output terminal and the second input terminal, so that the voltage at the measurement terminal is used as a reference voltage. The main charging means held at constant 1 to the measuring end! a discharging means for supplying current; and an auxiliary charging means for charging the measuring end via the second fixed capacitor by switching between the operating voltage and the predetermined voltage.

A bistable means is provided which inverts the state in response to the output level of the main charging means, switches between the selection means and the auxiliary charging means, and outputs an operation signal! fIIIi.

<Example> Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Components having the same functions as those shown in FIG. 4 are denoted by the same reference numerals, and explanations thereof will be omitted as appropriate.

16 is the selection circuit and OMO! 9) Transistor switch SW3. It is composed of SW4. 11th! pole 12
is connected to the measurement end 17 through one end of the switch SW3, and the second electrode is connected to the measurement end 17 through one end of the switch SW4. The switch SW3 includes P-channel and N-channel field effect transistors Q6. Q7. switch S
W4 is a P-channel and N-channel field effect transistor Q8. Each consists of Q9.

The main charging circuit 18 is composed of a regular customer tOKl and a differential amplifier Q5.
are respectively connected to a reference voltage source EB□. A fixed capacitor CKl is connected between the inverting input terminal (-) and the output terminal of the differential amplifier Q5.

The output terminal of the differential amplifier Q5 is connected to the input terminal OL of a 7-lip-flop FP as a bistable means.

Switch sw3. Controls sw4.

19 is a voltage manipulation circuit, which is composed of an integrator QIO and an inverting amplifier Qll that inverts this output voltage;
The output voltage +V of o is at the other end of switch SW3.

The output voltage -■ of the inverting amplifier Qll is applied to the other end of the switch SW4.

20 is an auxiliary charging circuit, which is composed of a switch 3Ws composed of a transistor (0MO8) and a fixed capacitor CK2,
One end of the switch SW- is connected to the common potential point 00M, and the other end is connected to the output end of the integrator QIO. The switch SW5 is composed of P-channel and N-channel field effect transistors Q1□ and Q13. The switch 8Ws is controlled by the voltage level of the output '4Q of the flip-frog FP, and applies the voltage +V at the output terminal of the integral 1QIQ or the voltage at the common potential point COM to the measurement terminal 17 via the fixed capacitor CK2. At the end 17, there is a current I made by making the power supply voltage +z a constant current by a constant FL current circuit OC2.
is applied to form a discharge means.

Next, the embodiment shown in FIG. 1 having one or more configurations will be described with reference to the waveform diagram shown in FIG. 2.

The voltage level at the output terminal Q of the clip-flop FF is -E
When it becomes 10E from ■ (Fig. 2 (E)), S
S is the transistor Q6. Q8 is off (see Figure 2).

Transistor Q7. Q9 is on (Figure 2 (G) (S))
becomes.

Therefore, the first electric dropper 12 and the common electrode 11 are connected to the measuring end 17.
The first volume between '1itC? The voltage +V of I (Fig. 2 (b)) is applied, and the potential of the measuring terminal 17 of the differential amplifier Q5 is maintained at the reference voltage E, and the fixed capacitor CK is maintained by the same action.
1, charging of the measuring end 17 takes place. On the other hand, the potential of the measuring terminal 17 is about to be changed by the current iK from the current circuit CC2, but the differential amplifier Q5 maintains the potential of the measuring terminal 17 constant relative to the reference voltage E1 (see Fig. 2). )), so the α current i1d is absorbed into the fixed volume -da, and the light at the point of ■? ! ! The amount is gradually erased by the current i (see Figure 2)), and at the point ■, the clip 70 tube F
F is reversed (Fig. 2 (E)).

The voltage change at the output terminal of the differential amplifier Q5 at time point ■ is expressed as eHl
If the period tH is used to absorb this voltage change eH, then the following equation holds true taking into consideration the amount of charge fluctuation at regular customer CKl.

(OH"0sXEB-V) +0K2(V -0)=
OKI eHC3)) (3 to 1-eH== I tH(
6) Next, at the time point (■), the transistor Q5. When Q8 is on (FIG. 2 (E)), transistor Q7. Q8 turns on (Fig. 2 (g) (s)). Therefore, the second electrode 13 and the common 1! to the measurement end 17! Second view C between pole 11
9 voltage -V (Fig. 2 (c)) is applied, and the differential amplification a
By controlling and maintaining the potential of the measuring end 17 of Q5 at the reference voltage "a", the measuring end 17 is charged via the fixed customer MOKl, and the potential of the measuring end 17 is maintained at the reference voltage ER. (Fig. 2 (a)).The output voltage e of the differential amplifier 6Q5 increases as much as necessary to maintain this (see Fig. 2))
,In addition.

The charging current to the measuring terminal 17 which is carried out via the fixed capacitor CK1 flows into the second capacitor OLK. In addition, constant current circuit CC
Electricity from 2? Since the potential of the measuring end 17 of Mi is maintained at the reference voltage E□, the second capacitor thtCLK does not flow and is completely absorbed by the fixed customer "CKl".The current i to the fixed customer fitOKl
As a result, the output voltage of the differential amplifier Q5 gradually decreases (see FIG. 2)), and the flip-flop FF is inverted at the point (2) in FIG.

The period for absorbing this voltage change e is 11. (See Figure 2)
), a linear equation is established taking into account the amount of charge fluctuation in the fixed capacitor CK1.

(C(,+Os)(EFL-(-'/))"2 to C'(0-V)" OKI eb (7) OKI
' e(, = i tL(8) Figure 2 (a) to (a)
In the state shown in FIG.
As shown in FIG. 7, since the period 11 is larger than the period tH, the integrator QIO continuously lowers the voltage of +V. As a result, as shown by the arrows in FIG. 2 (7) and (b), the voltages +V and -V are changed and the period tL+tH is corrected,
Finally, it comes to rest at tH"' tH.

This becomes eL=e1-1 from equations (6) and (8).

Therefore, from the relationship e,=eH and equations (5) and (7), (CH+C5)("R-v) +aK2v=(aH+o
, we get 2V at 0g1+v)-0.

Note that the distributed capacitance Ocl formed between the measuring end 17 and the common potential point 00M is such that the potential of the measuring end 17 is always equal to the reference voltage E.
, (Figure 2 (a)), so the distributed capacity is 0゜1
Since no charge transfer occurs in this case, its existence can be ignored, but this point is significantly different from the conventional capacitive converter shown in FIG.

The influence of distributed capacitance C5 can be removed by selecting CK2=Cs. That is, in equation (9), if CK2 is set as Cs, the distributed capacitance O does not appear.
The distribution volumes thtO formed between the first electrode 12 and the second electrode 13 can be made equal by making the structure symmetrical. From the output terminal 15, a voltage V proportional to the difference in the sum of capacitances can be obtained as in the conventional case.

FIG. 3 is a partial block diagram showing another embodiment of the present invention. In this embodiment, when the capacitance sensor 10 and the conversion circuit 21 are separated, a distributed capacitance is formed between the cable CBH (CB,) connecting them and the common H1 point COM, but this influence is removed. It shows the configuration.

The cable 0BH (OBL) is composed of a core wire 22H (22L) and a guard 23H (23L), but there is a distributed capacitance CGH (CGL)- between the core wire 22H (22L) and the guard 23H (23L). Guard 23H (2
3L) and the common potential point 00M, there is a distributed capacitance coH.
(CoL) is formed.

24 is a guard circuit, which is a transistor switch sw6. It is composed of sw7. switch SW6
are P-channel and N-channel field effect transistors Q14. Q15' switch sw7'd P-channel and N-channel field effect transistor Q16
゜Q17.

One end of the transistor Q1 and one end of the transistor Q17 are respectively connected to the output end of the inverting amplifier Qll of the integrator circuit QIO. The other end of transistor Q14.

The other ends of Q17 are connected to the guards 231-1.23L, respectively. Switch 5w6 (5w7) is switch 5
W3 (SW4) K is interlocked with slip flop FF Q
Controlled by the voltage level of the terminal.

In FIG. 3, the potential of the measuring terminal 17 is always maintained at the reference voltage E1, but the potential of the measuring terminal 17 is always maintained at the reference voltage E1.
7) operate in conjunction, so the distribution volume is 1o. H(CG
The charge of L) is always maintained at zero and is guarded.

Electric charge flows in and out of the distributed capacitance C81 ((CGL), but this does not affect the measuring end 17. This guard circuit 24 limits one distributed capacitance to a very small distributed capacitance fa within the capacitance sensor 0. Ru.

Note that it is sufficient that a voltage related to the voltage V be applied to the regular customer -'taK2 for compensating the distributed capacitance C every time the switch SW5 is switched.For example, the transistor Q13 may be at -V instead of the common potential point 00M. When switching from (+V) to (-■) instead of switching between +V and zero, fixed customer t
Set the value of CK2 to 1/2. Also.

(+V) to 0 may be replaced by θ to (-V).

The voltage operation circuit 19 reads the duty cycle value with a micro combinator, determines the operation amount with the microcomputer, and outputs the voltage (+V) via a digital/analog converter and an output multiplexer.

By supplying (-■) and possessing the amount of operation to the digital/analog converter at that time as internal data, a digital view corresponding to the voltage (+■) and (-V) is obtained, and this is transferred externally. It can also be transferred to or displayed.

Each of the switches SW1 to SW7 is not limited to P-channel and N-channel MO8-FETs, and any element that can be operated for switching can be used.

In the embodiment shown in FIG.
Although a constant current i was obtained through C2, the potential of the measurement end 17 was controlled to be maintained at the reference voltage E□.

It is also possible to supply a constant current i using a simple resistor.

Further, it is preferable to interpose a comparator with one end of its input connected to a common potential point between the input end OL of the flip-flop FF and the main charging circuit 18 to stabilize the threshold at the time of one inversion. in this case.

If the total delay time at the time of inversion of the comparator or clip-flop FF is td, then the period tL shown in FIG.
, tH includes this t, and equations (6) and (8) become the following α force and equation (2).

OKI eH” 1 (tH-td)
Q″0K1er, =l (tL-id)
+1 In this case, in the example shown in FIG. 1, equilibrium is achieved with t H = t L, but this condition is changed to <5),
<7), αKu, by substituting into equation (b) and rearranging the equation, we get (9
) to obtain the formula. Therefore, in the same way as when formula 1Q is obtained from formula (9), the influence of this t does not occur.

Furthermore, the potential of the measuring terminal 17 for each state reversal is equal to the differential amplifier S.
Although it instantaneously fluctuates due to insufficient charging capacity or delay of Q5, since the balanced Ka with the same waveform is drawn for each period 'H'L, similarly to this t, the capacity of the differential amplifier Q5 changes. No resulting waveform distortion occurs.

<Effects of the Invention> As specifically explained above with reference to Example 1, according to the present invention, measurement is performed by applying four initializing voltages to the first electrode or the 2711th electrode and resetting by constant four current discharge. Since the potential at the end is fixed to the reference voltage, it is possible to avoid being affected by the distributed capacitance at the measurement end. Furthermore, since a simple binary voltage is repeatedly applied to the first IT electrode and the second electrode, the cable can be easily guarded. Furthermore, since a simpler guard configuration can be used, it is only necessary to compensate for the distributed capacitance 0 within the capacitive sensor, and the amount of compensation can be reduced. In addition, the influence of the delay time from completion of discharge to reversal of the output of the bistable means can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a waveform diagram showing the waveforms of each part of the embodiment shown in FIG. 1, and FIG. 3 is a partial block diagram showing another embodiment of the present invention.
FIG. 4 is a block diagram showing the configuration of a conventional capacitive converter, FIG. 5 is a waveform diagram showing waveforms of each part of the capacitive converter shown in FIG. 4, and FIG. 6 is a block diagram showing the configuration of a conventional capacitive converter shown in FIG. FIG. 2 is a waveform diagram illustrating a problem with a capacitive converter. 10...Capacitance sensor, 11...Common electric picture, 12.
...first pole, 13...second electrode, 14...integrator, 16...selection circuit. 17... Measuring end, 18... Main charging circuit, 19...
Voltage operation circuit. 20... Auxiliary charging circuit, 21... Conversion circuit, 24.
...guard circuit, CH...first capacitance, CL...2g
2 capacity, Co1...bidirectional constant current circuit, CO□...
・Constant current circuit 1gR...Reference voltage, FF...Flip-flop. l:l:Be agent Patent attorney Shinsuke Ozawa,... To ^ To 6 To 1
567 ward-1 〉 ya bi, , , , , w 7'-+ Fig.

Claims (1)

[Claims] A capacitive sensor in which a first capacitance and a second capacitance are formed by a first electrode and a second electrode with respect to a common electrode that moves in response to physical displacement, and an operating voltage that is increased or decreased by an operating signal and vice versa. a voltage operating means having a first and second output terminal that outputs a polarity-reversed operation voltage; a measuring terminal to which the first electrode and the second electrode are alternately connected; and the first electrode and the first output terminal. a selection means for alternately switching the second electrode at the measurement end to the measurement end and the second output end respectively in this order; and a reference voltage source for generating a reference voltage at the first input end to the second input end. a main charging means to which the measurement terminals are respectively connected and a first fixed capacitor connected between the output terminal and the second input terminal to maintain the voltage of the measurement terminal at the reference voltage; and supplying a constant current to the measurement terminal. a discharging means for switching between the operating voltage and a predetermined voltage to charge the measuring terminal via a second fixed capacitor; and a selecting means for reversing the state in response to the output level of the main charging means. and bistable means for switching the auxiliary charging means and outputting the operation signal.