JPH0756529A - Power source circuit - Google Patents

Abstract

PURPOSE:To simplify and miniaturize the circuit and to reduce electric consumption. CONSTITUTION:When a control signal POL is low, switches SW2 and 3 are turned ON, a capacitor C1 is charged to a potential Vy1, the control signal POL is made high, switches SW1 and 4 are turned ON and the capacitor C1 is charged by the output potential of a power source 17. The capacitor C1 has a function as a circuit for discharging or absorbing electric loads between it and a load 19. Thus, when the charged or discharged current of the load 19 is fluctuated, current equivalent to its fluctuation is supplied by the power source 17 and the capacitor C1. At this time, a capacitor C2 is charged to a potential Vy2. When the control signal POL is made low again, the switches SW 2 and 3 are turned ON and the capacitor C2 has a function as a circuit for discharging or absorbing electric loads between it and the load 19. By charging the capacitor C1 to the potential Vy1 a part of a charged or discharged electric load when the voltage of the power source 17 is inverted is supplied from the capacitor C1. Thus, the current capacity of the power source 17 is made small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, and more particularly, to a driving circuit for a display device, particularly a gradation voltage source circuit for a digital data driver of an active matrix type liquid crystal display device and an AC drive for a common electrode. The present invention relates to a power supply circuit applicable to a common electrode drive circuit in the case of

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device (hereinafter referred to as a display device) which performs display based on digital image data (hereinafter referred to as image data) includes a display panel and a drive circuit. The display panel is a display substrate in which a plurality of data lines, a plurality of gate lines, picture element electrodes arranged in a matrix, and switch elements respectively connected to the picture element electrodes are formed on a glass substrate. And a common substrate which is arranged to face the display substrate and has a common electrode formed on a glass substrate. A display device is configured with a liquid crystal layer sandwiched between these display substrate and common substrate, and a plurality of gate lines and a plurality of data lines are formed on a glass substrate to display an image. The drive circuit applies a drive voltage to the liquid crystal layer of the display panel.
The drive circuit is arranged for each pixel in the display panel, and a gate drive circuit for individually selecting any one of a plurality of switch elements connected to a gate line and a data line, A data drive circuit for supplying an image signal corresponding to an image to the pixel electrode via the selected switch element.

FIG. 12 is a block diagram of the data drive circuit of the drive circuit to which image data of the prior art is input. The configuration of FIG. 12 shows a configuration of a part of a data driving circuit that outputs an image signal to a single data line.
Therefore, the data driving circuit has the configuration shown in FIG. 12 in the same number as the number of data lines of the display panel. In the following, for simplification of description, a case where the image data is composed of 3 bits (D ₀ , D ₁ , D ₂ ) will be exemplified. In this case, the image signal data has eight values of 0 to 7, and the signal voltage given to each picture element is one of the 8-level gradation voltages V _{0 to} V ₇ output from the gradation power supply circuit P. Will be either.

The data drive circuit is provided for each bit (D ₀ , D ₁ , D ₂ ) of the image signal data and is used for the sampling operation in the first stage D-type flip-flop M.
_SMP , a second-stage D-type flip-flop M _H used for a hold operation, one decoder DEC, and eight external power supply voltages V _{0 to} V ₇ and a data line On, respectively. A plurality of analog switches ASW ₀ to
And ASW ₇ . Eight kinds of gradation voltages V ₀
.About.V ₇ and control signals S _{0 to} S ₇ from the decoder DEC.
Are input to the plurality of analog switches ASW _{0 to} ASW ₇ , respectively, corresponding to the levels of the control signals S _{0 to} S ₇ ,
Gradation voltage V from each analog switch ASW _{0 to} ASW _{7
0 to} V ₇ is output or cut off.

In this data drive circuit, for example, when the value of the image data is "3", the analog switch AS
W ₃ is rendered conductive, the gradation voltage V ₃ becomes the output. In this case, the gray scale voltage V ₃ drives the data line via the analog switch ASW ₃ . Here, the gradation power supply circuit P
Is configured separately from the LSI (Large Scale Integrated Circuit) that constitutes the drive circuit, and is input to the drive circuit for each data line. This is because, in the actual driving circuit, the circuit of FIG. 12 exists for the number of data lines of the display panel. For example, in the case of a VGA type liquid crystal display device, the number of data lines reaches 1920. Here, the gradation power supply circuit P may drive all the data lines at the same time. In that case, it is difficult to manufacture the gradation power supply circuit P capable of sufficiently supplying the current required to drive all the data lines at the same time with a high degree of integration inside the drive circuit by the thin film technology.

Further, the above-mentioned conventional data drive circuit is
There is a problem that the structure is complicated and large. This means that when the digital image signal is 4 bits, 16 kinds of gradation voltages are required, and as the image signals increase to 6 bits and 8 bits, 64 kinds of gradation voltages are used.
This is because the number of types will increase to six. In other words, the same number of gradation voltages as the number of gradations is required. For this reason, the configuration of the power supply circuit for generating such a large number of gradation voltages becomes complicated and large, and the connection wiring between the power supply circuit and the analog switch becomes complicated.

For this reason, the data driving circuit of the prior art is practically limited to the case where the image signal has 3 bits or 4 bits. There is a problem that it is difficult to configure a drive circuit that performs gray scale display.

FIG. 13 shows an example of waveforms of the external gradation voltages V0 and V7 together with the waveform of the common electrode drive signal Vcom. FIG. 14 shows the waveform examples of the external gradation voltages V0 and V7 and the waveform example of the common electrode drive signal Vcom separately. In addition,
13 and 14 show waveforms in the case of line inversion in which the polarity of the voltage is inverted every horizontal line, and this case will be described below. Thus, the external gradation voltage V0 is
When the image data is “0”, it is a rectangular wave whose polarity is opposite to that of the common electrode drive signal Vcom and which is alternately inverted at the same time point. When the image data is “0”, a voltage between the grayscale voltage V0 and the common electrode drive signal Vcom Capacitance such as liquid crystal layer for each element is charged. The external gradation voltage V7 is the common electrode drive signal Vcom.
When the image data is “7”, the liquid crystal layer has a voltage between the grayscale voltage V7 and the common electrode drive signal Vcom and the liquid crystal layer for each pixel is the same. The capacity is charged.

A power supply circuit as shown in FIG. 15 has been used as the gradation power supply circuit P and the common electrode drive circuit. The case where this power supply circuit is the gradation power supply circuit P will be described below. This power supply circuit has an operational amplifier OP1, and the control signal POL is input to the inverting input terminal of the operational amplifier OP1 via the resistor R1. A high potential V _{H is applied} to the non-inverting input terminal of the operational amplifier OP1.
And a low potential V _L connected in series between resistors R2 and R3
The electric potential in between is connected. The output terminal of the operational amplifier OP1 is commonly connected to the bases of the transistors Q1 and Q2.

The collector of the transistor Q1 has a high potential V
_It is connected to _H and its emitter is connected to the emitter of the transistor Q2 via resistors R4 and R5 which are connected in series with each other. The collector of the transistor Q2 has a low potential V _L
Connected to. An output line is connected between the resistors R4 and R5, and the gradation voltage Vi (i = 0 to 7) is output to the analog switch SWi. The gradation voltage V
i is negatively fed back to the inverting input terminal of the operational amplifier OP1.

There is essentially no difference in the configuration of the power supply circuit between the case where the power supply circuit shown in FIG. 15 is used as the common electrode drive circuit and the case where it is used as the gradation power supply circuit P. When the power supply circuit is used as a common electrode drive circuit, the output from the power supply circuit is a constant potential or a voltage whose polarity is inverted. When the power supply circuit is used as the gradation power supply circuit P, the gradation voltage Vi output from the gradation power supply circuit P has an amplitude corresponding to each display data. Further, as compared with the case where the power supply circuit is used for a common electrode circuit, the gradation power supply circuit P
However, the difference is that the grayscale voltage Vi output from the power supply circuit may be in-phase or anti-phase with respect to the control signal POL.

[0012]

As described above, as shown in FIG.
Since the essence of the problem is the same regardless of whether the power supply circuit P of No. 5 is used as a gradation power supply or a common electrode driving power supply, the problem will be described below in the case of the gradation power supply circuit. explain.

The data line of the display panel is charged / discharged between a positive potential and a negative potential each time the common electrode driving power source and the grayscale power source reverse the polarities of their outputs. FIG. 16 shows an equivalent circuit when the data line is viewed as a load. In this equivalent circuit, the equivalent resistance Rs of the data line and the equivalent capacitance Cs of the data line are electrically connected in series. In an actual liquid crystal display device, 640 × 3 = 1920 such data lines are formed in a display panel of VGA specification, for example, and when the gradation voltage source is the maximum, 1920 of the circuit of FIG. It is necessary to drive a double load. The peak current that flows when the positive polarity and the negative polarity of the grayscale power source are reversed is considered below.

If the equivalent resistance Rs of the data line is 50 KΩ and the maximum potential difference between the positive and negative polarities seen from the common electrode is 10 V, the maximum peak current is

[0015]

## EQU1 ## 10/50 KΩ × 1920 = 384 mA. Conventionally, since the gradation power source needs to have the ability to basically satisfy this maximum current capacity, for example, in the circuit of FIG. 15, the operational amplifier OP1 has a large slew rate and a large current capacity. In addition, a current amplifier is formed by a complementary circuit of transistors in the subsequent stage, and a power supply circuit is configured so as to meet such requirements.

This conventional technique is based on the price increase (cost u).
p). Further, the current amplifier including the transistors Q1 and Q2 always amplifies the power supply current output from the power supply circuit P, resulting in an increase in current consumption. This increase in current consumption is an increase in current unnecessary for driving the display panel.

FIG. 17 shows a configuration of the power supply circuit P1 which can obtain the same effect as that of the power supply circuit P of FIG. The power supply circuit P1 is provided with DC power supplies 1 and 2 that output two different power supply voltages, respectively, and a capacitor C1 is connected to each power supply line 3 and 4 connected to each DC power supply 1 and 2.
C2 is connected in parallel. Each capacitor C
The terminals on the opposite side of the power supply lines 3 and 4 of C1 and C2 are connected to the reference potential Vy. The power supply lines 3 and 4 are connected to the respective input terminals of the changeover switch SW, the output terminals of the changeover switch SW are connected to the power supply line 5, and the gradation voltage Vi is output.

This prior art power supply circuit P1 alternately selects the DC voltage from the DC power supplies 1 and 2 by the changeover switch SW and outputs it. This allows the power supply circuit P1 to output a rectangular wave gradation voltage Vi. The capacitors C1 and C2 are connected to the DC power sources 1 and 1, respectively.
It is provided in order to stabilize the DC voltage during the period when the DC voltage is being output from 2.

The problem that a large peak current flows in the power supply circuit P shown in FIG. 15 also occurs in the power supply circuit P1 shown in FIG. However, in the power supply circuit P1 configured as shown in FIG. 17, the capacitors C1 and C2 absorb a part of the peak current or supply the current so as to compensate the peak current and smooth the output current. Has been realized. Therefore, the characteristics of the DC power supplies 1 and 2 for eliminating the peak current may be lower than the characteristics of the power supply circuit P shown in FIG. However, if the capacities of the capacitors C1 and C2 are increased in order to bear the peak current, the capacitors C1 and C having a large capacity will be used.
The electric charge charged in 2 flows back to the DC power supplies 1 and 2, and the effect of compensating for the peak current cannot be great. Furthermore, it causes an unnecessary increase in power consumption.

The present invention has been made to solve the above problems, and a first object thereof is to simplify the structure,
An object of the present invention is to provide a power supply circuit that is downsized and that can reduce power consumption. A second object of the present invention is to make it possible to supply all of the peak current at the time of switching the level of the power supply voltage from the power storage means, and thereby to significantly reduce the current capacity of the power supply. Is to provide.

[0021]

The power supply circuit of the present invention has a first AC waveform that oscillates between a first level and a second level.
A first power supply that outputs a voltage to a power supply line connected to a load, a second power supply that outputs a second voltage of a predetermined voltage level, and a third power supply that outputs a third voltage of a predetermined voltage level.
A power source, a first switch connected to the power source line in parallel with each other, the power storage means connected between the first switch and a second power source, and the power storage means in parallel with the first switch. A second switch connected between the first power source and the third power source;
The switch and the second switch are in a conducting state and a shut-off state, respectively, and are opposite to each other, and the storage means is in a period including a period in which the storage means is connected to the first power source by the first switch. Is cut off from the third power supply by the second switch, and the power storage means is switched to the third power supply by the second switch during a period included in the period in which the power storage means is cut off from the first power supply by the first switch. It is provided with a control means for controlling the first switch and the second switch so as to be connected, whereby the above object can be achieved.

In the present invention, the control means is configured such that when the power storage means is connected to the first power supply, the first voltage from the first power supply is between the first level and the second level. There is a case where a part of the charge / discharge charge with the load at the time of switching the level of the first voltage is selected immediately after switching and is supplied from the storage means.

In the present invention, a plurality of the storage means are used, and the control means uses the first voltage from the first power source as the first voltage.
A part of the plurality of power storage means is connected to the first power source only during the time period of the level, and the plurality of power storage means only during the time period when the first voltage from the first power source is at the second level. May connect the remaining portion of the to the first power source.

The power supply circuit of the present invention has a first level and a second level.
A first power supply that oscillates between levels and outputs a first voltage of an AC waveform having an output cutoff period to a power supply line between the first level period and the second level period, and a predetermined voltage A second power supply that outputs a second voltage of a level;
A third power supply outputting a third voltage having a voltage level near the level, and a fourth power supply having a voltage level near the second level
A fourth power source for outputting a voltage, a first switch and a second switch connected in parallel to the power source line, and a first switch
A first power storage means connected between the switch and the second power supply; a second power storage means connected between the second switch and the second power supply; and a first power storage means in parallel with the first switch. Third
A third switch connected between the power supply and the second switch, a fourth switch connected in parallel with the second power storage means and the fourth power supply, the first switch and the third switch,
During the period including the period of the first level of the first voltage on the power supply line, the conductive state and the cutoff state are controlled to be opposite to each other, and the power storage means is controlled by the first switch. The electricity storage means is cut off from the third power source by the third switch during the period of being connected to the power supply line, and the electricity storage means is cut off from the electricity line by the first switch. The means is connected to a third power supply by a third switch, and controls the first switch and the third switch to connect the power storage means to the power supply line during an output cutoff period of the first voltage,
Further, the second switch and the fourth switch are controlled so that the conductive state and the cutoff state are opposite to each other in a period including a period in which the first voltage on the power supply line is the second level. Then, during a period in which the power storage means is connected to the power supply line by the second switch, the power storage means is disconnected from the third power source by the fourth switch, and the power storage means is disconnected from the power supply line by the second switch. The storage means is connected to the third power source by the fourth switch during the cutoff period, and the storage means is connected to the power supply line during the output cutoff period of the first voltage. A control means for controlling the second switch and the fourth switch is provided, whereby the above object can be achieved.

In the present invention, the first power source includes a plurality of DC power sources for outputting DC voltages of a plurality of mutually different levels, and a plurality of power storage means respectively connected to output terminals of the DC power sources. In some cases, a plurality of switches are provided between the plurality of power storage means and the power supply line.

In the present invention, the control means is the first
It is the timing at which the first voltage from the power source switches between the first level and the second level, and at either the timing immediately after or immediately after the DC power source connected to the power storage means is disconnected. And the first, second, third, and third power storage means are connected to the first power source.
The fourth switch may be controlled.

In the present invention, a DC power source may be used as the third power source and the fourth power source.

[0028]

The power supply circuit of the present invention has a first power supply, a second power supply, and a third power supply. The first power source is the first level and the second
The first voltage having an AC waveform that oscillates between the levels is output to the load. The second power source and the third power source respectively output a second voltage and a third voltage of a predetermined voltage level. The control means controls the first switch so that the power storage means is set to the first
Connect to power. In the period including the connection period, the control unit controls the second switch to disconnect the power storage unit from the third power source. On the other hand, during the period included in the period in which the control unit controls the first switch to disconnect the power storage unit from the first power source, the control unit controls the second switch to set the power storage unit to the first power source. 3 Connect to power supply.

Therefore, during the period when the power storage means is disconnected from the first power supply, the power storage means is connected to the third power supply which outputs the third voltage. As a result, during the shutoff period with the first power supply, a part of the charge / discharge charge when the first voltage from the first power supply performs the level inversion between the first level and the second level is eliminated. It is supplied from the power storage means. Accordingly, when all of the charge / discharge charges are supplied from the first power source,
The situation in which a type having a large current capacity has to be selected as the first power source is eliminated, and a small first power source having a small current capacity and a simple configuration can be adopted. Therefore, it is possible to realize a power supply circuit having a small current capacity, low current consumption, a simple configuration, and a small size.

Further, the power supply circuit of the present invention comprises a first power supply, a second power supply, a third power supply, and a fourth power supply. The first power supply oscillates between a first level and a second level, and supplies a first voltage of an AC waveform having an output cutoff period between the first level period and the second level period to the power supply line. Output to. The second power supply outputs a second voltage having a predetermined voltage level. The third power supply outputs a third voltage having a voltage level near the first level. The fourth power supply outputs a fourth voltage having a voltage level near the second level. The control means controls the first switch and the third switch to connect the power storage means to the power supply line by the first switch during a period including a period in which the first voltage on the power supply line is at the first level. . While the power storage means is connected to the power supply line, the power storage means is cut off from the third power supply by the third switch.

The first voltage on the power line is the first
During the period including the level period, the power storage unit is cut off from the power supply line by the first switch. While the power storage means is disconnected from the power supply line, the power storage means is connected to the third power supply by the third switch. The control means connects the power storage means to the power supply line during the output cutoff period of the first voltage.

Further, the control means controls the second switch and the fourth switch, and the storage means is controlled to the second level during a period including a period in which the first voltage on the power supply line is at the second level. The switch connects to the power supply line. While the power storage means is connected to the power supply line, the power storage means is cut off from the third power supply by the fourth switch. On the other hand, during a period in which the power storage means is cut off from the power supply line by the second switch, the power storage means is connected to the third power supply by the fourth switch. Further, during the output cutoff period of the first voltage, the storage means is connected to the power supply line. Thus, by appropriately controlling the switching timing of each switch that controls the connection between the power storage means and the power supply line and the connection with each power supply, the load at the time of level switching between the first level and the second level is controlled. All or most of the sudden charge / discharge current is supplied from the power storage means. Thereby, when all of the charge / discharge charges are supplied from the first power supply, the situation in which the type having a large current capacity has to be selected as the first power supply is solved, the current capacity is small, and the configuration is simple. A small first power source can be adopted. Therefore, it is possible to realize a power supply circuit having a small current capacity, low current consumption, a simple configuration, and a small size.

[0033]

EXAMPLES Examples of the present invention will be described below. In this embodiment, a matrix type liquid crystal display device will be described as an example of a display device, but the present invention can be applied to other types of display devices.

FIG. 1 shows a power supply circuit 11 according to an embodiment of the present invention provided in a data driving circuit 13 according to an embodiment of the present invention.
2 is a block diagram of an active matrix liquid crystal display device (hereinafter, display device) 12 in which the data driving circuit 13 is used, and FIG. 3 is a block diagram of the data driving circuit 13. The present embodiment is characterized by the configuration of the power supply circuit 11 shown in FIG.

The power supply circuit 11 of this embodiment is, for example,
It is used for a flat panel display device, especially a power supply circuit for gradation display of a data drive circuit of a liquid crystal display device or a power supply circuit for driving a common electrode. The power supply circuit 11 includes a voltage source and a storage means such as a capacitor as described later.
The connection / disconnection of the power storage means to the voltage source is controlled by the switch means, and when the power storage means is disconnected from the voltage source, it is connected to another circuit having a certain potential. As a result, a functional feature is that a part of the charge / discharge charge between the output of the voltage source and the load when the level is switched is supplied from the storage means.

As shown in FIG. 2, the display unit 15 of the display device 12 has M × N picture elements P (j, i) arranged in M rows and N columns.
(J = 1,2, ..., M; i = 1,2, ..., N) and switching elements T (j, i) (j) respectively connected to the picture elements P (j, i). = 1,2, ...,
M; i = 1,2, ..., N). A drive circuit 16 for driving the display unit 15 is configured to include the data drive circuit 13 and the scanning circuit 14. The N data lines Oi (i = 1,2, ..., N) in the display unit 15 are output terminals S (i) (i = 1,2, ... , N) and the switching element T (j, i) are individually connected. Display 1
The M scanning lines Lj (j = 1,2, ..., M) in 5 are connected to the output terminal G (j) (j = 1,2, ..., M) of the scanning circuit 14 and The switching elements T (j, i) are connected to each other.

A thin film transistor (TFT) can be used as the switching element T (j, i). Other switching elements may be used. In the following description, the switching element is a thin film transistor, so the scanning line Lj is referred to as a gate line Lj, and the scanning circuit 14 is referred to as the gate drive circuit 1.
Called 4.

From the output terminal G (j) of the gate drive circuit 14, a voltage whose voltage level is high is sequentially output to the gate line Lj during a specific period. Hereinafter, the specific period is defined as one horizontal scanning period jH (j = 1, 2, ..., M,
When collectively referred to, it is indicated by a symbol H). Also, the variable j =
A period obtained by adding all the lengths of one horizontal period jH over 1, 2, ..., M is called one vertical scanning period.

When the voltage level of the gate signal output from the output terminal G (j) to the gate line Lj is high level, the switching element T (j, i) is turned on. When the switching element T (j, i) is in the ON state, the picture element P
(j, i) is charged according to the voltage output from the output terminal S (i) of the data driving circuit 3 to the data line Oi. The voltage level of the charged voltage is maintained at a constant voltage level during the one vertical period, and the voltage of the voltage level is maintained at the pixel P (j,
i) is applied.

FIG. 3 is a block diagram showing the internal structure of the data driving circuit 13. Hereinafter, a case where the image data is composed of 3 bits (D ₀ , D ₁ , D ₂ ) will be exemplified. That is, the image signal data has eight kinds of values of 0 to 7, and the signal voltage applied to each picture element is the external gradation voltage V ₀ , V input from the power supply circuit 11 of this embodiment. ₂ ,
Four levels of V ₅ and V ₇ , and the external gradation voltage V ₀ ,
The gradation voltage is one level or a plurality of levels between the pair of external gradation voltages generated from any one pair of external gradation voltages of V ₂ , V ₅ , and V ₇ .

The data driving circuit 13 is provided for each bit (D ₀ , D ₁ , D ₂ ) of the image data, and the first-stage D-type flip-flop M _{SM P} used for sampling operation, The second-stage D-type flip-flop M _H used for the hold operation, the selection control circuit SCOL, the power supply 11, and the four kinds of external power supply voltages V _{0 to} V ₇ and the data line Oi, respectively. Provided analog switch AS
It is configured to include W ₀ , ASW ₂ , ASW ₅ , and ASW ₇ . In the analog switches ASW _{0 to} ASW ₇ , four types of external gradation voltages V ₀ , ..., V ₇ and control signals S ₀ , S ₂ , S ₅ , S ₇ from the selection control circuit SCOL are provided. Is entered. Further, the selection control circuit SCOL is supplied with a signal t ₃ having a predetermined duty ratio.

In the data drive circuit 13 shown in FIG.
The number of external gradation voltages that need to be supplied from the outside in order to realize gradation display is reduced to four, which is half that in the conventional data drive circuit shown in FIG. . In the present data drive circuit 13, the gradation voltage V1,
The outputs corresponding to V3, V4, and V6 are created by the oscillating voltage driving method.

The value of the image signal data is "1, 2, 5, 7".
, Any one of the external grayscale voltages V ₀ , ..., V ₇ input from the outside is applied to the data line On.
Is output to. The value of the image signal data is "1, 2, 5,
7 ", a pair of gradation voltages of the external gradation voltages V ₀ , ..., V ₇ and the duty signal t.
Based on 3, the vibration signal of appropriate vibration frequency and duty is created. An oscillating voltage oscillating between the pair of gradation voltages is output to the data line On based on the oscillating frequency and the duty of the oscillating signal. When this oscillating voltage is averaged over time, the external gradation voltage V ₀ ,
, V ₇ and gray scale voltages V ₁ , V ₃ , V ₄ , and V ₆ are obtained. In this way, it is possible to realize a display level of 8 gradations from the external gradation voltages V ₀ , ..., V _{7 of} 4 levels.

The structure of the power supply circuit 11 of this embodiment provided in the data drive circuit 13 is shown in FIG. The power supply circuit 11 includes a power supply 17. A control signal POL that switches between a high level and a low level every horizontal scanning period H is input to the power supply 17. The power supply 17 outputs a power supply voltage having a rectangular wave or an AC waveform corresponding thereto, and may have the same configuration as that of the power supply circuit P shown in FIG. 15, for example. The power supply line 18 is connected to the power supply 17, and the power supply line 1
Reference numeral 8 denotes the analog switches ASW0 and ASW shown in FIG.
2, the data line O via ASW5 and ASW7
i, each switching element T (j, i), each picture element P (j, i), etc. are connected to a load 19.

The terminal 20a of the capacitor C1 is connected to the power supply line 18 via the switch SW1, and the other terminal 20b of the capacitor C1 is connected to the power supply 25 which outputs a predetermined potential Vy. In addition, the power line 18
To the terminal 21 of the capacitor C2 via the switch SW2.
a is connected, and the other terminal 21b of the capacitor C2 is connected to the power supply 25. Terminal 20a of capacitor C1
Is connected to a power supply 26 that outputs a predetermined potential Vy1 via a switch SW3, and is connected to a terminal 2 of a capacitor C2.
1a is a predetermined potential Vy via the switch SW4
It is connected to a power supply 27 that outputs 2.

The control signal POL corresponds to the data driving circuit 1
3 or a control circuit 23 provided outside the driving circuit 16 and input to the power supply 17, and the switches SW1 and SW4 are turned on (conducting) and off (cutting off). ) Is input to the switches SW1 and SW4 as a control signal. The polarity of the control signal POL is inverted by the inversion circuit 22, so that the inversion control signal / POL (hereinafter, the symbol “/” is a symbol that indicates the inversion of the signal) is switched by the switch SW2,
A control signal for switching between the ON state and the OFF state of SW3 is input to the switches SW2 and SW3. The switches SW1 to SW4 are turned on when the control signal POL or the inverted control signal / POL is at high level,
It turns off when the level is low. This control signal PO
L or inverted control signal / POL level and each switch SW
The relationship with the ON / OFF states of 1 to SW4 may be the reverse of the above.

The switches SW1 and SW2 have control signals POL whose polarities are inverted every horizontal scanning period H as described above.
During the high level or low level period, the capacitors are turned on, and the capacitors C1 and C2 are connected to the power supply line 18 during the respective periods. Capacitor C
While the switches C1 and C2 are cut off from the power supply line 18 from the power supply 17 by the switches SW1 and SW2, the capacitors C1 and C2 are connected to the other power supplies 26 and 27 by the switches SW3 and SW4, respectively. .

In the present embodiment, the power supply circuit 1 is used regardless of the structure of the power supply 17.
The effect of enabling the design of the peak current characteristic in the current from 1 to the load 19 to be small is realized. In the following description, the power supply 17 is the power supply circuit P shown in FIG.
Description will be made assuming a case having the same configuration as.

FIG. 4 is a timing diagram illustrating the operation of power supply circuit 11 shown in FIG. Here, the control signal P
When OL is at a high level, it is the time period when the picture element P shown in FIG. 2 is charged to the positive polarity, and when it is at the low level, it is the time period when the picture element P is charged to the negative polarity. Further, the power supply 17 switches between the positive polarity and the negative polarity of the output voltage according to the level of the control signal POL.

In FIG. 4, when the control signal POL is at a low level, the output voltage of the power supply 17 becomes negative, the switches SW2 and SW3 are turned on, and the switches SW1 and SW are turned on.
4 turns off. As a result, the capacitor C1 is charged to the potential Vy1 that is set to a potential close to the potential of the output voltage from the power source 17 in the positive time period of the power source 17. The capacitor C2 is connected to the power supply line 18.

Next, the control signal POL goes high and the output voltage of the power supply 17 becomes positive, and the switch SW1 and
SW4 is turned on and switches SW2 and SW3 are turned off.
When the switch SW1 is turned on, the capacitor C
1 is connected to the power supply line 18 and is charged with the output potential from the power supply 17. Here, since the capacitor C1 is charged with the potential Vy1, the capacitor C1 and the load 19 including the data line Oi shown in FIG. Therefore, when the charging current or the discharging current of the load 19 fluctuates rapidly, the fluctuation current is supplied by the power supply 17 and the capacitor C1. At this time, the capacitor C2 is connected to the power source 17
Is charged to a potential Vy2 that is set to a potential close to the potential of the output voltage from the power supply 17 in the negative time period of.

When the control signal POL becomes low level again, the output voltage of the power supply 17 becomes negative, the switches SW2 and SW3 are turned on, and the switches SW1 and S are turned on.
W4 is turned off. As a result, the capacitor C1 is charged to the potential Vy1 that is set to a potential close to the potential of the output voltage from the power source 17 in the positive time period of the power source 17. The capacitor C2 is connected to the power supply line 18. At this time, the capacitor C2 also constitutes a circuit that discharges or absorbs charges with the load 19 together with the power supply 17. Therefore,
As an example, during the period in which the capacitor C1 is cut off from the power source 17, the capacitor C1 has a potential Vy1 close to the level of the voltage output from the power source 17 in the period.
Is charged by. As a result, a part of the charge / discharge charge when the power supply voltage from the power supply 17 performs the level inversion between the first level and the second level, the capacitor C
Supplied from 1. As a result, when all of the charging / discharging charges are supplied from the power supply 17, the situation of having to select a type having a large current capacity as the power supply 17 is solved, the current capacity is small, and the configuration is simple and small. A power supply 17 can be adopted. Therefore, it is possible to realize the power supply circuit 11 having a small current capacity, low current consumption, a simple configuration, and a small size.

FIG. 5 shows a power supply circuit 11 according to the second embodiment of the present invention.
The circuit diagram of a is shown. This embodiment is similar to the first embodiment, and the same reference numerals are given to corresponding parts. In the present embodiment, FETs (field effect transistors, hereinafter referred to as transistors) Tr1, Tr2, Tr3 are provided as the switches in the first embodiment, which are arranged between the power source 17 and the capacitors C1 and C2. , Tr4 are used. The control signal POL and the inverted control signal / POL are converted by the level conversion circuit 24 from, for example, a TTL (transistor transistor circuit) level to a level suitable for controlling the FET.

Further, resistors r1 and r2 are respectively connected in series between the transistors Tr1 and Tr4 and the power supply line 18.
Are arranged. The resistors r1 and r2 are arranged as current limiting resistors. The reason is that the capacitor C1,
The resistances r1 and r2 are added to the current flowing out (flowing in) from C2.
This is to prevent the sudden outflow of an excessive electric charge by restricting by. As a result, the excessive current causes damage to the transistors Tr1 and Tr4 and the data line Oi.
It prevents the load 19 from being damaged. Further, with respect to the capacitors C1 and C2, it is also an object to prevent unnecessary consumption by absorbing the electric charge of the excessive current by the power supply 17 when the excessive current is generated. In addition,
The resistors r1 and r2 may be unnecessary depending on the characteristics of the FET or other switch element used.
The level conversion circuit 24 may be unnecessary depending on the characteristics of the FET used.

The following description is commonly related to the first and second embodiments. Power source voltage potentials Vy, Vy1, Vy output from the power sources 25, 26, 27, respectively.
2 will be described. As a basic idea when determining the potentials Vy, Vy1 and Vy2, the power supply circuits 26 and 27 output the potentials Vy1 and Vy2 as described above.
It is desirable to use a power supply circuit in which the output from the power supply 17 has a stable potential as close as possible to the potentials in the positive polarity time period and the negative polarity time period, respectively. Further, the electric potential Vy output from the power supply 25 is the electric potentials Vy1 and Vy of the both.
It is desirable that the potential be in the middle of y2.

In the actually applied power supply circuit, the potentials of the respective potentials Vy, Vy1 and Vy2 are not necessarily limited to the potentials of the desirable example. Load 1 at the time of switching the positive / negative of the power supply voltage from the power supply 17
If the combination is such that a part of the charging / discharging current of the battery 9 and the power supply 17 can be borne by the above-mentioned operation, the respective potentials Vy, Vy1, Vy2 have practically a large degree of freedom. forgiven. Therefore, only for the purpose of realizing the present invention, in the display device 12 including the power supply circuits 11 and 11a of the present embodiment, new power supplies 25, 26 and 27 are provided, and new potentials Vy and Vy1, In principle, there is no need to define Vy2.

FIG. 6 shows a power supply circuit 1 according to the third embodiment of the present invention.
1b shows a circuit diagram. In the second embodiment, the power source 25
If two kinds of potential Vy of the output from are prepared, the degree of freedom of design is further expanded. In this embodiment, the potential Vya and the potential Vyb are used as the potential Vy. Power supply circuit 11b of FIG.
Are, for example, the potential Vya = 0V and the potential Vyb, respectively.
It is a circuit diagram when it is set to = Vdd (+ 5V).

In this embodiment, when the control signal POL is at low level, the output voltage of the power supply 17 becomes negative, the switches SW2 and SW3 are turned on, and the switches SW1 and S1 are turned on.
W4 is turned off. As a result, the capacitor C1 is charged with the potential difference between the ground potential and the voltage Vy1 which is set to a potential close to the potential of the output voltage from the power supply 17 in the positive time period of the power supply 17. The capacitor C2 is connected to the power line 18
Connected to.

Next, the control signal POL goes high and the output voltage of the power supply 17 becomes positive, and the switches SW1 and
SW4 is turned on and switches SW2 and SW3 are turned off.
When the switch SW1 is turned on, the capacitor C
1 is connected to the power supply line 18 and is charged with the output potential from the power supply 17. Here, since the capacitor C1 is charged by the potential difference between the voltage Vy1 and the ground potential, the capacitor C1 is connected to the load 19 including the data line Oi shown in FIG. Configured with 17. Therefore, when the charging current or the discharging current of the load 19 fluctuates rapidly, the fluctuation current is supplied by the power supply 17 and the capacitor C1. At this time, the capacitor C2 is charged with the potential difference between the drive potential Vdd and the potential Vy2 that is set to a potential close to the potential of the output voltage from the power supply 17 in the negative time period of the power supply 17.

When the control signal POL becomes low level again, the output voltage of the power supply 17 becomes negative, the switches SW2 and SW3 are turned on, and the switches SW1 and S1 are turned on.
W4 is turned off. As a result, the capacitor C1 is charged by the potential difference between the potential Vy1 and the ground potential. The capacitor C2 is connected to the power supply line 18. At this time, the capacitor C2 also constitutes a circuit that discharges or absorbs charges with the load 19 together with the power supply 17.

In this way, the effects described in the above embodiment can be achieved even by using the power supply circuit 11b having the structure shown in FIG. Further, as the potential Vy, the ground potential and the drive voltage V
Since dd is used, it is not necessary to use a new circuit as the potential Vy, and the configuration of the power supply circuit 11b is simplified.

FIG. 7 shows a power supply circuit 1 according to the fourth embodiment of the present invention.
It is a circuit diagram which shows the electric constitution of 1c. This embodiment is similar to the third embodiment, and the corresponding parts are designated by the same reference numerals. The features of this embodiment are as follows. That is, the power supply circuit of this embodiment includes two DC power supplies, a switch, and a capacitor connected to a power supply line connected to the output side of the switch, and the two DC power supplies are alternately switched by the switch. Thus, an AC voltage is created as the output of the power supply circuit. Further, the connection timing of the capacitor to the power supply line and the switch switching time are appropriately controlled. As a result, all or most of the sudden charge / discharge current of the load at the time of switching between the positive polarity and the negative polarity of the output voltage on the power supply line is supplied from the capacitor.

The power supply circuit 11c of this embodiment includes two DC power supplies 17a and 17b. The DC power supply 17a outputs a predetermined potential V1, and the DC power supply 17b outputs a predetermined potential V2 different from the potential V1.
These potentials V1 and V2 may be selected as potentials having the same absolute value and opposite polarities.

The power supply lines 28, 29 from the DC power supplies 17a, 17b are connected to a power supply 31 for outputting a predetermined potential Vy via capacitors C11, C12 in parallel with the power supply lines 28, 29, respectively. ing. Each power supply line 28, 29 has a switch SW11, S
It is connected to the common power supply line 30 via each W12. Each of the switches SW11 and SW12 is switched on / off by control signals CS11 and CS12 described later.

The common power supply line 30 is connected to the load 19. The common power line 30 is connected to the potential Vy via the series circuit of the switch SW14 and the capacitor C13.
Is connected to a power supply 31 that outputs Further, the common power supply line 30 is connected to the power supply 31 via a series circuit of the switch SW16 and the capacitor C14.

The connection terminal of the capacitor C13 with the switch SW14 is connected via the switch SW13 to the power source 32 which outputs a predetermined potential Vy1.
The connection terminal of the switch SW16 of 14 is a switch SW.
A power supply 3 for outputting a predetermined potential Vy2 via 15
Connected to 3. Each switch SW13, SW14,
SW15 and SW16 are control signals CS13 and CS14,
ON / OFF is controlled by CS15 and CS16.
Each of the control signals CS11 to CS16 has a high level / low level switching timing, which will be described later, based on the control signal POL which is the same as the control signal POL in each of the embodiments. Is generated at.

FIG. 8 is a timing chart for explaining the operation of the power supply circuit 11c of this embodiment. 8 (1) to 8 (7), the control signal POL and each control signal CS1 are shown.
The mutual timing relationship of 1-CS16 is shown. As shown in FIG. 8A, the control signal POL is a signal that repeats a high level period and a low level period for each horizontal scanning period H. The control signal CS11 is, as shown in FIG.
High-level period T1 of time t1 to t2 of control signal POL
Rises at time t3 after the elapse of a predetermined delay period T3 from the rise timing t1 in FIG.
It is a signal that simultaneously falls at the timing of L falling.

As shown in FIG. 8C, the control signal CS12 simultaneously falls at the rising timing t1 of the control signal POL, and at time t4 after a lapse of a predetermined delay period T4 from the falling timing t2 of the control signal POL. It is a rising signal. The control signal CS13 is shown in FIG.
As shown in (4), in the low level period of the control signal CS11, only the period T13 from the time t1 when the control signal CS12 falls to the time t3 when the control signal CS11 next rises, and the remaining period Is a rising signal. As shown in FIG. 8 (5), the control signal CS14 is an inverted signal of the control signal CS13, and the same period as the low level period T13 of the control signal CS13 is a low level period T14. The control signal CS15 is shown in FIG.
As shown in (6), in the low level period of the control signal CS12, only the period T15 from the time t2 when the control signal CS11 falls to the time t4 when the control signal CS12 next rises, and the remaining period Is a rising signal. As shown in FIG. 8 (7), the control signal CS16 is an inverted signal of the control signal CS15, and the same period as the low level period T15 of the control signal CS15 is a high level period T16.

The outline of the operation of this embodiment will be described below.
When the control signal CS11 is at high level, the switch SW1
1 is connected to the DC power supply V1 side, and the power supply potential V1 corresponding to the positive polarity is output to the common power supply line 30.
During this period, the switch SW15 is also turned on, and the capacitor C14 is charged by the potential Vy2 which is selected as a potential close to the DC power source V2 in principle. Control signal P
At time t2 when OL becomes low level, DC power supply V1
Are disconnected from the common power line 30. At the same time as time t3, the capacitor C14 is disconnected from the potential Vy2,
It is connected to the common power supply line 30.

At this time, the capacitor C14 has the power supply potential V1.
Is charged to a potential Vy2 having a value close to, and both the DC power supplies 17a and 17b are disconnected from the common power supply line 30. Therefore, the charge to be charged and discharged is exchanged only between the load 19 and the capacitor C14. After the transient state of the period T4 at this time ends, the switch SW12 is turned on, the DC power supply 17b is connected to the common power supply line 30, and the power supply potential V2 is output to the common power supply line 30. Further, at this time, the capacitor C14 is disconnected from the common power supply line 30, is connected to the power supply potential Vy2 again, and is recharged in preparation for the next.

When the control signal POL changes from the low level to the high level, the capacitor C13 changes to the capacitor C14.
The operation similar to that described above is performed.

Therefore, the DC power supplies 17a and 17b connected to the common power supply line 18 connected to the load 19 are
At both the timing of switching from the DC power supply 17a to the DC power supply 17b and the timing of switching from the DC power supply 17b to the DC power supply 17a, both of the DC power supplies 17a and 17b are cut off from the common power supply line 18. The periods T3 and T4 are provided. During this period T3 and T4, the common power supply line 18
Are connected to capacitors C13 and C14.

Therefore, in this embodiment, it is possible to achieve the same effects as the effects described in the above embodiments. In the present embodiment, the load 1 is further connected to the common power line 18.
It is possible to supply all of the peak currents generated when the polarity of the power supply voltage supplied to 9 is switched between positive and negative by the capacitors C13 and C14. This eliminates the need for the DC power supplies 17a and 17b to partially bear the peak current. Therefore, the DC power supply 17a,
The current capacity characteristic of 17b can be remarkably suppressed.

FIG. 9 shows a power supply circuit 11 according to the fifth embodiment of the present invention.
It is a circuit diagram of d. The present embodiment is similar to each of the above-described embodiments, and corresponding parts are designated by the same reference numerals. This embodiment uses transistors Tr11 to Tr16 formed of FETs as the switches SW11 to SW16 in the power supply circuit 11c of the fourth embodiment. The transistors Tr11 and Tr12 are on / off controlled by control signals CS11 and CS12. Transistors Tr14, Tr16
Is on / off controlled by control signals CS14 and CS16. The transistors Tr13 and Tr15 have control signals CS
14 and CS16 are on / off controlled by inversion control signals / CS14 and / CS16 which are inverted by inversion circuits 35 and 36, respectively.

In FIG. 9, transistors Tr13, T
r14 is connected via a capacitor C13, and the transistors Tr15 and Tr16 are connected via a capacitor C14 to a power supply 37 that outputs a predetermined potential Vy3. In addition, the common power line 30 and the transistor Tr1
Resistors r1 and r2 are connected between 4 and Tr16, respectively. Here, the resistance values of the resistors r1 and r2 may be the same. The resistors r1 and r2 are capacitors C1
3, a resistor for limiting the inrush current flowing from C14 to the load 19. The resistors r1 and r2 may be unnecessary depending on the value of the ON resistance of the switching element such as the TFT used.

Even in such an embodiment, the same effects as those described in the above-mentioned embodiments can be achieved.

FIG. 10 shows a power supply circuit 1 according to the sixth embodiment of the present invention.
The circuit diagram of 1e is shown. In the power supply circuit 11e of the present embodiment, the GND (ground potential) of the power supply circuit 11e is used as the potential Vy1, and the drive voltage Vdd is used as the potential Vy2. Further, as the potential Vy3, two kinds of potentials Vdd,
Using GND, the potential Vdd is connected to the capacitor C13, and the potential GND is connected to the capacitor C14.

In each of the fourth, fifth and sixth embodiments, the positive and negative output voltages from the DC power supplies 17a and 17b output to the common power supply line 30 as the potentials Vy1 and Vy2, respectively. Basically, the potential is close to. In reality, such potentials Vy1 and Vy2 are not always required.
The setting is not limited to.

FIG. 11 shows a power supply circuit 1 according to the seventh embodiment of the present invention.
The circuit diagram of 1f is shown. The present embodiment is similar to each of the above-described embodiments, and corresponding parts are designated by the same reference numerals. The feature of the power supply circuit 11f of this embodiment is that the ground potential G of the transistor Tr13 in the power supply circuit 11e shown in FIG.
This is because the terminal connected to ND is connected to the power supply line 29 from the DC power supply 17b, and the drive voltage Vd of the transistor Tr15 in the power supply circuit 11e.
That is, the terminal connected to d is connected to the power supply line 28 from the DC power supply 17a. The terminal of the capacitor C13 connected to the drive voltage Vdd is connected to the power supply line 28, and the terminal of the capacitor C14 connected to the ground potential GND is connected to the power supply line 29. Is.

With the power supply circuit 11f having such a configuration, it is possible to achieve the same effects as those described in each of the above embodiments.

The following effects can be realized by the power supply circuits 11c to 11f of the fourth to seventh embodiments.

In a power supply circuit which outputs an AC voltage such as a rectangular wave by a circuit composed of two DC power supplies 17a and 17b and two switches SW1 and SW2,
Most of the charging / discharging current with the load 19 at the time of switching the positive polarity and the negative polarity of the AC voltage can be supplied by the capacitor. As a result, the current capacity characteristic for the peak current of the DC power supply for creating the rectangular wave can be significantly reduced.

The degree of reduction is 1/10 or more. Therefore, the price of the original DC power supply can be greatly reduced.

Nevertheless, the power supply circuits 11c to 11f of the fourth to seventh embodiments can have their rising characteristics made extremely steep.

As a result, each of the power supply circuits 11c-11
This is useful for improving the display quality in the display device 12 using f.

Further, the power supply circuits 11c to 11c of the above-mentioned respective embodiments.
11f supplies electric charges to the capacitors C11 to C14,
It is possible to use the power supply circuits 11c to 11f, the generation circuit and the supply circuit of the drive voltage Vdd in the display device 12, or the ground circuit as they are. This eliminates the need to use a circuit for generating and supplying a new power supply voltage and a new ground circuit, and simplifies the circuit configuration.

In such a case, useless power consumption due to the charge supply is minimized, and further the power consumption for driving the original DC power source itself is also small. Therefore, as a whole, it is possible to largely reduce the power consumption which is originally unnecessary for driving the display unit 15.

In the first to third embodiments, the current capacity characteristic relating to the peak current of the power source 17 can be remarkably suppressed. In each embodiment, when the power supply 17 includes an operational amplifier, an inexpensive operational amplifier having a small slew rate can be used. Therefore, depending on the specifications of the operational amplifier, the current amplification circuit in the subsequent stage is unnecessary, and the overall configuration is simplified, downsized, and the price is reduced.
In addition, it is possible to realize a voltage source circuit with low power consumption by eliminating unnecessary power consumption.

[0089]

As described above, according to the present invention, a part of the charge / discharge current at the time of switching the level between the first level and the second level can be supplied by the storage means. Therefore, the specifications for the peak current of the power supply circuit can be significantly reduced. Therefore, an expensive operational amplifier having a large slew rate and a large capacity, which has been conventionally required, can be configured with a large capacity and an inexpensive one even if the slew rate is low. Further, it is possible to eliminate the need for a current amplification circuit such as a transistor which has been conventionally required.

Therefore, according to the present invention, Cost reduction.

2. Reduction of power consumption.

3. Further, it is possible to realize a voltage source in which the rising characteristic is improved and the voltage is stabilized during the periods of the first level and the second level of the first power supply voltage.

4. Therefore, while giving each of the above effects,
Further, the display quality of the display unit is improved. According to the invention,
In the power supply circuit that outputs an AC voltage, most of the charging / discharging current with the load at the time of level switching can be supplied by the storage means.

As a result, the specifications for the peak current of the power supply that creates the AC voltage can be greatly reduced. The degree of reduction is 1/10 or more, and therefore the price of the original DC power supply can be greatly reduced.

Nevertheless, the power supply constructed according to the present invention can have a very excellent rising characteristic. As a result, it is useful for improving the display quality. Furthermore, the present invention relates to the charge supply to the storage means,
It is possible to use the drive current of the entire circuit and the ground circuit as they are. In that case, the wasteful power consumption associated with the charge supply is minimized. Furthermore, since the power consumption for driving the power supply is small, it is possible to greatly reduce the power consumption that is not directly required for driving the display means as a whole.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a power supply circuit 11 according to a first embodiment of the present invention.

FIG. 2 is a display device 12 in which a data driving circuit 13 is used.
It is a block diagram of.

FIG. 3 is a block diagram of a data driving circuit 13.

FIG. 4 is a timing chart illustrating the operation of the power supply circuit 11.

FIG. 5 is a circuit diagram of a power supply circuit 11a according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram of a power supply circuit 11b according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a power supply circuit 11c according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart explaining the operation of the power supply circuit 11c of the present embodiment.

FIG. 9 is a circuit diagram of a power supply circuit 11d according to a fifth embodiment of the present invention.

FIG. 10 is a circuit diagram of a power supply circuit 11e according to a sixth embodiment of the present invention.

FIG. 11 is a circuit diagram of a power supply circuit 11f according to a seventh embodiment of the present invention.

FIG. 12 is a block diagram of a conventional data driving circuit.

FIG. 13 is a waveform diagram showing an example of waveforms of external gradation voltages V0 and V7 together with a waveform of a common electrode drive signal Vcom.

FIG. 14 is a waveform diagram separately showing the waveform examples of the external gradation voltages V0 and V7 and the waveform example of the common electrode drive signal Vcom.

FIG. 15 is a circuit diagram of a conventional power supply circuit.

FIG. 16 is an equivalent circuit diagram of a data line when viewed as a load.

FIG. 17 is a circuit diagram of a power supply circuit P1 that can obtain the same effect as that of the power supply circuit P.

[Explanation of symbols]

11, 11a, 11b, 11c, 11d, 11e, 11
f power supply circuit 12 display device 13 data drive circuit 15 display section 16 drive circuit 17, 31, 32, 33 power supply 17a, 17b DC power supply 18, 28, 29 power supply line 19 load 23 control circuit 24 level conversion circuit 30 common power supply line 34 Signal generation circuit

Claims (7)

[Claims] 1. A first power supply for outputting a first voltage of an AC waveform oscillating between a first level and a second level to a power supply line connected to a load, and a second voltage of a predetermined voltage level. A second power supply, a third power supply outputting a third voltage of a predetermined voltage level, a first switch connected in parallel to the power supply line, and a connection between the first switch and the second power supply The stored electricity storage means, the second switch connected between the electricity storage means and a third power source in parallel with the first switch, the first switch and the second switch, respectively, in a conductive state and a cutoff state. Are opposite to each other, and the storage means is connected to the third switch by the second switch during a period including a period in which the storage means is connected to the first power source by the first switch.
The power storage means is connected to the third power supply by the second switch during a period included in a period in which the power storage means is cut off and the power storage means is cut off from the first power supply by the first switch. A power supply circuit comprising: a control means for controlling the first switch and the second switch. 2. The control means determines when the first voltage from the first power supply is the first voltage when the power storage means is connected to the first power supply.
Immediately after switching between level and second level, choose
2. The power supply circuit according to claim 1, wherein a part of the charge / discharge charge with the load at the time of switching the level of the first voltage is supplied from the storage means. 3. A plurality of the storage means are used, and the control means controls a part of the plurality of storage means only when the first voltage from the first power source is at a first level. The power source according to claim 2, wherein the power source is connected to one power source, and the remaining portions of the plurality of power storage means are connected to the first power source only when the first voltage from the first power source is at the second level. circuit. 4. A power supply line that oscillates between a first level and a second level, and has a first voltage of an AC waveform having an output cutoff period between the period of the first level and the period of the second level. A second power supply for outputting a second voltage having a predetermined voltage level, a third power supply for outputting a third voltage having a voltage level near the first level, and a second power supply for the second level A fourth power supply outputting a fourth voltage having a voltage level of, a first switch and a second switch connected in parallel to each other on the power supply line, and connected between the first switch and the second power supply. A first power storage means, a second power storage means connected between the second switch and the second power supply, and a first power storage means connected in parallel with the first switch between the first power storage means and the third power supply. The third switch, the second switch, and the second power storage means and the fourth power source in parallel. A fourth switch connected between the first switch and the third switch, and a first switch and a third switch in a conductive state and a cutoff state, respectively, in a period including a period in which the first level of the first voltage on the power supply line is included. Are controlled so that they are opposite to each other, and during a period in which the power storage means is connected to the power supply line by the first switch, the power storage means is cut off from the third power supply by the third switch, During the period when the means is cut off from the power supply line by the first switch, the storage means is turned on by the third switch by the third switch.
Connected to the power supply, during the output cutoff period of the first voltage,
The first switch and the third switch are controlled so as to connect the power storage means to the power supply line, and the second switch and the fourth switch are controlled by the second level of the first voltage on the power supply line. In a period including a certain period, the conduction state and the cutoff state are controlled to be opposite to each other, and the electricity storage means is connected to the power supply line by the second switch. The means is cut off from the third power supply by the fourth switch, and the storage means is cut off from the power supply line by the second switch,
The power storage means is connected to the third power supply by the fourth switch, and controls the second switch and the fourth switch so as to connect the power storage means to the power supply line during the output cutoff period of the first voltage. Power supply circuit including a control means for controlling. 5. The plurality of direct current power supplies, each of which outputs a plurality of mutually different levels of direct current voltage,
The power supply circuit according to claim 4, further comprising a plurality of power storage means connected to the output terminals of the respective DC power supplies, and a plurality of switches respectively connected between the plurality of power storage means and the power supply line. 6. The control means is a timing at which the first voltage from the first power supply switches between a first level and a second level, and the DC power supply connected to the power storage means until the timing is reached. At the same time as or immediately after the disconnection, the power storage means is set to the first
The power supply circuit according to claim 5, wherein the first, second, third, and fourth switches are controlled so as to be connected to a power supply. 7. The power supply circuit according to claim 4, wherein a DC power supply is used for the third power supply and the fourth power supply.