JP3568615B2 - Liquid crystal driving device, control method thereof, and liquid crystal display device - Google Patents

Liquid crystal driving device, control method thereof, and liquid crystal display device Download PDF

Info

Publication number
JP3568615B2
JP3568615B2 JP05901495A JP5901495A JP3568615B2 JP 3568615 B2 JP3568615 B2 JP 3568615B2 JP 05901495 A JP05901495 A JP 05901495A JP 5901495 A JP5901495 A JP 5901495A JP 3568615 B2 JP3568615 B2 JP 3568615B2
Authority
JP
Japan
Prior art keywords
voltage
liquid crystal
crystal display
precharge
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP05901495A
Other languages
Japanese (ja)
Other versions
JPH0876083A (en
Inventor
靖武 古越
和浩 岡本
敏光 峯村
博之 磯貝
Original Assignee
富士通ディスプレイテクノロジーズ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP15728694 priority Critical
Priority to JP6-157286 priority
Application filed by 富士通ディスプレイテクノロジーズ株式会社 filed Critical 富士通ディスプレイテクノロジーズ株式会社
Priority to JP05901495A priority patent/JP3568615B2/en
Publication of JPH0876083A publication Critical patent/JPH0876083A/en
Application granted granted Critical
Publication of JP3568615B2 publication Critical patent/JP3568615B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Description

[0001]
[Industrial applications]
The present invention relates to a liquid crystal driving device, a control method therefor, and a liquid crystal display device, and a driving circuit that uses a staircase waveform voltage as a gradation power supply to perform polarity inversion driving every horizontal period, a driving method thereof, and an active matrix type. Related to a liquid crystal display.
[0002]
2. Description of the Related Art In recent years, with the development of high integration and high density technology of a semiconductor integrated circuit (hereinafter referred to as LSI) device, an active matrix type liquid crystal display device (LCD: Liquid Crystal Display) provided with a TFT (Thin Film Transistor) for each pixel has been developed. Being manufactured. LCDs are spreading in a wide range of fields from home TVs to OA equipment. This is because the LCD can easily realize a thinner and lighter weight than the CRT and can obtain display quality not inferior to the CRT. In addition to portable information devices that take advantage of their small size and light weight, LCDs are expected as display devices for multimedia-compatible information devices. In the future, the ability to display more information with richer expressiveness will be required.
[0003]
[Prior art]
As shown in FIG. 15A, a multi-gradation liquid crystal display device that performs polarity inversion driving every one horizontal period includes a liquid crystal driving device 1 and a liquid crystal display panel 2. The display panel 2 has a TFT substrate 2A, a common electrode 2B, a data driver 3, a scan driver 4, and the like. The liquid crystal driving device 1 has a common voltage supply circuit 5 and a power supply circuit (not shown).
[0004]
The common voltage supply circuit 5 switches the common voltage VCOM ± every horizontal period, and supplies it to the common electrode 2B. As shown in FIG. 15B, the circuit 5 has switch elements SW1, SW2, an output buffer BF, and an inverter INV.
As shown in FIG. 16, the circuit 5 turns on SW1 and turns off SW2 during a horizontal period for displaying one line, for example, a line inversion signal LN = “H” level. As a result, the common voltage VCOM + is supplied from the output buffer BF to the common electrode 2B of the liquid crystal display panel 2.
[0005]
At this time, when VCOM + reaches a common voltage stabilization period within one horizontal period, the output signal VS of the scan driver 4 becomes “H” level, and, for example, four gradation voltages obtained by combining the reference voltages V0 to V7 are: The data is applied from the data driver 3 to the TFT substrate 2B of the liquid crystal display panel 2.
Here, the common voltage stabilization period is a period obtained by subtracting an unstable period (transition period) from one horizontal period, and indicates, for example, a range in which four grayscale voltages for a selected pixel are valid. The transition period is a period from the time when the line inversion signal LN rises to the time when the common voltage VCOM reaches a steady state.
[0006]
In FIG. 15B, when the line inversion signal LN goes to the “L” level to perform the polarity inversion drive, SW1 is turned off and SW2 is turned on. As a result, the common voltage VCOM- is supplied from the output buffer BF to the common electrode 2B of the liquid crystal display panel 2. The use of such alternating drive is to prevent deterioration and flicker of the liquid crystal itself.
[0007]
Further, when the TFT of the bus line selected by the scan driver 4 is turned on, the video signal voltage is written from the data driver 3 to each pixel electrode, and then the pixel electrode of the bus line is selected until the TFT of the bus line is selected. The charge is held in the distribution capacitance. In this state, the information is maintained, the tilt of the liquid crystal is determined correspondingly, the amount of transmitted light is controlled, and gradation display is performed.
[0008]
[Problems to be solved by the invention]
By the way, according to the conventional common voltage supply circuit 5, the switch element SW1 is turned on in synchronization with the rise of the line inversion signal LN, and the switch element SW2 is turned on in synchronization with the fall of the line inversion signal LN. In the method of controlling the switches SW1 and SW2 based on the signal LN, the transition period until VCOM + reaches the common voltage stabilization period on the positive side and the transition period until VCOM− reaches the common voltage stabilization period on the negative side have a transition period. It becomes longer and hinders early writing of information.
[0009]
This is because the potential held in the selected pixel is based on the common electrode voltage, and the common electrode capacitance and the common electrode resistance, and furthermore, the time constant for the resistance of the common electrode input terminal portion and the like are subject to the following. This is because the charging of the common voltage requires a certain period of time (transient period) or more, and the scan driver 4 cannot be quickly turned ON. The common electrode capacitance is generated between the TFT substrate 2A and the common electrode 2B.
[0010]
In general, when higher definition of a liquid crystal display device is required with an increase in the amount of information, this is dealt with by a method of shortening one horizontal period or increasing the number of pixels. To this end, it is necessary to stabilize the common electrode voltage at an early stage while the electrode capacitance increases.
However, in the grayscale control method using the distributed capacitance, as shown in FIG. 17, when one horizontal period is shortened to increase the definition of the liquid crystal display panel 2, the common voltage stable period is shortened. For example, it becomes difficult to charge the selected pixel with four gradation voltages. In order to avoid this, a method of shortening the pulse width per step of the reference voltages V0 to V7 is adopted, but there is a problem that insufficient charging of the gradation voltage occurs.
[0011]
Even in the case of multi-gradation display without using the distributed capacitance method, as shown in FIG. 18, as the one horizontal period becomes shorter, the same problem as the former gradation control method is encountered.
In addition, as the demand for higher definition and larger size of the liquid crystal display device increases with the increase in the amount of information, the resistance and capacitance of the gate electrode as well as the common electrode further increase.
[0012]
The present invention has been made in view of the problems of the conventional example, and prevents a shortage of charge in a circuit necessary for a liquid crystal display, allows a drive voltage to reach a target level during a precharge period, and provides a stable operation period. It is an object of the present invention to provide a liquid crystal driving device, a control method thereof, and a liquid crystal display device capable of increasing the length of the liquid crystal display device.
[0013]
[Means for Solving the Problems]
As shown in FIG. 1A, a liquid crystal driving device according to the present invention has a voltage generating circuit 100 for generating a driving voltage necessary for a liquid crystal display and a precharge voltage obtained by adding an auxiliary voltage to the driving voltage. When,
From the voltage generating circuit from the voltage generating circuit 100 A precharge voltage is output during a precharge period corresponding to a first control signal having one horizontal period required for liquid crystal display as one cycle, and then a drive voltage from the voltage generation circuit is supplied to the first control signal. A voltage output circuit for outputting a signal and a second control signal having a half period of one horizontal period necessary for liquid crystal display as a half cycle, and controlling the length and precharge voltage of the precharge period to control one horizontal period. Adjust the time period It is characterized by.
[0014]
As shown in FIG. 2A, the first device of the present invention preferably processes a positive power supply voltage to generate a positive drive voltage required for a liquid crystal display, and rises more rapidly than the drive voltage. A first control signal having a positive precharge voltage of one horizontal period B required for liquid crystal display as one cycle Precharge period according to A first voltage generating circuit 11 that superimposes the driving voltage on the basis of a negative power supply voltage to generate a negative driving voltage necessary for the liquid crystal display, and a negative voltage that falls more rapidly than the driving voltage. Precharge voltage The precharge period A second voltage generating circuit 12 that superimposes the driving voltage on the basis of the positive driving voltage superimposed on the positive precharging voltage from the first voltage generating circuit and the negative precharging voltage An output control circuit 13 that alternately outputs the negative drive voltage based on a second control signal having the one horizontal period B as a half cycle, Adjusting one horizontal period by controlling the length of the precharge period and the precharge voltage It is characterized by.
[0015]
In the second device of the present invention, as shown in FIG. 2B, preferably, the voltage output circuit 200 selects a positive drive voltage and a positive precharge voltage based on the first control signal. A first selection circuit 14 for combining and outputting the first driving signal and a negative precharge voltage based on the first control signal; The positive precharge voltage and the positive drive voltage synthesized and output from the selection circuit 14 and the negative precharge voltage and the positive drive voltage synthesized and output from the first selection circuit 15 are controlled by the second control. And an output control circuit 16 for alternately outputting the signals based on the signals.
[0016]
In the third device of the present invention, as shown in FIG. 3A, preferably, the voltage output circuit 200 outputs a positive drive voltage based on the signal logic of the first control signal and the second control signal. A first output circuit 17 for permitting the output of the first control signal, a second output circuit 18 for permitting the output of the negative drive voltage based on the signal logic of the first control signal and the second control signal, A third output circuit 19 that permits output of a positive precharge voltage based on the signal logic of the control signal and the second control signal; and a negative output based on the signal logic of the first control signal and the second control signal. And a fourth output circuit 20 for permitting output of the precharge voltage.
[0017]
In the first to third devices of the present invention, the voltage generation circuit 100 processes a positive or negative power supply voltage to generate a positive or negative common voltage VCOM necessary for a common electrode of an active matrix type liquid crystal display panel. And a positive or negative precharge voltage VPC ± obtained by adding an auxiliary voltage to the common voltage VCOM ±.
In the first to third devices of the present invention, the voltage generating circuit 100 processes a positive or negative power supply voltage to generate a positive or positive drive voltage necessary for a gate electrode of an active matrix type liquid crystal display panel. And a positive or negative precharge voltage obtained by adding an auxiliary voltage to the driving voltage.
[0018]
In the first to third devices of the present invention, the voltage generation circuit 100 processes a positive or negative power supply voltage to generate a positive or negative reference voltage necessary for the liquid crystal driving circuit, and an auxiliary voltage as the reference voltage. To generate a positive or negative precharge voltage to which the positive and negative voltages are added.
According to the control method of the liquid crystal driving device of the present invention, a driving voltage necessary for a liquid crystal display and a precharge voltage obtained by adding an auxiliary voltage to the driving voltage are generated in advance, and the driving voltage required for the liquid crystal display is generated. Adjust for each load circuit During precharge period A of one horizontal period B Adjust for each load circuit required for LCD display The precharge voltage is selected, and the drive voltage is selected in the remaining period excluding the precharge period A from the one horizontal period B, and the sequentially selected voltage is supplied to a load circuit necessary for a liquid crystal display. It is characterized by the following.
[0019]
In the control method of the present invention, preferably, the load circuit necessary for the liquid crystal display includes an active matrix type liquid crystal display panel, and the liquid crystal display panel performs a polarity inversion drive every horizontal period B for displaying one line. Is performed.
[0020]
In the control method of the present invention, the drive voltage and the precharge voltage are generated by dividing the power supply voltage by resistance, and a generated voltage value is adjusted by changing a resistance value used for the resistance division. I do.
The liquid crystal display device of the present invention outputs a stepped waveform voltage obtained by sampling a reference voltage as shown in FIG. 3B, and performs a multi-grayscale control. A liquid crystal display panel for holding one step voltage in a distributed capacitance is provided, and the liquid crystal driving unit has any one of the liquid crystal driving devices of the present invention, thereby achieving the above object.
[0021]
[Operation]
According to the liquid crystal driving device of the present invention, the precharge voltage is applied from the voltage output circuit 200 to the load circuit 101 during the precharge period according to the first and second control signals. 101 can reach the target voltage early.
[0022]
As a result, the load circuit 101 required for the liquid crystal display, for example, the liquid crystal drive circuit and the gate electrode of the liquid crystal display panel can be charged at high speed. In addition, even when the horizontal period is shortened and the number of pixels is increased, insufficient charging and insufficient data writing can be eliminated, and the stable operation period of the liquid crystal driving circuit and the liquid crystal display panel becomes longer, thereby reducing crosstalk. This contributes to providing a high-definition and high-definition liquid crystal display device.
[0023]
The precharge period can be easily set by adjusting the pulse width of the first control signal according to the load circuit 101. Thus, the precharge voltage can be arbitrarily set in accordance with the load circuit 101.
Further, according to the first device of the present invention, the positive drive voltage superimposed on the positive precharge voltage and the negative drive voltage superimposed on the negative precharge voltage are alternately switched to the second control signal. Is supplied from the output control circuit 13 to the load circuit 101 on the basis of the following formula, so that the drive voltage of the load circuit reaches the target level early during the precharge period during the common non-inverting drive by the positive precharge voltage. With the negative precharge voltage, the drive voltage of the load circuit can reach the target level early during the precharge period during the common inversion drive.
[0024]
According to the second device of the present invention, the voltage obtained by combining the positive precharge voltage and the positive drive voltage and the voltage obtained by combining the negative precharge voltage and the negative drive voltage are based on the second control signal. The output voltage is supplied alternately from the output control circuit 16 to the load circuit 101, so that the drive voltage of the load circuit is quickly increased to the target level during the precharge period by the positive or negative precharge voltage as in the first device. Can be reached.
[0025]
According to the third device of the present invention, the positive precharge voltage is applied from the first to fourth output circuits 17 to 20 to the load circuit 101 based on the signal logic of the first control signal and the second control signal. , A positive drive voltage, a negative precharge voltage, and a negative drive voltage are sequentially supplied, so that the positive or negative precharge voltage causes a load during the precharge period, as in the first and second devices. The drive voltage of the circuit can reach the target level early.
[0026]
According to the liquid crystal display device of the present invention, since any one of the first to third devices is included in the liquid crystal driving unit 300, the gradation voltage is charged with a margin for the selected pixel of the liquid crystal display panel 101. be able to.
This contributes to the provision of a high-quality and high-definition liquid crystal display device in which insufficient charging of the gradation voltage is eliminated.
[0027]
【Example】
Next, embodiments of the present invention will be described with reference to the drawings. 4 to 14 are diagrams illustrating a liquid crystal driving device, a control method thereof, and a liquid crystal display device according to an embodiment of the present invention.
(1) Description of the first embodiment
FIG. 4 is a configuration diagram of a multi-tone liquid crystal display device according to each embodiment of the present invention, and FIG. 5 is an explanatory diagram of electrodes of the liquid crystal display panel. FIG. 6 shows a configuration diagram of a common voltage supply circuit according to the first embodiment.
[0028]
As shown in FIG. 4, an active matrix type liquid crystal display device that performs 32 gradation display based on eight kinds of reference voltages V0 to V7 includes a liquid crystal drive unit 300 and a liquid crystal display panel 101.
The liquid crystal drive unit 300 outputs a stepped waveform voltage obtained by sampling eight kinds of reference voltages V0 to V7, and controls the liquid crystal display panel 101 to 32 gradations. The unit 100 includes a power supply circuit 40, a common voltage supply circuit 41, and a data generation & control circuit 42. The power supply circuit 40 generates eight kinds of reference voltages V0 to V7, a positive power supply +, and a negative power supply-.
[0029]
The common voltage supply circuit 41 receives a positive power supply + and a negative power supply-and generates a common voltage VCOM based on a precharge control signal (hereinafter, referred to as a PC signal) and a line inversion signal (hereinafter, referred to as an LN signal). . In the first embodiment, the common voltage supply circuit 41 employs the first liquid crystal driving device of the present invention. This circuit configuration will be described in detail with reference to FIG.
[0030]
The data generation & control circuit 42 generates video data (RDATA, GDATA, BDATA) DOUT for color display based on the horizontal synchronizing signal (hereinafter, referred to as HS signal) and the video signal SIN, and a data capture start signal (hereinafter, SPD signal and SPS signal). ), A shift clock signal (hereinafter referred to as CLKD signal and CLKS signal), and a line inversion signal (hereinafter referred to as LN signal and LP signal).
[0031]
The liquid crystal display panel 101 holds any one of the stepped waveform voltages in the distributed capacitance. The panel 101 has a TFT substrate 51, a common electrode 52, a data driver 53, and a scan driver 54. As shown in FIG. 5, a scan bus line (scan electrode) SBL and a data bus line (signal electrode) DBL are provided in a matrix on the TFT substrate 51, and a switching element (TFT) is connected to an intersection thereof. A pixel electrode is connected to the TFT.
[0032]
The common electrode 52 is provided in a lower layer on the TFT substrate 51, and liquid crystal is sealed between the substrate 51 and the electrode 52. The common voltage VCOM is supplied to the electrode 52.
The data driver 53 receives the reference voltages V0 to V7, the CLKD signal, the SPD signal, the LP signal, and the video data DOUT, and writes information to the TFT connected to the data bus line DBL. In addition, this information is suppressed by the driver 53 so that the amplitude range of the gradation voltage is within 5V. The driving power supply VCC of the driver 53 is a single -5V. The scan driver 54 receives the CLKS signal and the SPS signal, and selects a TFT connected to the scan bus line SBL.
[0033]
Next, the internal configuration of the common voltage supply circuit 41 will be described. For example, the circuit 41 includes a positive voltage generation circuit 21, a negative voltage generation circuit 22, and a voltage selection circuit 23, as shown in FIG.
The positive voltage generation circuit 21 is an example of the first voltage generation circuit 11, and includes a switch element SW1, resistors R1 to R3, and an output buffer BF1. The switch element SW1 performs an ON / OFF operation based on a PC signal (an overline is omitted). The resistors R2 and R3 are connected in series, and generate a positive common voltage VCOM + by dividing the positive power supply VDD + by resistance. One end of the resistor R1 is connected to SW1, and is connected to one end of R3 by SW1 = ON operation. As a result, a positive precharge voltage (hereinafter referred to as an overshoot voltage) VH that rises more rapidly than the positive common voltage VCOM + by dividing the positive power supply VDD + by resistance is output. The output buffer BF1 amplifies and outputs the common voltage VCOM + and the overshoot voltage VH.
[0034]
The negative voltage generation circuit 22 is an example of the second voltage generation circuit 12, and includes a switch element SW2, resistors R4 to R6, and an output buffer BF2. The switch element SW2 performs an ON / OFF operation based on the inverted PC signal (bar). The resistors R6 and R5 are connected in series, and generate a negative common voltage VCOM- by dividing the negative power supply VDD- by resistance. One end of the resistor R4 is connected to SW2, and is connected to one end of R6 by SW2 = ON operation. As a result, the negative power supply VDD- is resistance-divided, and a negative precharge voltage (hereinafter, referred to as an overshoot voltage) VL that falls more rapidly than the negative common voltage VCOM- is output. The output buffer BF2 amplifies and outputs the common voltage VCOM- and the overshoot voltage VL.
[0035]
The overshoot voltage VH sets the generated voltage value by changing the resistance values of R1 to R3, and the voltage VL sets the generated voltage value by changing the resistance values of R4 to R6.
The voltage output circuit 23 is an example of the output control circuit 13 and includes switch elements SW3, SW4, an inverter INV, and an output buffer BF3. The switch element SW3 performs an ON / OFF operation based on the non-inverted LN signal. The switch element SW4 performs an ON / OFF operation based on the inverted LN signal. The inverter INV inverts the LN signal. The output buffer BF3 amplifies either the overshoot voltage VH superimposed on the common voltage VCOM + or the overshoot voltage VL superimposed on the common voltage VCOM−.
[0036]
The function of the voltage output circuit 23 is to selectively output either the overshoot voltage VH superimposed on the common voltage VCOM + or the overshoot voltage VL superimposed on the common voltage VCOM− based on the LN signal.
Next, the operation of the liquid crystal display device will be described. FIG. 7 shows an operation timing chart of the liquid crystal drive unit according to the first embodiment of the present invention. In FIG. 7, when the PC signal is supplied to the positive voltage generation circuit 21 in synchronization with the rising of the HS signal during the precharge period during the common non-inverting drive of the liquid crystal display panel 101, the generation circuit 21 When the switch element SW1 is momentarily turned ON based on the signal PC, the positive power supply VDD + is resistance-divided by the resistors R1 and R3, and a positive overshoot voltage VH is generated.
[0037]
This voltage VH is a voltage having a large peak value that rises more rapidly than the positive common voltage VCOM +. At the same time, in the positive voltage generating circuit 21, the positive power supply VDD + is resistance-divided by the resistors R2 and R3, and a positive common voltage VCOM + is generated from the positive power supply VDD +.
The overshoot voltage VH is superimposed on the common voltage VCOM +, and this superimposed voltage is selected by the voltage output circuit 23 in synchronization with the rise of the LN signal, and is supplied to the common electrode 52 of the liquid crystal display panel 101.
[0038]
When the PC signal is supplied to the negative voltage generation circuit 22 in synchronization with the rising of the HS signal during the precharge period during the common inversion drive, the circuit element 22 switches the switch element SW2 based on the control signal PC. By turning ON momentarily, the negative power supply VDD- is divided by the resistors R4 and R6, and a negative overshoot voltage VL is generated.
[0039]
This voltage VL is a voltage having a large peak value that has fallen more rapidly than the negative common voltage VCOM-. At the same time, in the negative voltage generating circuit 22, the negative power supply VDD- is resistance-divided by the resistors R6 and R5, and a negative common voltage VCOM- is generated from the negative power supply VDD-.
The overshoot voltage VL is superimposed on the common voltage VCOM-, and the superimposed voltage is selected by the voltage output circuit 23 in synchronization with the rise of the LN signal, and is supplied to the common electrode 52 of the liquid crystal display panel 101.
[0040]
As a result, polarity inversion driving for inverting the voltage applied to the common electrode of the liquid crystal display panel 101 every horizontal period is performed. For example, a step-like waveform voltage obtained by sampling the reference voltages V0 to Vn, and common voltages VCOM + and VCOM− having a long common voltage stabilization period are output from the liquid crystal driving unit 300 to the liquid crystal display panel 101 and selected by the scan driver 54. When the TFT of the scan line SBL is turned on, the four gradation voltages applied to the data bus line DBL from the data driver 53 are held in the distribution capacitance of the liquid crystal display panel 101.
[0041]
When the output of the driver 54 is in the ON state, the output of the driver 53 is applied to the pixel electrode, and as shown in FIG. , The pixel electrode potential is held in the distribution capacitor, and the information is kept held until the output of the driver 54 is turned off.
[0042]
As a result, information is written to each pixel electrode, and this gradation voltage is held until the next row is selected. By maintaining the charge at this time in the distribution capacitor, information is maintained, the inclination of the liquid crystal is determined in accordance with this information, the amount of transmitted light is controlled, and color gradation display is performed.
Thus, according to the multi-tone liquid crystal driving device according to the first embodiment of the present invention, the common voltage supply circuit 41 having the voltage output circuit 23 as shown in FIG. During the precharge period of one horizontal period, the overshoot voltage VH superimposed on the common voltage VCOM + or the overshoot voltage VL superimposed on the common voltage VCOM− based on the LN signal is applied from the voltage output circuit 23 to the common electrode 52. Since the output voltage is alternately output, the common voltage VCOM + reaches the target level early during the positive-side precharge period by the steeply rising overshoot voltage VH or the steeply falling overshoot voltage VL. During the precharge period, the common voltage VCOM- can reach the target level early. You.
[0043]
As a result, the transition period until VCOM + reaches the common voltage stabilization period and the transition period until VCOM− reaches the common voltage stabilization period are extremely short, and the positive or negative common voltage The period can be lengthened, and information can be written to the distribution capacitor at an early stage. It is not necessary to shorten the pulse width per step of the reference voltages V0 to V7 as in the conventional example.
[0044]
In addition, since high-speed charging that allows the common electrode 52 to quickly reach the positive or negative stable state can be performed, the gray scale voltage can be charged to the selected pixel of the liquid crystal display panel 101 with a margin.
As a result, even when the horizontal period is shortened and the number of pixels is increased, the polarity inversion drive of the active matrix type liquid crystal display panel 101 can be performed with high accuracy, and a high voltage that eliminates insufficient charging of the gradation voltage can be eliminated. It contributes to providing high quality and high definition liquid crystal display devices. It is also effective for a liquid crystal display device that does not use the distributed capacitance method.
[0045]
(2) Description of the second embodiment
FIG. 8 shows a configuration diagram of a common voltage supply circuit according to the second embodiment of the present invention. The second embodiment differs from the first embodiment in that the positive precharge voltage VPC + and the common voltage VCOM + are switched and output, the negative precharge voltage VPC− and the common electrode voltage VCOM−. And an output which is selectively output alternately by an LN signal.
[0046]
That is, the common voltage supply circuit applied to the multi-tone liquid crystal display device according to the second embodiment includes a positive voltage selection circuit 24, a negative voltage selection circuit 25, and a voltage output circuit 26, as shown in FIG. ing.
The positive voltage selection circuit 24 is an example of the first selection circuit 14, and includes switch elements SW1, SW2, an output buffer BF1, and an inverter INV1. The switch element SW1 performs an ON / OFF operation based on the non-inverted PC signal. The switch element SW2 performs an ON / OFF operation based on the inverted PC signal. The output buffer BF1 amplifies the positive common voltage VCOM + whose output is permitted by the switch element SW1 or the precharge voltage VPC + whose output is permitted by the switch element SW2. The precharge voltage VPC + is a voltage that rises more rapidly than the common voltage VCOM +. The inverter INV1 inverts the PC signal.
[0047]
The negative voltage selection circuit 25 is an example of the second selection circuit 15, and has switch elements SW3 and SW4 and an output buffer BF2. The switch element SW3 performs an ON / OFF operation based on the non-inverted PC signal. The switch element SW4 performs ON / OFF operation based on the inverted PC signal. The output buffer BF2 amplifies the negative common voltage VCOM- whose output is permitted by the switch element SW3 or the precharge voltage VPC- whose output is permitted by the switch element SW4. The precharge voltage VPC- is a voltage that falls more rapidly than the common voltage VCOM-.
[0048]
The voltage output circuit 26 is an example of the output control circuit 16, and includes switch elements SW5, SW6, an output buffer BF3, and an inverter INV2. The switch element SW5 performs an ON / OFF operation based on the non-inverted LN signal. The switch element SW6 performs an ON / OFF operation based on the inverted LN signal. The output buffer BF3 amplifies either the precharge voltage VPC + and the common voltage VCOM + sequentially output from the selection circuit 24, or the precharge voltage VPC− and the common voltage VCOM− sequentially output from the selection circuit 25. The inverter INV2 inverts the LN signal.
[0049]
In the second embodiment of the present invention, the power supply circuit 40 as shown in FIG. 4 generates a positive common voltage VCOM + and a precharge voltage VPC + obtained by processing a positive power supply + in addition to eight types of reference voltages V0 to V7. Then, a negative common voltage VCOM- and a precharge voltage VPC- obtained by processing the voltage of the negative power supply-are generated.
Next, the operation of the liquid crystal drive unit incorporating the common voltage supply circuit will be described. FIG. 9 shows an operation waveform diagram of the liquid crystal drive unit according to the second embodiment of the present invention. In FIG. 9, in the positive precharge period in which the PC signal is at the “L” level in the horizontal period during the common non-inverting drive of the liquid crystal display panel 101, the switch element SW 2 is momentarily turned on in the positive voltage selection circuit 24. By operating, the positive precharge voltage VPC + is selected. Further, during the period of PC = “H” level, the positive common voltage VCOM + is selected by continuing the ON operation of the switch element SW1. This voltage VPC + is an overshoot voltage having a large peak value that rises more rapidly than the positive common voltage VCOM +.
[0050]
Further, the voltage VPC + is superimposed on the common voltage VCOM +, and the superimposed voltage is selected by the voltage output circuit 26 in synchronization with the rise of the LN signal, and is supplied to the liquid crystal display panel 101.
Further, in the negative precharge period in which the PC signal is at the “L” level in the horizontal period during the common inversion driving, the switch element SW4 is momentarily turned on in the negative voltage selection circuit 25, so that the negative precharge is performed. Charge voltage VPC- is selected. Thus, during the period of PC = “H” level, the switch element SW3 continues the ON operation, so that the negative common voltage VCOM− is selected. This voltage VPC- is an overshoot voltage having a large peak value that has fallen more rapidly than the negative common voltage VCOM-. The voltage VPC + is superimposed on the common voltage VCOM +, and this superimposed voltage is selected by the output control circuit 16 in synchronization with the rise of the LN signal, and is supplied to the liquid crystal display panel 101.
[0051]
Thus, according to the multi-tone liquid crystal driving device according to the second embodiment of the present invention, the common voltage supply circuit 41 having the voltage output circuit 26 as shown in FIG. Similarly to the embodiment, during the horizontal period, the precharge voltage VPC + superimposed on the common voltage VCOM + or the precharge voltage VPC- superimposed on the common voltage VCOM− is alternately output from the voltage output circuit 26 to the common electrode based on the LN signal. 52, the common voltage VCOM + is made to reach the target level early during the positive-side precharge period, and the common voltage VCOM− is made negative during the negative-side precharge period. Can reach the target level early.
[0052]
Thus, high-speed charging can be performed to quickly bring the common electrode of the liquid crystal display panel 101 to a stable state on the positive or negative side. Further, the transition periods of VCOM + and VCOM− are shortened as compared with the conventional example, and the positive and negative common voltage stabilization periods can be extended.
This contributes to shortening the horizontal period and providing a high-quality and high-definition liquid crystal display device in which insufficient charging of the gray scale voltage is eliminated even when the number of pixels is increased.
[0053]
(3) Description of the third embodiment
FIG. 10 shows a configuration diagram of a common voltage supply circuit according to the third embodiment of the present invention. The difference from the first and second embodiments is that in the third embodiment, either one of the positive or negative precharge voltage VPC ± or the common electrode voltage VCOM ± is controlled by a switch which decodes the LN signal and the PC signal. The signals are selectively output by the signals S1 to S4.
[0054]
That is, as shown in FIG. 10, the common voltage supply circuit applied to the multi-tone liquid crystal display device according to the third embodiment includes four output control circuits 27 to 30, two inverters INV1 and INV2, and an output buffer. 31 are provided. The output control circuit 27 is an example of the first output circuit 17, and includes a two-input AND circuit 27A and a switch element SW1. The two-input AND circuit 27A decodes the LN signal and the PC signal to generate a switch control signal S1, and outputs it to the switch element SW1. SW1 performs an ON / OFF operation based on the signal S1, and outputs or cuts off (enables control) the positive common voltage VCOM +.
[0055]
The output control circuit 28 is an example of the second output circuit 18, and includes a two-input AND circuit 28A and a switch element SW2. The two-input AND circuit 28A decodes the LN signal and the PC signal to generate a switch control signal S2, and outputs it to the switch element SW2. SW2 performs ON / OFF operation based on the signal S2, and outputs or cuts off the negative common voltage VCOM-.
[0056]
The output control circuit 29 is an example of the third output circuit 19, and includes a two-input AND circuit 29A and a switch element SW3. The two-input AND circuit 29A decodes the LN signal and the PC signal to generate a switch control signal S3, and outputs it to the switch element SW3. SW3 performs an ON / OFF operation based on the signal S1, and outputs or cuts off a positive precharge voltage VPC + that rises more rapidly than the positive common voltage VCOM +.
[0057]
The output control circuit 30 is an example of the fourth output circuit 20, and includes a two-input AND circuit 30A and a switch element SW4. The two-input AND circuit 30A decodes the LN signal and the PC signal to generate a switch control signal S4, and outputs it to the switch element SW4. SW4 performs an ON / OFF operation based on the signal S4, and outputs or cuts off a negative precharge voltage VPC- that falls more rapidly than the negative common voltage VCOM-. The inverter INV1 inverts the LN signal, and the inverter INV2 inverts the PC signal. The output buffer 31 amplifies the precharge voltage VPC + superimposed on the common voltage VCOM + or the precharge voltage VPC- superimposed on the common voltage VCOM−.
[0058]
Next, the operation of the liquid crystal drive unit of this embodiment will be described. For example, referring to the operation waveform diagram used in the second embodiment, in FIG. 9, in the horizontal period during the common non-inverting drive, the PC signal is at the “L” level and the LN signal is at the “H” level. During the positive-side precharge period, the signal S3 = "H" level is generated from the AND circuit 29A as shown in FIG. 10, and the switch SW3 is momentarily turned ON. The other switches SW1, SW2, and SW4 are in the OFF operation.
[0059]
As a result, during the precharge period, the output control circuit 29 supplies the liquid crystal display panel 101 with the positive precharge voltage VPC + that rises more rapidly than the positive common voltage VCOM +. In the horizontal period excluding this period, the signal PC is at the “H” level, so that the signal S1 = “H” level is generated from the AND circuit 27A, and the switch SW1 is continuously turned ON. The other switches SW2 to SW4 are in the OFF operation, and the output control circuit 27 supplies the liquid crystal display panel 101 with the positive common voltage VCOM + continuously to the voltage VPC +.
[0060]
During the negative precharge period in which the PC signal is at the “L” level and the LN signal is at the “L” level in the horizontal period during the common inversion drive, the signal S4 = “H” level from the AND circuit 30A is changed. Then, the switch SW4 is momentarily turned ON. The other switches SW1 to SW3 are in the OFF operation. During this precharge period, the output control circuit 30 supplies the liquid crystal display panel 101 with a negative precharge voltage VPC- that falls sharply below the negative common voltage VCOM-.
[0061]
In the horizontal period excluding this period, the signal PC becomes the “H” level, so that the signal S2 = “H” level is generated from the AND circuit 28A, and the switch SW2 is continuously turned ON. The other switches SW1, SW3, and SW4 are in the OFF operation, and the output control circuit 28 supplies the liquid crystal display panel 101 with the negative common voltage VCOM- continuously from the voltage VPC-.
[0062]
Thus, according to the multi-tone liquid crystal driving device according to the third embodiment of the present invention, a common voltage supply circuit having four output control circuits 27 to 30 and an output buffer 31 as shown in FIG. 41, the precharge voltage VPC + superimposed on the common voltage VCOM + or the precharge voltage VPC- superimposed on the common voltage VCOM- based on the LN signal is alternately provided during the horizontal period, similarly to the second embodiment. Is switched from the output buffer 31 to the common electrode 52, so that the common voltage VCOM + reaches the target level early during the positive precharge period by the precharge voltage VPC ±, and the negative precharge During the period, the common voltage VCOM- can reach the target level early.
[0063]
Thus, high-speed charging can be performed to quickly bring the common electrode of the liquid crystal display panel 101 to a stable state on the positive or negative side. Further, the number of output buffers can be reduced as compared with the second embodiment, so that low power consumption, integration and cost reduction can be achieved. This is because the occupied area of the AND circuits 27A to 30A can be smaller than the chip occupied area of the output buffer.
[0064]
This provides a high-quality and high-definition liquid crystal display device in which the horizontal period is shortened as in the first and second embodiments, and even when the number of pixels is increased, insufficient charging of the gradation voltage is eliminated. To contribute.
(4) Description of the fourth embodiment
FIG. 11 shows a configuration diagram of a gate voltage generation circuit according to the fourth embodiment of the present invention. The fourth embodiment differs from the first embodiment in a voltage generation circuit for supplying a gate control voltage to a thin film transistor (hereinafter, referred to as a TFT) of a liquid crystal display panel.
[0065]
The gate voltage generation circuit applied to the multi-tone liquid crystal display device according to the fourth embodiment includes a voltage generation circuit 61 and a voltage selection output circuit 62 as shown in FIG. The voltage generation circuit 61 is an example of the voltage generation circuit 100, and includes a positive or negative gate control voltage VG ± required for a liquid crystal display and a positive or negative precharge voltage VPC ± obtained by adding an auxiliary voltage Vα ± to the voltage VG ±. Is a circuit that generates In this embodiment, the voltage Vα is about 0.3 to 0.5 V when the voltage VG is 3 to 5 V.
[0066]
The voltage generation circuit 61 includes five resistors R1 to R5. The resistors R1 to R5 are connected in series, one end of the resistor R1 is connected to a supply source of the voltage VDD +, and one end of the resistor R5 is connected to a supply source of the voltage VDD−. VPC + is led from the connection point of the resistors R1 and R2 to the switch element SW1, VG + is led from the connection point of the resistors R2 and R3 to the switch element SW2, and VG- is led from the connection point of the resistors R3 and R4 to the switch element SW4. That is, VPC- is led to the switch element SW3 from the connection point between the resistors R4 and R5.
[0067]
The voltage selection output circuit 62 is an example of the voltage output circuit 200. The voltage selection output circuit 62 selectively outputs the positive or negative precharge voltage VPC ± from the voltage generation circuit 61 during a precharge period of one horizontal period necessary for liquid crystal display. This is a circuit for selectively outputting the positive or negative gate control voltage VG ± during the remaining period of one horizontal period excluding the charging period B. The voltage selection output circuit 62 includes two inverters INV1 and INV2, four two-input AND circuits A1 to A4, four switch elements SW1 to SW4, and an output buffer BF.
[0068]
The inverter INV1 inverts the non-inverted PC signal and outputs the inverted PC signal to the AND circuits A1 and A3. The inverter INV2 inverts the non-inverted LN signal and outputs the inverted LN signal to the AND circuits A1 and A2. The AND circuit A1 outputs a switch control signal S1 to the switch element SW1 according to the logic of the inverted PC signal and the inverted LN signal. The AND circuit A2 outputs a switch control signal S2 to the switch element SW2 according to the logic of the non-inverted PC signal and the inverted LN signal. The AND circuit A3 outputs the switch control signal S3 to the switch element SW3 according to the logic of the inverted PC signal and the non-inverted LN signal. The AND circuit A4 outputs a switch control signal S4 to the switch element SW4 according to the logic of the non-inverted PC signal and the non-inverted LN signal.
[0069]
SW1 outputs precharge voltage VPC + to output buffer BF in response to signal S1. SW2 outputs the gate control voltage VG + to the output buffer BF according to the signal S2. SW3 outputs the precharge voltage VPC- to the output buffer BF according to the signal S3. SW4 outputs the gate control voltage VG- to the output buffer BF according to the signal S4. The output buffer BF applies the above four voltages VPC ± and VG ± to the TFT 63 during the horizontal period.
[0070]
FIG. 12A is an equivalent circuit diagram of a gate line connected to a TFT of the liquid crystal display panel, and FIG. 12B is a waveform diagram of the gate line.
As shown in FIG. 12A, an equivalent circuit of a gate line of a liquid crystal display panel is represented by a resistance R of the gate line and an auxiliary capacitance C existing on the line. It takes a certain time to charge the gate of the TFT 63 depending on the time constant of RC. However, in this embodiment, the delay of the rise of the drive voltage of the gate line is improved by the precharge voltage VPC as shown in FIG. In FIG. 12B, A indicates a precharge period, and B indicates one horizontal period of a horizontal synchronization signal (hereinafter, referred to as an HS signal).
[0071]
For example, the output voltage waveform from the output buffer BF during the common non-inverting drive includes a precharge voltage VPC + selectively output during the precharge period A and a gate selectively output during the remaining period of the horizontal period B other than the period A. It is composed of a control voltage VG +. This precharge voltage VPC + hastens the rise of the drive voltage of the gate line, and as a result, the voltage waveform X of the gate line according to the present invention has a gate control voltage VG + applied to the load circuit from the beginning throughout the horizontal period. This is improved compared to the waveform Y.
[0072]
Next, the operation of the liquid crystal display device will be described. FIG. 13 shows an operation timing chart of the gate voltage generation circuit according to the fourth embodiment of the present invention. In FIG. 13, in a precharge period A at the time of common non-inversion driving, a PC signal and an LN signal which become “L” level in synchronization with the rising of the HS signal are supplied to the voltage selection output circuit 62. When the switch element SW1 is momentarily turned on in response to the PC signal and the LN signal, the precharge voltage VPC + is selected and applied to the gate line of the liquid crystal display panel via the output buffer BF. The other switch elements SW2 to SW4 are OFF.
[0073]
In the remaining period of the horizontal period B excluding the precharge period A, the PC signal that goes to the “H” level and the LN signal that keeps the “L” level are applied to the voltage selection output circuit 62, and as a result, In the circuit 62, the gate control voltage VG + is selected by turning on the switch element SW2 in response to the PC signal and the LN signal, and is applied to the gate line of the liquid crystal display panel via the output buffer BF. The other switch elements SW1, SW3, SW4 are operating OFF.
[0074]
Further, in the precharge period A at the time of the common inversion drive, the PC signal which becomes “L” level and the LN signal which becomes “H” level in synchronization with the rise of the HS signal are supplied to the voltage selection output circuit 62, In this case, the switch element SW3 is momentarily turned on in response to the PC signal and the LN signal, whereby the precharge voltage VPC- is selected and applied to the gate line of the liquid crystal display panel via the output buffer BF. The other switch elements SW1, SW2, and SW4 are OFF.
[0075]
In the remaining period of the horizontal period B excluding the precharge period A, the PC signal that goes to the “H” level and the LN signal that continues to be at the “H” level are applied to the voltage selection output circuit 62. At 62, the switch element SW4 is turned on in response to the PC signal and the LN signal, whereby the gate control voltage VG- is selected and applied to the gate line of the liquid crystal display panel via the output buffer BF. The other switch elements SW1 to SW3 operate OFF.
[0076]
Thus, the overshoot of the precharge voltage waveform X as shown in FIG. 12B cancels the waveform Y due to the transient phenomenon of the gate line, and as a result, the waveform of the gate line sharply rises.
As described above, according to the multi-gradation liquid crystal driving device according to the fourth embodiment of the present invention, the precharge voltage VPC + is applied to the gate line from the voltage selection output circuit 62 in the precharge period A during the common non-inversion driving. The gate control voltage VG + is selectively supplied during a period other than the precharge period, the precharge voltage VPC− is selectively supplied during a precharge period A during common inversion driving, and the gate control voltage VG− is selected during a period other than the precharge period. Since it is supplied, the precharge voltage VPC allows the gate control voltage VG ± to reach the target level early during the precharge period.
[0077]
Thereby, the gate electrode of the liquid crystal display panel can be charged at a high speed. In addition, even when the horizontal period is shortened and the number of pixels is increased, insufficient charging and insufficient data writing can be eliminated, the stable operation period of the liquid crystal display panel can be extended, crosstalk can be reduced, and high image quality can be achieved. In addition, it contributes to providing a high-definition liquid crystal display device. The precharge period can be easily set by adjusting the pulse width of the PC signal according to R and C of the gate line, and the charge time can be shortened by changing the resistance value of the voltage generation circuit. Can be achieved.
[0078]
(5) Description of the fifth embodiment
FIG. 14 shows a configuration diagram of a reference voltage generation circuit according to the fifth embodiment of the present invention. The fifth embodiment differs from the first to fourth embodiments in that the fifth embodiment relates to a reference voltage generating circuit for supplying reference voltages V0 to V7 to the data driver 53 as shown in FIG.
[0079]
The reference voltage generation circuit applied to the multi-gradation liquid crystal display device according to the fifth embodiment includes eight reference voltage generation units VRF1 to VRF8 as shown in FIG. The unit VRF1 has the voltage generation circuit 61 and the voltage selection output circuit 62 as described in the fourth embodiment, and outputs the reference voltage V0 to the driver 53 according to the PC signal and the LN signal. Similarly, the units VRF2 to VRF8 output the reference voltages V1 to V7 to the driver 53 according to the PC signal and the LN signal, respectively. The supply source of the voltage VDD ± of the voltage generation circuit 61 has a polarity opposite to that of the fourth embodiment. This is because the phase differs from the voltage supplied to the common electrode and the gate electrode of the liquid crystal display panel by 180 °.
[0080]
As described above, according to the reference voltage generation circuit according to the fifth embodiment of the present invention, the precharge voltage VPC is selectively supplied to the driver 53 from each of the units VRF1 to VRF8 during the precharge period. When the reference voltage is selectively supplied from each of the units VRF1 to VRF8 to the driver 53, the precharge voltage VPC allows the reference voltage to reach the target level early during the precharge period.
[0081]
As a result, the liquid crystal driving circuit required for liquid crystal display can be charged at a high speed. In addition, even if the horizontal period is shortened and the number of pixels is increased, insufficient charging and insufficient data writing can be eliminated, the stable operation period of the liquid crystal drive circuit can be extended, crosstalk can be reduced, and high image quality can be achieved. In addition, it contributes to providing a high-definition liquid crystal display device.
In this embodiment, the same charging time can be easily obtained by exchanging the supply sources of the voltages VDD ± of the voltage generation circuit 61 of the fourth embodiment. Also, by adjusting the “L” level period of the PC signal, it is possible to make the charging time of the common voltage supply circuit and the gate voltage generating circuit equal to the charging time of the reference voltage generating circuit.
[0082]
【The invention's effect】
As described above, according to the liquid crystal driving device of the present invention, since the voltage output circuit for applying the precharge voltage is provided to the load circuit required for the liquid crystal display, the driving voltage of the load circuit is reduced during the precharge period. The target level can be reached early.
[0083]
Thus, the load circuits such as the liquid crystal display panel and the liquid crystal drive circuit can be charged at a high speed. In addition, insufficient charging and insufficient data writing are eliminated, the stable operation period of the liquid crystal driving circuit and the liquid crystal display panel is extended, and crosstalk can be reduced.
According to the liquid crystal display device of the present invention, the gray scale voltage can be charged with a margin for the selected pixel of the liquid crystal display panel.
[0084]
This greatly contributes to providing a high-definition and high-definition liquid crystal display device having a short horizontal period and a large number of pixels.
[Brief description of the drawings]
FIG. 1 is a principle diagram (part 1) of a liquid crystal driving device according to the present invention.
FIG. 2 is a principle diagram (part 2) of the liquid crystal driving device according to the present invention.
FIG. 3 is a principle diagram of a liquid crystal driving device and a liquid crystal display device according to the present invention.
FIG. 4 is a configuration diagram of a multi-tone liquid crystal display device according to each embodiment of the present invention.
FIG. 5 is an explanatory diagram of an electrode of the liquid crystal display panel according to each embodiment of the present invention.
FIG. 6 is a configuration diagram of a common voltage supply circuit according to a first example of the present invention.
FIG. 7 is an operation waveform diagram of the liquid crystal drive unit according to the first embodiment of the present invention.
FIG. 8 is a configuration diagram of a common voltage supply circuit according to a second embodiment of the present invention.
FIG. 9 is an operation waveform diagram of the liquid crystal drive unit according to the second embodiment of the present invention.
FIG. 10 is a configuration diagram of a common voltage supply circuit according to a third embodiment of the present invention.
FIG. 11 is a configuration diagram of a gate voltage generation circuit according to a fourth embodiment of the present invention.
FIG. 12 is an equivalent circuit diagram and a time chart of a gate line according to a fourth embodiment of the present invention.
FIG. 13 is an operation waveform diagram of the voltage generation circuit according to the fourth example of the present invention.
FIG. 14 is a configuration diagram of a reference pressure generation circuit according to a fifth embodiment of the present invention.
FIG. 15 is an explanatory diagram of a liquid crystal display device and a common voltage supply circuit according to a conventional example.
FIG. 16 is an operation waveform diagram of a liquid crystal driving device according to a conventional example.
FIG. 17 is an operation waveform diagram (part 1) of a liquid crystal driving device for explaining a problem according to the conventional example.
FIG. 18 is an operation waveform diagram (part 2) of the liquid crystal drive device for explaining a problem according to the conventional example.
[Explanation of symbols]
11, 12 ... first and second voltage generating circuits,
13, 16 ... output control circuit,
14, 15 ... first and second selection circuits,
17-20 ... first to fourth output circuits,
41 ... common voltage supply circuit,
100 ... voltage generation circuit,
101 ... liquid crystal display panel,
200 ... voltage output circuit,
300: LCD drive unit,
VDD +: Positive power supply,
VDD-: negative power supply,
VCOM +: positive common voltage (drive voltage),
VCOM-: negative common voltage (drive voltage),
VH, VPC + ... positive precharge voltage,
VL, VPC -... negative precharge voltage,
PC: precharge control signal (first control signal),
LN: Line inversion signal (second control signal).

Claims (11)

  1. A voltage generating circuit for generating a driving voltage necessary for a liquid crystal display and a precharge voltage obtained by adding an auxiliary voltage to the driving voltage;
    A precharge voltage from the voltage generation circuit is output during a precharge period according to a first control signal having one horizontal period required for liquid crystal display as one cycle, and then a drive voltage from the voltage generation circuit is output. A voltage output circuit for outputting in response to the first control signal and a second control signal having a horizontal period required for liquid crystal display as a half cycle,
    A liquid crystal driving device , wherein one horizontal period is adjusted by controlling a length of the precharge period and a precharge voltage .
  2. A first selection circuit that selects a positive driving voltage and a positive precharge voltage based on the first control signal and combines and outputs the selected voltage;
    A second selection circuit that selects a negative drive voltage and the negative precharge voltage based on the first control signal and outputs the combined output;
    The positive precharge voltage and the positive drive voltage output from the first selection circuit and the negative precharge voltage and the negative drive voltage output from the second selection circuit are output from the second selection circuit. 2. The liquid crystal driving device according to claim 1, further comprising: an output control circuit that outputs the signals alternately based on the control signal.
  3. A first output circuit that permits output of a positive drive voltage based on the signal logic of the first control signal and the second control signal;
    A second output circuit that permits output of a negative drive voltage based on the signal logic of the first control signal and the second control signal;
    A third output circuit that permits output of a positive precharge voltage based on the signal logic of the first control signal and the second control signal;
    2. The liquid crystal driving device according to claim 1, further comprising: a fourth output circuit that permits output of a negative precharge voltage based on the signal logic of the first control signal and the second control signal. .
  4. The positive power supply voltage is processed to generate a positive drive voltage required for liquid crystal display, and a positive precharge voltage that rises more rapidly than the drive voltage is defined as a first cycle in which one horizontal period required for liquid crystal display is one cycle. A first voltage generation circuit that superimposes on the drive voltage based on a precharge period according to the control signal of
    Processing a negative power supply voltage to generate a negative drive voltage required for the liquid crystal display, and superimposing a negative precharge voltage falling more rapidly than the drive voltage on the drive voltage based on the precharge period. A second voltage generation circuit;
    A positive drive voltage superimposed on a positive precharge voltage from the first voltage generating circuit and a negative drive voltage superimposed on a negative precharge voltage are set to a second period in which the one horizontal period is a half cycle. An output control circuit for alternately outputting based on a control signal,
    A liquid crystal driving device , wherein one horizontal period is adjusted by controlling a length of the precharge period and a precharge voltage .
  5. The voltage generation circuit processes a positive or negative power supply voltage to generate a positive or negative common voltage required for a common electrode of an active matrix type liquid crystal display panel and a positive or negative voltage obtained by adding an auxiliary voltage to the common voltage. 5. The liquid crystal display device according to claim 1, wherein the liquid crystal display device generates a precharge voltage of:
  6. The voltage generation circuit processes a positive or negative power supply voltage to generate a positive or negative drive voltage required for a gate electrode of an active matrix type liquid crystal display panel, and a positive or negative drive voltage obtained by adding an auxiliary voltage to the drive voltage. 5. The liquid crystal display device according to claim 1, wherein the liquid crystal display device generates a precharge voltage of:
  7. The voltage generation circuit processes a positive or negative power supply voltage to generate a positive or negative reference voltage required for the liquid crystal driving circuit and a positive or negative precharge voltage obtained by adding an auxiliary voltage to the reference voltage. The liquid crystal display device according to any one of claims 1, 2, 3, and 4, wherein:
  8. A driving voltage required for liquid crystal display and a precharge voltage obtained by adding an auxiliary voltage to the driving voltage are generated in advance, and the voltage is adjusted for each load circuit required for liquid crystal display. The precharge voltage to be adjusted for each load circuit is selected, and the drive voltage is selected during the remaining period excluding the precharge period from the one horizontal period, and the sequentially selected voltages are used for liquid crystal display. A method for controlling a liquid crystal driving device, wherein the method is supplied to a load circuit.
  9. 9. A load circuit required for the liquid crystal display, comprising an active matrix type liquid crystal display panel, wherein the liquid crystal display panel performs a polarity inversion drive every horizontal period for displaying one line. The control method of the liquid crystal drive device described in the above.
  10. 9. The liquid crystal according to claim 8, wherein the drive voltage and the precharge voltage are generated by dividing the power supply voltage by resistance, and the generated voltage value is adjusted by changing a resistance value used for the resistance division. A control method of a driving device.
  11. A liquid crystal drive unit that outputs a stepped waveform voltage obtained by sampling a reference voltage and performs multi-grayscale control; and a liquid crystal display panel that holds any one of the stepped waveform voltages in the distributed capacitance. A liquid crystal display device, wherein the liquid crystal drive unit includes the liquid crystal drive device according to any one of claims 1 to 7.
JP05901495A 1994-07-08 1995-03-17 Liquid crystal driving device, control method thereof, and liquid crystal display device Expired - Fee Related JP3568615B2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP15728694 1994-07-08
JP6-157286 1994-07-08
JP05901495A JP3568615B2 (en) 1994-07-08 1995-03-17 Liquid crystal driving device, control method thereof, and liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP05901495A JP3568615B2 (en) 1994-07-08 1995-03-17 Liquid crystal driving device, control method thereof, and liquid crystal display device

Publications (2)

Publication Number Publication Date
JPH0876083A JPH0876083A (en) 1996-03-22
JP3568615B2 true JP3568615B2 (en) 2004-09-22

Family

ID=26400039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP05901495A Expired - Fee Related JP3568615B2 (en) 1994-07-08 1995-03-17 Liquid crystal driving device, control method thereof, and liquid crystal display device

Country Status (1)

Country Link
JP (1) JP3568615B2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2954162B1 (en) 1998-05-20 1999-09-27 日本電気アイシーマイコンシステム株式会社 LCD drive circuit
KR100634827B1 (en) 1999-09-07 2006-10-17 엘지.필립스 엘시디 주식회사 Apparatus for Compensating Gamma Voltage of Liquid Crystal Display and Method Thereof
KR100759967B1 (en) * 2000-12-16 2007-09-18 삼성전자주식회사 Flat panel display
JP4963758B2 (en) * 2000-12-21 2012-06-27 三星電子株式会社Samsung Electronics Co.,Ltd. Liquid crystal display device and grayscale voltage generation circuit therefor
JP2002258242A (en) * 2001-03-05 2002-09-11 Matsushita Electric Ind Co Ltd Liquid crystal display and image display application device
JP2005208551A (en) * 2003-12-25 2005-08-04 Sharp Corp Display device and driving device
KR100698983B1 (en) 2004-03-30 2007-03-26 샤프 가부시키가이샤 Display device and driving device
JP4736335B2 (en) * 2004-03-19 2011-07-27 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
JP2005274658A (en) * 2004-03-23 2005-10-06 Hitachi Displays Ltd Liquid crystal display apparatus
JP4356616B2 (en) * 2005-01-20 2009-11-04 セイコーエプソン株式会社 Power supply circuit, display driver, electro-optical device, electronic apparatus, and control method for power supply circuit
US8259052B2 (en) 2005-03-07 2012-09-04 Lg Display Co., Ltd. Apparatus and method for driving liquid crystal display with a modulated data voltage for an accelerated response speed of the liquid crystal
WO2006123532A1 (en) * 2005-05-20 2006-11-23 Sharp Kabushiki Kaisha Display apparatus driving circuit and driving method
TWI284242B (en) 2005-12-30 2007-07-21 Au Optronics Corp Pixel unit and display device utilizing the same
KR101232161B1 (en) * 2006-06-23 2013-02-15 엘지디스플레이 주식회사 Apparatus and method for driving liquid crystal display device
KR101281926B1 (en) * 2006-06-29 2013-07-03 엘지디스플레이 주식회사 Liquid crystal display device
JP5186913B2 (en) * 2007-01-22 2013-04-24 セイコーエプソン株式会社 Source driver, electro-optical device and electronic apparatus
JP5250072B2 (en) * 2011-03-23 2013-07-31 シャープ株式会社 Drive device and display device

Also Published As

Publication number Publication date
JPH0876083A (en) 1996-03-22

Similar Documents

Publication Publication Date Title
JP5118188B2 (en) Active matrix display device
EP1335344B1 (en) Reference voltage generation method and circuit, display drive circuit and display device with gamma correction and reduced power consumption
US8111230B2 (en) Drive circuit of display apparatus
KR100417572B1 (en) Display device
US8264454B2 (en) Electrophoretic display and driving method thereof
KR100536871B1 (en) Display driving device and display using the same
US6310616B1 (en) Voltage generating circuit, and common electrode drive circuit signal line drive circuit and gray-scale voltage generating circuit for display device
US6965365B2 (en) Display apparatus and driving method thereof
JP3807321B2 (en) Reference voltage generation circuit, display drive circuit, display device, and reference voltage generation method
KR100570317B1 (en) Display device, display system and method for driving the display device
US7133035B2 (en) Method and apparatus for driving liquid crystal display device
KR100511809B1 (en) Liquid crystal display device and driving method of the same
US8487859B2 (en) Data driving apparatus and method for liquid crystal display device
USRE39366E1 (en) Liquid crystal driver and liquid crystal display device using the same
USRE44484E1 (en) Method and circuit for driving electrophoretic display and electronic device using same
KR100859467B1 (en) Liquid crystal display and driving method thereof
US6839043B2 (en) Active matrix display device and mobile terminal using the device
US5798746A (en) Liquid crystal display device
KR101157251B1 (en) Liquid Crystal Display and Driving Method thereof
KR101245944B1 (en) Liquid crystal display device and driving method thereof
US6873312B2 (en) Liquid crystal display apparatus, driving method therefor, and display system
US6160533A (en) Method and apparatus for driving display panel
KR100965571B1 (en) Liquid Crystal Display Device and Method of Driving The Same
US7486268B2 (en) Gate driving apparatus and method for liquid crystal display
JP4269582B2 (en) Liquid crystal display device, control method thereof, and portable terminal

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040203

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040405

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20040615

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20040616

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090625

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100625

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100625

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110625

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120625

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120625

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130625

Year of fee payment: 9

LAPS Cancellation because of no payment of annual fees