JPH0666640B2 - Switch control circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention uses a switch circuit and a capacitive element to function equivalently to a resistance element and realizes a circuit such as an integrator or a filter. The present invention relates to a switch control circuit that controls ON / OFF of a switch circuit in a circuit.

[Conventional technology]

The switched capacitor circuit realizes various filters and analog / digital converters by connecting the switch circuit, the capacitive element and the operational amplifier.

The basic principle is to implement a function equivalent to that of a resistance element by turning on / off a switch circuit to charge / discharge a signal voltage to / from a capacitive element and to cause a current proportional to the signal voltage to flow.

FIG. 6 is an example diagram of a conventional switched capacitor circuit, and illustrates a switched capacitor integrator. This is a device that uses four switch circuits so that it is not affected by parasitic capacitance (for example,
Martin and Adel S Sedra “Streys-Insensit”
ive Switched-Capacitor Filters Based on Bilinear Z
-transform "Electronics letters 21st June 1979 Vol,
15 No, 13 pp 365-366).

In FIG. 6, 1 to 4 are switch circuits, 15 is a switch control circuit, 21 and 22 are capacitive elements, 23 is an operational amplifier, 30 is a clock input element, 31 is a signal input terminal, and 32 is a signal output terminal. The switch circuits 1 to 4, the switch control circuit 15, and the capacitance element 21 form a sampling circuit, and the capacitance element 22 and the operational amplifier 23 form an integration circuit.

Further, the switch control circuit 15 is configured by using logic gate circuits 50 and 51 and a delay circuit 52 as shown in FIG. 7, for example. Then, the clock signal CLK-0 as shown in FIG.
It outputs LK-A and CLK-B.

The switch circuits 1 to 4 in FIG. 6 turn on when the control signal is "High", and turn off when the control signal is "Low". The control signal CLK-A simultaneously controls the switch circuits 1 and 3, and the control signal CLK-B simultaneously controls the switch circuits 2 and 4.

The operation of the above circuit is as follows.

That is, in the period of t ₁ in FIG. 8, the switch circuits 1 and 3 are turned on, the switch circuits 2 and 4 are turned off, and the signal input terminals are turned on.
The capacitive element 21 is charged with the signal voltage applied to 31.

Next, in the period of t ₃ , the switch circuits 2 and 4 are turned on, the switch circuits 1 and 3 are turned off, and the charge of the capacitance element 21 is integrated into the capacitance element 22 of the integration circuit. Note that all the switch circuits are off during the period of t ₂ and t ₄ , but this is because the switch circuits 1 and 2 or 3 and 4 are set in order to ensure that the electric charge of the capacitor 21 is held. It is designed to avoid being turned on at the same time.

[Problems to be solved by the invention]

In the conventional switched capacitor circuit as described above, there is a problem that an error is generated in the electric charge to be integrated due to the clock noise when the switch circuits 1 to 4 are turned on and off.

The details will be described below.

FIG. 9 is an example of a switch circuit used as 1 to 4 in FIG. 6, in which an n-channel MOS transistor 41, p
It is an example of a switch circuit using a channel MOS transistor 42 and an inverter 43. Incidentally, 44 and 45 are signal input / output terminals, and 46 is a control signal input terminal.

In the switch circuit as above, the MOS transistor has parasitic capacitance between the gate and the source and drain, so the voltage change of the control signal leaks to the source and drain terminals (signal input / output terminals 44 and 45) through the parasitic capacitance. This becomes clock noise.

FIG. 10 shows the voltage V _{7 at} nodes 7 and 8 of FIG.
FIG. 7 is a diagram showing the relationship between changes in V ₈ and clock noise.

In FIG. 10, v ₁ is the input signal voltage in the period t ₁ , and v ₄
Are the input signal voltages in the period t ₁ of the next cycle, and these are the voltages that change with time. Since the magnitude of the parasitic capacitance of the MOS transistor changes depending on the voltage of the source terminal and the drain terminal, if the input terminal voltage changes as described above, the magnitude of clock noise also changes.

Clock noise is the change in clock waveform T ₁ , T ₂ , T ₃ , T ₄
The noise occurs at four points of (T ₀ ), but what is affected by the signal voltage is the clock noise generated at the points of T ₁ and T ₂ .

At time T ₁ , the switch circuits 1 and 3 are turned off, but at this time, the input / output terminal voltage of the switch circuit 3 is always constant at the ground voltage.

However, output terminal voltage v ₁ of the switch circuit 1 varies with the input signal voltage. Although clock noise is added to this voltage v ₁ and becomes v ₂ , the capacitive element 21 is charged with the voltage of (v ₂ −v ₅ ) during the period t ₂ , and this charge is integrated after time T _2. It

At time T ₂ , the switch circuits 2 and 4 are turned on, but the voltage V _{7 of the} node 7 rapidly becomes the ground voltage, so the operational amplifier 23 does not follow up, and immediately after time T ₂ , the voltage V ₈ is transiently changed to v Touch up to a voltage of ₆ .

Since this voltage v ₆ is a voltage that is substantially proportional to the voltage v ₁ , it affects clock noise when the switch circuit 4 is turned on.

Further, since the parasitic capacitance value of the MOS transistor changes nonlinearly with the source-drain voltage, it also exhibits nonlinear dependence when the clock noise is affected by the input signal voltage. Therefore, there is a problem that the integrated charge is not completely proportional to the input signal voltage, distortion occurs, and it becomes impossible to realize a highly accurate switched capacitor circuit.

It is an object of the present invention to solve the problems of the prior art as described above and to provide a highly accurate switched capacitor circuit.

[Means for solving problems]

In order to achieve the above object, in the present invention, in a switched capacitor circuit including the above-mentioned four switch circuits, a capacitive element and an integrating circuit, when switching from the integrating state to the charging state, first, Controlling each switch circuit to turn off the switch circuit of No. 4, then turn on the third switch circuit, then turn off the second switch circuit, and then turn on the first switch circuit; When switching from the charging state to the integrating state, first, the third
To turn off the switch circuit, then turn on the fourth switch circuit, then turn off the first switch circuit, and then turn on the second switch circuit. It is configured to be equipped.

With the above configuration, the circuit of the present invention operates as follows.

That is, when switching from the integration state to the charging state, first, the integration circuit side terminal of the capacitive element is disconnected from the integration circuit, then the integration circuit side terminal is connected to the first voltage terminal (eg, ground potential), and then the Each switch circuit is controlled so that the input side terminal of the capacitive element is disconnected from the first voltage terminal, and then the input side terminal is connected to the input voltage terminal,
When switching from the charging state to the integrating state, first, the integrating circuit side terminal of the capacitive element is disconnected from the first voltage terminal, then the integrating circuit side terminal is connected to the integrating circuit, and then the input side of the capacitive element is connected. Each switch circuit is controlled to connect the terminal to the input voltage terminal and then disconnect the input side terminal from the first voltage terminal.

As described above, by controlling the four types of switch circuits by the four types of control signals and turning them on and off at different predetermined timings, respectively, a precise switched capacitor circuit that does not generate distortion due to clock noise Can be realized.

Example of Invention

 FIG. 1 is a diagram showing an embodiment of the present invention.

In FIG. 1, 1 to 4 are switch circuits, 16 is a switch control circuit, 21 and 22 are capacitive elements, 23 is an operational amplifier, 30 is a clock input terminal, 31 is a signal input terminal, and 32 is a signal output terminal. Switch circuits 1 to 4 and switch control circuit described above
The 16 and the capacitance element 21 form a sampling circuit, and the capacitance element 22 and the operational amplifier 23 form an integration circuit.

In the apparatus of FIG. 1, four kinds of switch circuits 1 to 4 are provided with different control signals CLK-1, CLK-2, CLK-.
3 and CLK-4, respectively, to turn on and off at different timings.

The switch control circuit 16 for outputting the above-mentioned four kinds of control signals can be composed of, for example, four logic gate elements 53 to 56 and three delay circuits 57 to 59 as shown in FIG.

Clock signal CLK− in the above switch control circuit 16
The relationship between 0 and the four kinds of control signals CLK-1 to CLK-4 has a characteristic as shown in FIG. 2, for example.

The switch circuits 1 to 4 are turned on when the control signal is "High" and turned off when the control signal is "Low", as in the case of FIG.

FIG. 3 is a diagram showing operating waveforms of the voltages V ₇ and V ₈ of the nodes 7 and 8 in the circuit of FIG.

The operation of the circuit shown in FIG. 1 will be described below with reference to FIGS. 2 and 3.

First, in the period t ₁ , the switch circuits 1 and 3 are on,
The capacitive element 21 is charged with the voltage of the input signal.

From the above described state of charge, the switch circuit 3 is turned off at time T ₁ .

At this time, the voltage of the input / output terminal of the switch circuit 3, that is, the voltage V _{8 of the} node 8 is always at the ground potential regardless of the input signal voltage. Therefore, the clock noise v ₅ generated from the switch circuit 3 is always constant. That's it.

Next, when the switch circuit 4 is turned on at the time point T ₂ , the node 8 becomes the inverting input terminal of the operational amplifier 23 (the input terminal of the integrator).
And the clock noise generated from the switch circuit 3 is integrated so that the voltage V ₈ at the node 8 becomes the ground voltage again.

Next, when the switch circuit 1 is turned off at the time point T ₃ , the voltage at the input / output terminal of the switch circuit 1 is the input signal voltage v ₁ , so the clock noise is affected by the input signal voltage.

However, since the switch circuit 4 is already turned on at that time, the charge amount integrated in the capacitive element 22 of the integrating circuit is the amount of change in the terminal voltage on the input terminal side of the capacitive element 21, that is, at time T ₃ . It is determined by the voltage difference between the voltage v ₁ and the voltage (ground voltage) at time T ₅ which is the end of the integration period t ₅ .

Therefore, independent of the transient voltage variation amount of charge is the integral of the voltage V _7, V ₈ in the period t ₄ ~t ₅ between the times T ₃ and time T _5.

Therefore, the voltage V _{7 of the} node ₇ becomes v ₂ due to the clock noise generated in the switch circuit 1, and the switch circuit 2
Even if the voltage V _{8 of the} node 8 becomes v ₆ when is turned on, it does not affect the integrated charge amount.

In this way, if the charging period t ₁ is switched to the state of the integration period t _{5 in} the above-mentioned order, the integrated charge is exactly proportional to the input signal voltage.

On the other hand, when switching from the integration state to the charging state, first, the switch circuit 4 is turned off at time T ₅ .

At this time, since the input / output terminal voltage of the switch circuit 4 is the ground voltage, the clock noise is always generated with a constant magnitude.

The subsequent switching order does not directly affect the integrated charge amount because the switch circuit 4 has already been turned off. However, a small voltage change of the node 8 is transmitted through the parasitic capacitance of the switch circuit.

Therefore, at time T ₆ , the switch circuit 3 is turned on to fix the voltage V _{8 of the} node 8 to the ground voltage, and then at time T ₇ and T ₈ , the switch circuit 2 and the switch circuit 1 are switched to the charging state. , And is not affected by the clock noise of the switch circuits 1 and 2 and the voltage change of the node 7.

Turn on the switch circuit according to the sequence described above.
By controlling the OFF, the integrated clock noise becomes constant independent of the input signal voltage, so the integrated charge becomes a value that is accurately proportional to the input signal voltage, and a highly accurate switched capacitor circuit can be realized. You can

It should be noted that alternating current is used as an input signal when sampling a voice signal or the like using the circuit of the present invention.
When used as a digital converter, direct current may be used as an input signal.

Further, in the switch control circuit shown in FIG. 4, the timing of the control signals CLK-3 and CLK-4 (time t ₂ and t _{6 in} FIG. ₂ ) is determined by the delay time of the delay circuit 57. Also,
The delay time of the delay circuit 58 determines the times t ₃ and t _{7 in} FIG. 2, and the delay time of the delay circuit 59 determines the times t ₄ and t ₈ .

Such a delay circuit can be generally easily realized by connecting even stages of inverter circuits.

Further, the length of the delay time is set in consideration of the response speed of the switch circuits so that the operations of the switch circuits do not overlap. However, control signals CLK-1 and CLK-
Since the period of t ₄ and t ₈ which is the time difference from 2 do not affect the accuracy of the integration operation, if there is no problem even if the switch circuits 1 and 2 are turned on at the same time and current flows, there is no problem. 2 and 2 may overlap and operate. In that case, the times t ₄ and t ₈ can be set to a timing close to zero.

Next, FIG. 5 is a diagram of another embodiment of the present invention.
An example in which the present invention is applied to a switched capacitor circuit different from the illustrated embodiment will be shown.

The circuit shown in FIG. 5 is an oversampling type analog / digital converter that converts an analog signal into a digital signal with 1-bit resolution.
It is a digital conversion circuit.

In FIG. 5, 5 and 6 are switch circuits, 24 is a voltage comparator, 25 is a delay circuit, 26 is a capacitance element, 27 is a polarity switching circuit, 33 is a reference voltage input terminal, 34 is an analog signal input terminal, and 35 is This is a digital signal output terminal, and the same reference numerals as those in FIG.

In the device of FIG. 5, the voltage difference between the analog input signal and the feedback signal is integrated by the integrator, and the integrated voltage is calculated by the voltage comparator 24.
Is converted into a digital signal, and this signal is used as a feedback signal in the next clock cycle.

The polarity switching circuit 27 switches the control signals input to the switch circuits 5 and 6 to integrate the reference voltage with either positive or negative polarity.

In addition, a control signal CLK- for controlling the switch circuits 5 and 6
1 and CLK-2 are the same as the control signals for controlling the switch circuits 1 and 2, and two sets of the switch circuits 1 and 2 and the capacitor element 21 circuit in the switched capacitor integrator of FIG. 1 are prepared. By connecting them in parallel, two voltages can be integrated at the same time.

In the circuit of FIG. 5, it is of course possible to use two sets of the switch circuits 3 and 4 and connect the output of each switch circuit 4 to the input of the integrating circuit.

As described above, the switch control circuit of the present invention can be applied to various switched capacitor circuits.

〔The invention's effect〕

As described above, in the switch control circuit of the present invention, the dependency of clock noise generated from the switch circuit of the switched capacitor circuit on the input signal voltage can be eliminated.

Therefore, the integral operation, which is the basic operation of the switched capacitor circuit, can be performed with extremely high accuracy.
It is possible to obtain the effect that the nonlinearity in the input / output characteristics of the switched capacitor circuit can be removed and the occurrence of distortion can be suppressed.

Further, when the filter is composed of the switched capacitor circuit, since the output is an analog signal, the effect of directly reducing the distortion of the output signal can be obtained.

Further, when the switched capacitor circuit is applied to the analog signal processing of the analog / digital converter, it is possible to improve the conversion accuracy of the digital output.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is an embodiment of a control signal waveform in a switch control circuit of the present invention,
FIG. 3 is an operation waveform diagram in the embodiment of FIG. 1, FIG. 4 is an embodiment diagram showing a concrete configuration of the switch control circuit, and FIG.
6 is another embodiment of the present invention, FIG. 6 is an example of a conventional device, FIG. 7 is an example of a switch control circuit in the conventional device, FIG. 8 is a control signal waveform diagram in the circuit of FIG. FIG. 9 is a concrete configuration diagram of the switch circuit, and FIG. 10 is an operation waveform diagram in the apparatus of FIG. <Description of symbols> 1 to 6 ... switch circuit 15, 16 ... switch control circuit 21, 22, 26 ... capacitive element, 23 ... operational amplifier 24 ... voltage comparator, 25 ... delay circuit 27 ... Polarity switching circuit, 30 …… Clock input terminal 31 …… Signal input terminal, 32 …… Signal output terminal 33 …… Reference voltage input terminal 34 …… Analog signal input terminal 35 …… Digital signal output terminal

Claims (2)

[Claims] 1. A first switch circuit connected between an input side terminal of a capacitance element and an input voltage terminal, and a first switch circuit connected between the input side terminal of the capacitance element and a first voltage terminal. 2 switch circuit, the integrating circuit side terminal of the capacitance element, and the first
A third switch circuit connected between the voltage terminal of
A fourth switch circuit connected between an integrating circuit side terminal of the capacitive element and an input terminal of the integrating circuit, and by turning on / off the first to fourth switch circuits at a predetermined timing, In a switched-capacitor circuit that charges the capacitance element with an input voltage, and integrates the charged charge in the integration circuit, from an integration state in which the charge of the charging element is integrated to a charge state in which the capacitance element is charged. When switching, first the fourth switch circuit is turned off, then the third switch circuit is turned on, then the second switch circuit is turned off, and then the first switch circuit is turned on. In order to control each of the switch circuits as described above and to switch from the charge state to the integration state, first turn off the third switch circuit, and then turn No. 4 is turned on, then the first switch circuit is turned off, and then the second switch circuit is turned on. Switch control circuit. 2. The input voltage, the capacitance element, the first switch circuit, and the second switch circuit are respectively provided in plurality, and a plurality of input voltages are integrated simultaneously. The switch control circuit according to item 1.