JPH09284096A - Switched capacitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit the influence of feed-through noise to be min. and to improve the arithmetic precision of an integrating equipment, etc., and the converting precision of an A/D converter by setting the timing of the control clock of a switches so as to permit feed-through noise not to give difference to the arithmetic result of an operation amplifier. SOLUTION: When the switches are turned off in order of SW4→SW1, a node N2 becomes floating and, then, the switch SW1 is turned off so that feed- through noise generated by the switch SW1 is not stored in sampling capacitance C1. When the switches are turned on in order of SW3→SW2, the potential of the node N2 is the same as that of the node N3 before turning on the switch SW2 so that feed-through noise generated at the time of turning on SW3 is fixed regardless of the charging voltage of sampling capacitance C1 and the variation of integrating precision owing to feed-through noise is prevented. Therefore, the influence of voltage dependence in feed-through noise which is generated in the switches SW1-SW4 is restricted to min.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit technology, and further to a switch feedthrough in a switched capacitor circuit composed of MOS transistors and capacitors.
The present invention relates to a technique that is effective when applied to the reduction of noise errors, for example, a technique that is effective when applied to an integrator using a switch capacitor circuit.

[0002]

2. Description of the Related Art In converting a circuit including a resistor into a semiconductor integrated circuit, there is a switched capacitor circuit in which the resistor is replaced with a switch composed of a MOSFET and a capacitor.
In the switched capacitor circuit, the switch MOS
There is a problem of so-called feedthrough noise that is transmitted to the source and drain sides through the parasitic capacitance existing between the gate and the source and drain of the FET when it is turned on and off.

Japanese Patent Publication No. 6-91419 discloses a conventional method for reducing an error due to feedthrough noise in an integrator using a switched capacitor circuit. This prior invention is to reduce the effect of feedthrough noise error by considering the timing (sequence) of switches that are turned off when the circuit shifts from the sampling state to the integrating state.

[0004]

However, this technique has two drawbacks. First, although the feedthrough noise has a characteristic that its magnitude varies depending on the voltage applied between the source and drain of the switch MOSFET, in the invention of the prior application, only the timing of turning off the switch is considered and the feed-on noise is turned on. Since it does not deal with the timing to do so, the voltage dependence of the feedthrough error cannot be minimized. Secondly, in the above-mentioned prior invention, two clocks having the same cycle but different duty are required, which complicates the circuit.

In order to realize an integrator and an A / D converter with high calculation accuracy by using a switched capacitor circuit,
It is impossible to ignore the effects of dosle-noise.
If this noise is added to the integration result irrespective of the voltage across the switch, the error due to the feedthrough noise generated in the switched capacitor circuit can be minimized.

An object of the present invention is to realize a switched capacitor circuit capable of minimizing the influence of feedthrough noise, and to improve the calculation accuracy of an integrator or the like and the conversion accuracy of an A / D converter. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

In order to achieve the above object, the present invention considers the timing of turning on the switch in addition to the timing of turning off the switch of the switched capacitor circuit. The timing of the control clock of the switch is set so that the feedthrough noise generated at the time of turning off does not give an error to the calculation result of the operational amplifier.

Specifically, in the case of a positive-phase integration type switched capacitor circuit in which an input signal is sampled with respect to a reference potential (analog ground) and the result is integrated using an operational amplifier, the analog ground is provided at the end of the sampling operation. The switch on the input signal side is disconnected after the switch on the side is disconnected, and at the start of the integration operation, the switch on the inverting input terminal side of the operational amplifier is connected and then the switch on the analog ground side is connected.

In addition, the sampling capacitor is connected to the reference potential at both ends, one terminal of the capacitor is connected to the input terminal at the time of integration, and the other terminal is connected to the inverting input terminal of the operational amplifier. In the case of a capacitor circuit,
At the end of the integration operation, the switch on the inverting input terminal side of the operational amplifier is disconnected and then the switch on the input signal side is disconnected, and at the start of the integration operation, the switch on the inverting input terminal side of the operational amplifier is connected and then the switch on the input signal side is disconnected. To be connected.

According to the above means, the voltage dependence of the feedthrough-noise error can be minimized, and the order of turning on the switches and the order of turning off the switches are the same. The switch control clock can be created by simply delaying this from one clock.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of a positive phase integral type switched capacitor circuit to which the present invention is applied. The switched capacitor circuit (integrator) of this embodiment has a switch SW1 connected between an input terminal IN to which an analog signal is input and a node N1, and a node N1 and an analog ground AGND as a reference potential. Connected switch SW2, operational amplifier AMP, operational amplifier A
A switch SW3 connected between the inverting input terminal (−terminal) of MP and the node N2, a switch SW4 connected between the node N2 and AGND, and the nodes N1 and N.
2 is composed of a sampling capacitor C1 connected between 2 and 2, and an integration capacitor C2 connected between the output terminal and the inverting input terminal (− terminal) of the operational amplifier AMP.

The switches SW1 to SW4 are
N-channel MOSFET and P-channel MO respectively
It is composed of a CMOS switch in which an SFET and a switch are connected in parallel, and the MOSFETs of each switch pair are turned on / off at the same time by applying a control clock of opposite phase to its gate terminal.

That is, the switch SW1 is composed of an N-channel type MOSFET Q11 and a P-channel type MOS.
FET Q12, which are turned on / off at the same time by applying opposite phase control clocks φ22 and / φ22 to their gate terminals. Further, the switch SW2 is an N-channel type MOSFET Q21 and P
The channel type MOSFET Q22 is configured to be turned on / off at the same time by applying control clocks φ12 and / φ12 of opposite phases to their gate terminals.

On the other hand, the switch SW3 includes an N-channel type MOSFET Q31 and a P-channel type MOSFET.
TQ32, which are turned on / off at the same time by applying opposite-phase control clocks φ11 and / φ11 to their respective gate terminals. Switch SW4 above
Is composed of an N-channel type MOSFET Q41 and a P-channel type MOSFET Q42, which are turned on / off at the same time by applying opposite phase control clocks φ21 and / φ21 to their gate terminals. In addition,
Control clock / φ11, / φ12, / φ21, / φ
22 is obtained by inverting φ11, φ12, φ21, and φ22 using an inverter, respectively. In FIG. 1, an inverter G for inverting the clock φ22 is representatively shown.

FIG. 2 shows the states of the switches SW1 to SW4 during sampling and integration in the switched capacitor circuit of FIG. 1, and FIG. 5 shows the timings of the control clocks φ11 to φ22. In FIG. 5, T1 is a sampling period and T2 is an integration period. φ1 and φ2 are reference clocks. During the sampling period T1, the control clocks φ21 and φ22 are set to the high level and φ11 and φ12 are set to the low level, and the switches SW1 to SW4 are brought into the state shown in FIG. 2 (a). As a result, the sampling capacitor C1 is connected to the input terminal I
The capacitor C1 is connected between N and the analog ground AGND, and charges corresponding to the potential of the signal input to the input terminal IN at that time are accumulated in the capacitor C1.

During the integration period T2, the control clock φ1
1, φ12 is set to the high level, φ21 and φ22 are set to the low level, and the switches SW1 to SW4 are brought into the state as shown in FIG. As a result, the sampling capacitor C1 is connected between the analog ground AGND and the inverting input terminal of the operational amplifier AMP, and the sampling capacitor C1 is connected.
The charge accumulated in 1 is transferred to the integrating capacitor C2 and the integrating operation is performed by the operational amplifier.

In the positive phase integration type circuit of FIG. 1, the potential of the node N1 varies depending on the potential of the signal input from the input terminal IN, but the node N2 is always at the same potential as the reference voltage (analog ground AGND). . In order to prevent the error due to the switch feed-through noise from appearing in the integration result, it is necessary to prevent the node N3 from being affected by the feed-through noise. Therefore, in this embodiment, the off timing of the switches SW1 and SW4 and the on timing of the switches SW2 and SW3 are important.

The operation of turning off the switches SW1 and SW4 occurs during sampling → integration. At this time, if the switches SW4 → SW1 are turned off in this order, first the node N
Since the switch SW1 is turned off after 2 becomes floating, the feedthrough noise generated in the switch SW1 is not accumulated in the sampling capacitor C1. Conversely, when the switches SW1 → SW4 are turned off in this order, the switch SW1 is turned off while the node N2 is connected to the reference potential, so that the feedthrough noise generated by the switch SW1 is stored in the sampling capacitor C1.

However, in this embodiment, as shown in FIG.
As shown in (f), the change of the control clock φ22 from the high level to the low level is delayed by Δt from the change of the control clock φ21 from the high level to the low level. Therefore, the switches SW1 and SW4 are turned off in the order of SW4 → SW1, and the sampling capacitance C1.
The feedthrough noise generated by the switch SW1 is prevented from being accumulated.

In this embodiment, the control clock φ2
The change from the low level to the high level of 2 is Δ more than the change from the low level of the control clock φ21 to the high level.
It is supposed to be delayed by t. That is, the switch SW
The switches are turned on in the order of 4 → SW1, but even if feedthrough noise is generated when the switch SW1 is turned on (start of sampling operation) and accumulated in the capacitor C1, the level immediately changes according to the input signal. Therefore, there is no influence of feedthrough noise on the integration operation. Therefore, in this embodiment, the control clock φ22 is changed to the high level or the low level by Δt more than the control clock φ21.
The control clock φ22 can be formed by simply delaying the control clock φ21 by Δt.

On the other hand, the operation of turning on the switches SW2 and SW3 occurs during sampling → integration. At this time, when the switches SW3 → SW2 are turned on in this order, since the nodes N2 and N3 have the same potential (analog ground) before the switch SW2 is turned on, the feedthrough noise generated when the switch SW3 is turned on is generated by the sampling capacitor C1. It is constant regardless of the charging voltage. Conversely, switch SW2 → S
When turned on in the order of W3, the potential fluctuation of the node N1 (change from the input potential to the ground potential) is caused by the sampling capacitor C1.
After being transmitted to the node N2 via the switch, the switch SW3 connects the nodes N2 and N3. Therefore, the node N2 has a voltage corresponding to the sampled input potential, and the nodes N2 and N3 do not have the same potential. Therefore, when the switch SW3 is turned on, feedthrough noise having voltage dependency is generated and added at the time of integration. , The accuracy of the integration result varies.

However, in this embodiment, as shown in FIG.
As shown in (d), the change of the control clock φ12 from the low level to the high level is delayed by Δt from the change of the control clock φ11 from the low level to the high level. Therefore, since the switches SW2 and SW3 are turned on in the order of SW3 → SW2, the generated feedthrough noise becomes constant regardless of the charging voltage of the sampling capacitor C1, and the variation of the integration accuracy due to the feedthrough noise is prevented. .

In this embodiment, the control clock φ1
The change from the high level to the low level of 2 is Δ more than the change from the high level of the control clock φ11 to the low level.
It is supposed to be delayed by t. That is, the switch SW
Although the switches are turned off in the order of 3 → SW2, even if the feedthrough noise is generated when the switch SW3 is turned off (the integration operation is completed), the nodes N1, N2 and N3 are both at the ground potential, so that they are generated. The feedthrough noise is constant and does not affect the integration result. Therefore, both the change from the low level to the high level of the control clock φ12 and the change from the high level to the low level may be delayed from the control clock φ11 by Δt, and the control clock φ12 is formed by simply delaying the control clock φ11 by Δt. can do.

In order to confirm the effect of the present invention, a simulation
Was carried out. In the circuit of FIG. 1, the reference voltage (A
GND) is 2.1V, the ratio of the capacitors C1 and C2 is 1: 2, and the input voltage is 3.3V, 2.7V, 2.1V, 1.5V,
The control clocks φ11 to φ22 for 0.9 V are shown in FIG.
Simulations were performed at the timings shown in (A), (B), and (C), and the integration errors were compared. In FIG. 6, (A) is the timing of the present invention,
(B) is the conventional (Japanese Patent Publication No. 6-91419) timing,
(C) is the timing when the switch-on timing is shifted in the direction opposite to that of the present invention in (B).

The simulation result shows that the input voltage is 3.
The relative error worst value of the integration result at 5 points of 3 V to 0.9 V is 0.5 mV in (A) and 0.7 mV in (B),
In (C), it was 5.1 mV. From this, (A),
Although there is no big difference between (B) and the result is very good, it can be confirmed that it is greatly deteriorated in (C). (B) and (C) are differences in whether the switch-on timings (that is, the rising edges of the control clocks) are the same or slightly misaligned. When mounted on an LSI, it is extremely difficult for clocks to arrive at the same time due to differences in device characteristics such as wiring capacitance. That is, when the clock is set as shown in (B), the timing of the clock reaching the integrator becomes as shown in (C), and it is considered that the accuracy of the circuit is deteriorated. Therefore, at least in the clock generation circuit, it is preferable to set the timing of the control clock to the timing shown in (A). From the above viewpoint, the clock φ1
It is desirable that the delay amount Δt of 2 and φ22 with respect to φ11 and φ21 is set to be slightly larger than the maximum variation in the clock arrival time from the clock generation circuit or the clock input terminal to the integrator. Δt can be created by using the gate delay time of a logic circuit such as an inverter.

FIG. 3 shows an embodiment of an anti-phase integration type switched capacitor circuit to which the present invention is applied. The configuration of the anti-phase integration type switched capacitor circuit of the present embodiment is the same as the configuration of the positive phase integration type switched capacitor circuit shown in FIG. The difference is that the switch SW1 in the embodiment of FIG.
Is turned on / off by the control clocks φ22, / φ22 and the switch SW2 is turned on / off by the control clocks φ12, / φ12, respectively, whereas in the circuit of the embodiment of FIG. 3, the switch SW1 is turned on by the control clocks φ12, / φ12. Control clock φ22, / φ22
It is only that they are turned on and off respectively. The timing of each of the control clocks φ11 to φ22 is the same as in the case of FIG. 1, and the clocks of the timing shown in FIG. 5 are used.

FIG. 4 shows the states of the switches SW1 to SW4 during sampling and integration operation in the switched capacitor circuit of FIG. In FIG.
T1 is a reset period and T2 is an integration period. During the reset period T1, the control clocks φ21 and φ22 are set to the high level, φ11 and φ12 are set to the low level, and the switch S
W1 to SW4 are brought into a state as shown in FIG. As a result, both terminals of the sampling capacitor C1 are connected to the analog ground AGND, and the charge of the capacitor C1 is reset.

During the integration period T2, the control clock φ1
1, φ12 is set to the high level, φ21 and φ22 are set to the low level, and the switches SW1 to SW4 are brought into the state as shown in FIG. 4B. As a result, the sampling capacitor C1 is connected between the input terminal IN and the inverting input terminal of the operational amplifier AMP, and the charges corresponding to the potential of the signal input to the input terminal IN are charged in the sampling capacitor C1 and the integrating capacitor C2. Then, the integrating operation is performed by the operational amplifier.

In the case of the anti-phase integrator circuit, what matters is the timing at which the switches SW1 and SW3 are turned on and off. That is, when the switches SW1 and SW3 are turned on, if the order is switch SW3 → SW1, the node N
2 and N3 have the same potential, and the generated feedthrough noise is constant. On the contrary, if the order of the switches SW1 → SW3 is, the potential fluctuation of the node N1 is transmitted to the node N2 via the capacitance C1 and then the nodes N2 and N3 are connected to each other. Is added during integration.

On the other hand, when the switches SW1 and SW3 are turned off, if the order is switch SW3 → SW1, the node N
2 and N3 have the same potential, and the generated feedthrough noise is constant. On the contrary, if the order of the switches SW1 → SW3 is, the feedthrough noise having the voltage dependency generated in the switch SW1 is transmitted to the node N3 via the capacitor C1 and the switch SW3, and is added to the integration result. The switches SW2 and SW4, which are not taken into consideration, have SW1 and SW3 turned off when they are turned on and off. Therefore, no matter which of SW2 and SW4 is turned on or off first, the integration node N3 is affected by feedthrough noise. There is no effect.

In the anti-phase integrator circuit of this embodiment, as shown in FIG.
By using the clocks φ11 to φ22 having the timings shown in FIG. 3, both the change timing of the clock φ12 to the high level and the change timing to the low level are delayed from the clock φ11 by Δt.
Since the switches are turned on in the order of SW1 and turned off in the order of SW3 → SW1, variations in integration accuracy due to feedthrough noise are prevented when the switches SW1 and SW3 are turned on and off.

Further, when the switch timing is set as described above, the order of turning on and turning off the switches becomes the same, so that the two types of switch control clocks necessary for each mode can be obtained by simply delaying the clocks. Can be generated. As the clock for controlling the switch SW2, the same clock φ as the switch SW4 is used instead of φ22.
21 may be used, or φ22 may be commonly used for SW2 and SW4.

FIG. 7 shows an embodiment in which the switched capacitor circuit according to the present invention is applied to an oversampling secondary Δ-Σ type A / D converter.

The oversampling type A / D converter is
The Nyquist sampling frequency (double frequency of the signal frequency band) based on the sampling theorem is sampled at a high frequency of tens to hundreds of times to disperse the frequency distribution of the quantization noise out of the band, and the out-band noise is A highly accurate conversion result can be obtained by removing with a digital filter such as a decimator. In the Δ-Σ type A / D converter, there is a noise shaping effect that pushes the quantization noise into a high frequency band, so that an even higher S / N characteristic can be obtained. The noise shaping effect becomes steeper as the integration order becomes higher, but the second-order Δ-Σ type is general.

In the second-order Δ-Σ type A / D converter shown in FIG. 7, the analog signal input from the terminal 61 outputs the digital signal output result of one sampling before the local D / Σ conversion.
After subtracting with the one returned to analog in A604,
The integrator 601 executes the first analog integration. Subsequently, this integrated output is subtracted from the above-mentioned data one sampling before, and then the integrator 602 performs the second analog integration. The result is judged by the comparator of the circuit 603, and the digital signal output can be obtained from the terminal 62. Reference numerals 605 and 606 are subtractors. Figure 7
As a circuit having the functions of the integrator 601 and the subtractor 605 shown in FIG. 6 and a circuit having the functions of the integrator 602 and the subtractor 606, a diagram in which a switched capacitor 608 is added to the integrator shown in FIG. A circuit as shown in 8 is used.

The integrators 601 and 602 are controlled so that when one is sampling, the other is integrating. Further, a clock generation circuit 607 for generating the control clocks φ11 to φ22 used in the integrators 601 and 602 is provided. A digital filter such as a decimator is connected after the terminal 62.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

In the above description, the case where the invention made by the present inventor is mainly applied to an integrator which is a field of application which is the background of the invention has been described. However, the present invention is not limited thereto and a switched capacitor is used. An analog circuit using a circuit can be generally used.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, it is possible to minimize the influence of the voltage dependence of the feedthrough noise generated in the switch of the integral type switched capacitor circuit on the integration result.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a positive phase integral type switched capacitor circuit to which the present invention is applied.

FIG. 2 is an operation explanatory diagram showing states of respective switches during a sampling operation and an integration operation of the positive-phase integral type switched capacitor circuit of FIG.

FIG. 3 is a circuit diagram showing an embodiment of an anti-phase integration type switched capacitor circuit to which the present invention is applied.

FIG. 4 is an operation explanatory view showing states of respective switches at the time of sampling operation and integration operation of the anti-phase integration type switched capacitor circuit of FIG.

FIG. 5 is a timing chart of a switch control clock used in the switched capacitor circuit of the embodiment.

FIG. 6 is a timing chart of clocks used for comparison simulation.

FIG. 7 is a circuit configuration diagram showing an embodiment in which the switched capacitor circuit according to the present invention is applied to an oversampling secondary Δ-Σ type A / D converter.

8 is an oversampling secondary Δ-Σ A / D of FIG.
It is a circuit diagram which shows the structural example of the integrator which comprises a converter.

[Explanation of symbols]

 IN input terminal SW1 to SW4 switch C1 sampling capacity C2 integration capacity AMP operational amplifier φ11 to φ22 control clock

Claims (6)

[Claims] 1. A switched capacitor circuit in which the timing of a control clock of a switch is set so that feedthrough noise generated when the switch is turned on and off does not give an error to a calculation result of an operational amplifier. 2. A positive-phase integration type switched capacitor circuit which samples an input signal with respect to a reference potential and integrates the result by using an operational amplifier. The switch on the reference potential side at the end of the sampling operation of the switch operating at the time of sampling. First, disconnect the switch on the input signal side, and then connect the switch on the inverting input terminal side of the operational amplifier first and then the switch on the reference potential side at the start of integration operation of the switch that operates during integration. The switched capacitor circuit is characterized by 3. A sampling capacitor having both ends connected to a reference potential, one of which is connected to an input signal during integration,
In the reverse-phase integration type switched capacitor circuit in which the other is connected to the inverting force terminal of the operational amplifier, at the end of the integration operation,
The switch on the inverting input terminal side of the operational amplifier is cut off, and then the switch on the input signal side is cut off.At the start of the integration operation, the switch on the inverting input terminal side of the operational amplifier is connected and then the switch on the input signal side is connected. The characteristic is a switched capacitor circuit. 4. A switched capacitor circuit, wherein the switch according to claim 1, claim 2 or claim 3 is a CMOS switch composed of a P-channel MOSFET and an N-channel MOSFET. 5. The switched capacitor circuit according to claim 4, wherein the control clock of the switch is a reference clock and a clock generated by delaying the reference clock. 6. An analog integrator, a D / A converter for D / A converting an output of the analog integrator, and a difference between an output of the D / A converter and an input signal. The analog-integrator comprises a switched capacitor circuit according to claim 1, claim 2, claim 3, claim 4, or claim 5 which is a Δ-Σ type A / D converter. A delta-sigma A / D converter.