JP2009267981A - MIXER AND DeltaSigma MODULATOR - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mixer etc. that downsizes a circuit for AD converting a signal superposed on a carrier. <P>SOLUTION: The mixer includes: a capacitor 35 having a first electrode which is at least connected to an input terminal IN where a modulated wave having a modulation signal superposed on the carrier is inputted; and a second electrode which is at least connected to an output terminal OUT, and has: a first state wherein a connection destination of the first electrode is set to be the input terminal IN and a connection destination of the second electrode is set to be the output terminal and a reference potential; a second state wherein the connection destination of the first electrode is set to be the output terminal OUT and the connection destination of the second electrode is set to be the reference potential; and a third state wherein the connection destination of the first electrode is set to be the reference potential and the connection destination of the second electrode is set to be the output terminal OUT. The mixer switches the first state, second state, first state, and third state in this order at a switching frequency four times as high as the carrier frequency of the carrier to repeat the switching operation of one cycle comprising the first state, second state, first state, and third state. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a mixer and a delta-sigma (ΔΣ) modulator, and more particularly to a mixer and a ΔΣ modulator when a modulated wave to be transmitted with a modulation signal on a carrier wave is input.

Conventionally, a ΔΣ modulator is known as a circuit that can realize a relatively small and highly accurate AD converter. There are several types of this ΔΣ modulator. Generally, the low-pass ΔΣ modulator has a low maximum frequency included in a signal to be AD converted (for example, the maximum frequency is the operation of the switched capacitor circuit in the ΔΣ modulation circuit). The bandpass ΔΣ modulator is used for AD conversion of a signal on a carrier wave that is somewhat high. Patent Document 1 discloses an example in which a bandpass ΔΣ modulator is used for a transceiver.
JP-T-2002-521554

Assume that there is an analog input signal A that is transmitted with a signal C (frequency f _C ) on a carrier B (frequency f _B ) (f _B > f _C ). When AD conversion is performed on the signal C included in the analog input signal A by the bandpass ΔΣ modulator, the analog input signal A is converted into digital data by the bandpass ΔΣ modulator, and the digital data after the conversion is frequency converted by the digital mixer. Is done. However, the band-pass ΔΣ modulator generally has a larger circuit scale than the low-pass ΔΣ modulator having the same order.

On the other hand, when the signal C is AD-converted by the low-pass ΔΣ modulator, the maximum frequency of the signal A is f _B , so that oversampling ratio (= sampling frequency / (2 × analog input) In order to increase the maximum frequency of the signal)), it is necessary to sample at a sampling frequency higher than the maximum frequency (for example, several tens to several hundreds). In order to avoid this, the frequency of the analog input signal A is often lowered by an analog mixer and then input to the low-pass ΔΣ modulator to perform AD conversion.

  However, since the conventional analog mixer is generally composed of analog components such as a diode and a transformer, the circuit scale and the like are increased as compared with the digital mixer.

  As a result, although the circuit scale of the low-pass ΔΣ modulator is smaller than the band-pass ΔΣ modulator of the same order, the combination of the “conventional analog mixer and low-pass ΔΣ modulator” is the “bandpass ΔΣ modulator and digital mixer”. In some cases, the circuit scale may be larger than the combination.

  Therefore, an object of the present invention is to provide a mixer and a ΔΣ modulator that can reduce the size of a circuit for AD-converting a signal carried on a carrier wave.

In order to achieve the above object, the mixer according to the present invention provides:
Sampling means for generating a first multi-valued signal by sampling a modulated wave transmitted with a modulated signal on a carrier wave at a sampling frequency that is a multiple of at least a multiple of the carrier frequency of the carrier wave;
A second multi-value signal is generated by sequentially multiplying the amplitude value of the first multi-value signal by a sample value sampled at each sampling period of the sampling from a periodic function having the same frequency as the carrier frequency. And a multiplying means for performing.

  Here, it is preferable that the multiple is 4, and when the multiple is 4, the sample value may be a sine wave displacement 1, 0, -1, 0.

When the multiple is 4,
The sampling means and the multiplying means are:
A capacitor having at least a first electrode connectable to an input end to which the modulated wave is input and a second electrode connectable to an output end to which the second multi-value signal is output. ,
A state in which the connection destination of the first electrode is the input end and the connection destination of the second electrode is the output end and a reference potential is a first state,
A state in which the connection destination of the first electrode is the output terminal and the connection destination of the second electrode is the reference potential is a second state,
When the state where the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the output end is the third state,
The first state, the second state, the first state, and the third state are switched in order of the sampling period in the order of the first state, the second state, the first state, and the third state. It is preferable to repeat the switching operation in which the third state is one cycle.

The mixer according to the present invention is
A capacitor having a first electrode connectable to at least an input end to which a modulated wave transmitted by transmitting a modulation signal on a carrier wave is input, and a second electrode connectable to at least an output end;
A state in which the connection destination of the first electrode is the input end and the connection destination of the second electrode is the output end and a reference potential is a first state,
A state in which the connection destination of the first electrode is the output terminal and the connection destination of the second electrode is the reference potential is a second state,
When the state where the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the output end is the third state,
The first state, the second state, the first state, and the third state are switched at a switching frequency that is four times the carrier frequency of the carrier wave in the order of the first state, the first state, and the third state. The switching operation in which the state 2, the first state, and the third state are one cycle may be repeated.

In order to achieve the above object, a ΔΣ modulator according to the present invention includes:
An integrator;
A capacitor having at least a first electrode connectable to an input terminal to which a modulated wave transmitted by transmitting a modulation signal on a carrier wave is input, and a second electrode connectable to an input section of the integrator;
A quantizer that outputs a signal obtained by comparing the integrator output signal obtained by integrating the voltage of the input unit of the integrator with a reference potential as a reference with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a third state,
A state in which the connection destination of the first electrode is an input unit of the integrator and the connection destination of the second electrode is an output side of the DA converter is a fourth state,
The state that switches from the first state to the second state is a first transition state,
The state that switches from the third state to the second state is a second transition state,
When the state that switches from the third state to the fourth state is the third transition state,
In the order of the first transition state, the second transition state, the first transition state, and the third transition state, the transition state is transited at a transition frequency that is four times the carrier frequency of the carrier wave, and the first transition state It is preferable to repeat a transition operation in which one transition state, the second transition state, the first transition state, and the third transition state are one cycle.

  According to the present invention, a circuit for AD converting a signal carried on a carrier wave can be reduced in size.

  Hereinafter, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a ΔΣ AD converter 20 that is an embodiment of the present invention. The AD converter 20 includes an analog mixer 10 that mixes the analog input signal A at a predetermined frequency, a low-pass filter 21 that receives the mixed signal mixed by the analog mixer 10, and an analog signal that is filtered by the low-pass filter 21. Is input, and a digital filter 23 that performs a filtering process on the digital data AD-converted by the ΔΣ modulator 22 and outputs the digital data. The low-pass filter 21 is provided as necessary. The low-pass filter 21 can properly remove the noise of the input signal input to the ΔΣ modulator 22.

The analog mixer 10 has a sampling unit 11 that samples the analog input signal A at the sampling frequency f _S , and a frequency f _{B that} is the same as the frequency f _{B of the} carrier B that carries the modulation signal included in the analog input signal A that is a modulated wave. A sine wave generator 12 capable of generating a sine wave reference signal as a reference signal represented by a periodic function, and a sampling signal sampled by the sampling unit 11 and the sine wave generated by the sine wave generator 12 are multiplied. And a multiplier 13 for outputting a signal after mixing.

  The ΔΣ modulator 22 is an AD converter architecture that realizes a high resolution of, for example, 14 bits or more. By converting the input signal into a 1-bit digital signal by the ΔΣ modulator 22 and subjecting it to digital filter processing, a highly accurate AD conversion output can be obtained. For example, in a secondary ΔΣ AD converter, if the oversampling ratio is 500 or more, a resolution of more than 16 bits and several tens of μV or less can be sufficiently realized.

  A fixed characteristic digital filter having a fixed filter characteristic may be provided between the ΔΣ modulator 22 and the digital filter 23. Further, thinning processing (decimation) at a constant data interval may be performed after filtering by the fixed characteristic digital filter. In particular, when a moving average filter is applied as the fixed characteristic digital filter, efficient decimation processing with a reduced circuit scale can be performed. For example, assuming that the load is high for processing all 1-bit data of 4 MHz, decimation processing is performed at 62.5 kHz, which is 1/64.

  The ΔΣ modulator 22 outputs a 1-bit digital data string. The digital filter 23 performs a moving average filter process on the digital data string to convert it into multi-bit data, and then performs a thinning (decimation) process, thereby lowering the internal processing frequency of subsequent calculations. Further, it is possible to reduce the subsequent digital filter calculation processing amount and simplify the circuit scale thereafter. Thereafter, based on the output data of the digital filter 23, the value of the modulation signal included in the input signal A is detected by a detection logic unit (not shown).

FIG. 2 is a waveform for explaining the operation of the analog mixer 10. It is assumed that the analog input signal A input to the sampling unit 11 is a signal that transmits the signal C having the frequency f _C on the carrier wave having the frequency f _B (f _B > f _C ). That is, the signal A corresponds to a modulated wave, and the signal C corresponds to a modulated signal. Sampling unit 11 samples the analog input signal A at the sampling frequency f _S. The sampling frequency f _S is set to four times the frequency f _B of the carrier B (f _S = 4f _B ). The sampled multi-level signal output from the sampling unit 11 is assumed to be A _SAMPLE . The multi-value signal A _SAMPLE is a discrete value in amplitude value.

The multiplier 13 mixes the multilevel signal A _SAMPLE with the frequency f _{B of the} sine wave generated by the sine wave generator 12 (the same frequency as the carrier wave B). Since the multilevel signal A _SAMPLE is sampled at the frequency f _S , the amplitude value of the multilevel signal A _SAMPLE changes every time (1 / f _S ) seconds according to the displacement of the analog input signal A. Therefore, the signal of the frequency f _B mixed with the multilevel signal A _SAMPLE in the multiplier 13 is not a continuous time signal but a discrete time signal (sampled-data sequence) only corresponding to the multilevel signal A _SAMPLE. ). That is, mixing can be performed by multiplying the sample value of the discrete-time signal and the multilevel signal A _SAMPLE .

Here, since “f _S = 4f _B ” is set, the multilevel signal A _SAMPLE has four samples sampled at the frequency f _S during time (1 / f _B ). That is, mixing can be performed by sequentially multiplying the amplitude value of the multilevel signal A _SAMPLE by the sample value sampled from the reference signal of the frequency f _B every quarter period. Generalizing this, if the sampling frequency f _S is set to x times the frequency f _B of the reference signal, the sampled specimens values from the reference signal of frequency f _B (1 / x) for each cycle By sequentially multiplying the amplitude value of the multilevel signal A _SAMPLE , mixing can be performed.

Here, the method of selecting the four sample values can be arbitrarily selected as long as it is a value for every ¼ period. However, in order to simplify the circuit scale, the displacement of the sine wave at the frequency f _B is equally spaced in time. As four points, four points “1”, “0”, “−1”, “0” are selected as sample values. That is, in the case of sample values of “1”, “0”, “−1”, “0”, resistance is compared to the case of sample values other than “1”, “0”, “−1”, “0”. This is advantageous in that the circuit scale is reduced because the sample value does not need to be accurately created by partial pressure or the like.

The multiplier 13 converts the multilevel signal A _SAMPLE into
(1) _Multiply "1": Output multi-value signal A _{SAMPLE as it} is (2) _Multiply "0": Output ground reference potential (eg, 0) (3) Multiply "-1": Multi-value Outputs an inverted signal in which the sign of signal A _SAMPLE is inverted
(Or, output a symmetric potential with respect to the reference potential)
(4) Multiply “0”: Four output operations are repeated as one cycle in the order of outputting a reference potential such as ground (for example, 0) (period: 1 / f _B ). Each output operation is switched every time (1 / f _S ).

The output of the multiplier 13 is analog data (multilevel signal) whose value changes every time (1 / f _S ). The analog data output from the multiplier 13 is input to the ΔΣ modulator 22 after cutting an extra frequency band by a filter 21 such as a low-pass filter (LPF) if necessary. The ΔΣ modulator 22 converts it into a 1-bit stream, and the digital data after the filter processing by the digital filter 23 such as a moving average filter is output as output data of the AD converter 20.

  FIG. 3 is a circuit diagram of the analog mixer 10. According to the circuit of FIG. 3, the sampling and mixing operations performed in the analog mixer 10 can be performed simultaneously. The analog mixer 10 outputs a mixed signal obtained by mixing analog input signals input from the input end from the output end. The analog mixer 10 includes an input terminal IN to which an analog input signal A is input as an input signal of the analog mixer 10, an output terminal OUT to which a mixed signal is output as an output signal of the analog mixer 10, an input terminal IN, and an output terminal A capacitor 35 is provided between OUT. Further, the switch 30 as a switching means for selectively switching and connecting the first electrode of the capacitor 35 to the input terminal IN (input terminal 30a), the high impedance Z terminal 30b, and the reference potential terminal 30c connected to the reference potential. And the switch 31 as a switching means for connecting or disconnecting the second electrode of the capacitor 35 to the reference potential, and the output terminal OUT is selectively connected to the first electrode of the capacitor 35 and the second electrode of the capacitor 35. And a switch 32 as a switching means for switching and connecting. The output terminal OUT is connected to a high impedance element such as a CMOS input operational amplifier.

  FIG. 4 is a diagram for explaining the switching operation of the analog mixer 10. 4 by repeating the switch operation of each switch in the order of (1) (2) (3) (4) (1) (2) (3) (4). The above-described multiplication of “1, 0, −1, 0, 1, 0, −1...” Can be realized, and at the same time, the sampling operation in the sampling unit 11 can be realized. Since (1) and (3) in FIG. 4 are the same circuit connection, the number of states of repeated switch operations is three.

In FIG. 4A, the output terminal OUT and the second electrode that is the output terminal OUT side electrode of the capacitor 35 are connected together to the reference potential, and the capacitor 35 is charged with an input signal (input voltage). This state corresponds to applying “0” to the multilevel signal A _SAMPLE .

In FIG. 4B, by disconnecting the connection between the input signal and the capacitor 35, the voltage at the input terminal IN when the capacitor 35 is disconnected is stored (sampling). Further, by connecting the first electrode which is the input terminal IN side electrode of the capacitor 35 to the output terminal OUT, the charging voltage of the capacitor 35 can be transmitted to the output terminal OUT terminal. This state corresponds to applying “1” to the multilevel signal A _SAMPLE .

In FIG. 4 (3), the output terminal OUT and the second electrode of the capacitor 35 are connected to the reference potential together, and the capacitor 35 is charged with an input signal (input voltage). This state is the same as the connection state of FIG. 4A and corresponds to applying “0” to the multilevel signal A _SAMPLE .

In FIG. 4 (4), the first electrode of the capacitor 35 is connected to the reference potential and the second electrode is connected to the output terminal OUT, so that the polarity of the capacitor 35 is reversed from that in FIG. Is transmitted to the output terminal OUT. This state corresponds to applying “−1” to the multilevel signal A _SAMPLE .

By performing the operation of FIG. 4, the multi-value signal A _SAMPLE corresponds to a signal representing the voltage change of the first electrode of the capacitor 35, and the multi-value signal of analog data output from the multiplier 13. Corresponds to a signal representing a voltage change of the output terminal OUT. By such a switching operation of the analog mixer 10, the output signal of the analog mixer 10 is input to the ΔΣ modulator 22 via the low-pass filter 21 as necessary, as shown in FIG.

  An example of the ΔΣ modulator 22 is shown in FIG. FIG. 5 is a block diagram of the first-order ΔΣ modulator 40. The primary ΔΣ modulator 40 outputs a subtractor 41 that outputs a signal obtained by subtracting a feedback signal from an analog input signal, an integrator 42 that integrates and outputs the output signal of the subtractor 41, and an output signal of the integrator 42. A comparator (quantizer) 43 that outputs a comparison with a predetermined threshold, a delay device (for example, a D flip-flop) 44 that is a delay element that delays the output signal of the comparator 15 for a unit time, and a delay device 44 And a 1-bit digital-analog converter (DAC) 45 that converts the digital output signal into an analog signal as the feedback signal and outputs the analog signal.

FIG. 6 is a circuit diagram of the primary ΔΣ modulator 40. The primary ΔΣ modulator 40 includes a switched capacitor to which an analog input signal is input (a capacitor 57 and a changeover switch 51 and a changeover switch 52 provided at both ends thereof), and an operational amplifier 53 that amplifies the output signal of the switched capacitor. And an integration capacitor 54, a comparator 55 to which the output signal of the integrator is input, and a digital signal output from the comparator 55 as a feedback signal to the switching signals of the switched capacitors 51 and 52. As a 1-bit DA converter 56. By the changeover switch is turned on / off according to the switching signal [Phi _A and [Phi _B, connection of the input electrode and the output electrode of the capacitor 57 is selectively changed. [Phi _A is the [Phi _B when on and off, [Phi _A is the [Phi _B when off is turned on. Capacitor 57 for sampling, when the switching signal [Phi _A, samples the analog input signal, when the clock signal [Phi _B is an inverted signal of the clock signal [Phi _A, the difference between the output of the 1-bit DA converter 56 It is configured as an input-side capacitor of an integrator connected to the CMOS operational amplifier 53 side.

  Incidentally, it is possible to arrange the first-order ΔΣ modulator 40 as illustrated in FIGS. 5 and 6 at the subsequent stage of the analog mixer 10 as illustrated in FIGS. And the capacitor 57 of the switched capacitor circuit of the primary ΔΣ modulator 40 can be further reduced in size. In addition, by performing switching control of the changeover switch arranged before and after the double capacitor as described later, “0, 1, 0, −1, 0, 1, 0, −1. .. "and the sampling operation in the sampling unit 11 can be realized simultaneously, and the multiplication function, the sampling function, and the subtraction function between the input signal and the feedback signal in the ΔΣ modulator. These three functions can be realized by a single capacitor. That is, in FIG. 1, a small circuit having a function that combines the functions of the analog mixer 10 and the ΔΣ modulator 22 can be realized.

  FIG. 7 is a circuit diagram of a primary ΔΣ modulator 60 including a capacitor 67 that doubles as the capacitor 35 of the analog mixer 10 and the capacitor 57 of the switched capacitor circuit of the primary ΔΣ modulator 40. The primary ΔΣ modulator 60 outputs an input terminal IN to which an analog input signal A is input as an input signal of the primary ΔΣ modulator 60 and a 1-bit digital output signal as an output signal of the primary ΔΣ modulator 60. And an output terminal OUT. The first-order ΔΣ modulator 60 amplifies the switched capacitor to which the analog input signal A is input (capacitor 67 and changeover switch 61 and changeover switch 62 provided at both ends thereof) and the output signal of the switched capacitor. An integrator including an operational amplifier 63 and an integrating capacitor 64, a comparator 65 to which an output signal of the integrator is input, and an analog signal obtained by converting a digital signal output from the comparator 65 as a feedback signal. And a 1-bit DA converter 66 that supplies the connection terminals of the changeover switches 61 and 62.

  The integrator of the primary ΔΣ modulator 60 includes an operational amplifier 63 and an integration capacitor 64 inserted between the inverting input terminal and the output terminal of the operational amplifier 63. The non-inverting input terminal of the operational amplifier 63 is connected to the reference potential. The reference potential may be ground or a predetermined positive potential (for example, a voltage that is half the power supply voltage of the operational amplifier 63).

  The changeover switch 61 includes a terminal 61 a connected to the inverting input terminal of the operational amplifier 63, an input terminal IN (input terminal 61 b), and a terminal 61 c connected to the same reference potential as the non-inverting input terminal of the operational amplifier 63; The switching means selectively switches and connects the first electrode of the capacitor 67 to the four terminals 61d connected to the output side of the 1-bit DA converter 66. The changeover switch 62 includes a terminal 62 a connected to the inverting input terminal of the operational amplifier 63, a terminal 62 b connected to the same reference potential as the non-inverting input terminal of the operational amplifier 63, and the output of the 1-bit DA converter 66. Switching means for selectively switching and connecting the second electrode of the capacitor 67 to the three terminals of the terminal 62c connected to the side.

  FIG. 8 is a diagram for explaining the operation of the first-order ΔΣ modulator 60. The above-described sampling operation of the analog input signal is realized by the circuit connection state of the odd numbers (1), (3), (5), and (7) shown in FIG. 8, and the even numbers (2) and (4) shown in FIG. (6) The circuit connection state of (8) realizes the integration operation by taking the difference between the analog input signal and the output of the 1-bit DA converter 66 while realizing the above-described multiplication operation of the analog input signal. . Since (2), (4), and (6) in FIG. 8 are the same circuit connection, and (3) and (7) in FIG. 8 are the same circuit connection, the number of repeated switch operation states is 4.

8 (1) and 8 (5), the first electrode that is the input terminal IN side electrode of the capacitor 67 is connected to the reference potential, and the second electrode that is the electrode on the inverting input terminal side of the operational amplifier 63 of the capacitor 67 is connected. The reference potential is sampled by connecting to the reference potential. 8 (2) and (6), the sampling value sampled in FIGS. 8 (1) and (5) is obtained by connecting the first electrode to the terminal 61d and connecting the second electrode to the terminal 62a. And the output value of the 1-bit DA converter 66 are integrated. In the transition state (a) from (1) to (2) and the transition state (a) from (5) to (6), the multi-value signal A _SAMPLE is multiplied by “0” to perform integration. Equivalent to.

In FIG. 8C, the input potential of the analog input signal is sampled by connecting the first electrode to the input terminal IN and connecting the second electrode to the terminal 62b. In FIG. 8 (4), the sampling value sampled in FIG. 8 (3) and the 1-bit DA converter 66 are obtained by connecting the first electrode to the terminal 61d and the second electrode to 62a. Integrate the difference from the output value of. The transition state (b) from (3) to (4) corresponds to performing integration after multiplying the multilevel signal A _SAMPLE by “1”.

In FIG. 8 (7), the input potential of the analog input signal is sampled by connecting the first electrode to the input terminal IN and connecting the second electrode to the terminal 62b. 8 (8), the first electrode is connected to the terminal 61a and the second electrode is connected to 62c, so that the capacitor 67 is connected with the opposite polarity to that of FIG. 8 (4). The difference between the sampled value sampled in (7) and the output value of the 1-bit DA converter 66 is integrated. The transition state (c) from (7) to (8) corresponds to performing integration after multiplying the multilevel signal A _SAMPLE by “−1”.

Therefore, by repeating the switch operation of each switch in the order of the transition states (a), (b), (a), (c), (a), (b), (a), (c). The above-described sampling operation in FIG. 5 and the above-described multiplication of “0, 1, 0, −1, 0, 1, 0, −1. Can do. Each transition state transitions every time (1 / f _S ) (f _S = 4f _B ).

  As described above, the 1-bit digital data string output from the ΔΣ modulator 60 is filtered by the digital filter 23, and is input to the input signal A in the detection logic unit based on the output data of the digital filter 23. The value of the modulation signal C included can be detected by AD conversion.

Therefore, by adding the connection destination of the electrode of the switched capacitor of the primary ΔΣ modulator 40 shown in FIG. 6 and repeating the operation shown in FIG. 8, the primary ΔΣ modulator 60 shown in FIG. 10 functions and the function of the ΔΣ modulator 22 can be provided. Further, the low-pass ΔΣ modulator 60 in which the function of the analog mixer 10 is combined with the function of the ΔΣ modulator 22 is “a configuration in which a conventional analog mixer using a diode or a transformer is combined with a low-pass ΔΣ modulator”. Compared with “a configuration in which a bandpass ΔΣ modulator and a digital mixer are combined”, the circuit scale can be reduced. In particular, by setting the ratio of the sampling frequency f _S and the carrier frequency f _B of the carrier wave to 4: 1, an analog mixer can be configured with a simple operation of the switched capacitor circuit. As a result, the circuit scale can be greatly reduced, and ΔΣ modulation By combining it with an amplifier, the analog mixer and ΔΣ modulator can be integrated to reduce the circuit scale.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

For example, in order to simplify the circuit scale, the embodiment in which “f _S = 4f _B ” is set in detail, but the multiple is not limited to 4, and may be a multiple exceeding 2. In this case, although it is necessary to accurately create the above-described sample value by resistance voltage division or another arithmetic circuit, the same effect as that obtained when “f _S = 4f _B ” is obtained.

  Moreover, although the sine wave is illustrated as the reference signal represented by the periodic function, a square wave, a triangular wave, a sawtooth wave, or a similar waveform thereof may be used.

  Further, although the first-order ΔΣ modulator has been exemplified, the same effect can be obtained by performing the same control with the same configuration in the second-order or higher-order delta-sigma modulator.

  FIG. 9 is a diagram for explaining the operation of the secondary ΔΣ modulator 70. The second-order ΔΣ modulator 70 includes a switched capacitor (capacitor 77 and both ends thereof) to which the output signal of the operational amplifier 63 of the first-stage integrator is input in addition to the configuration of the first-order ΔΣ modulator 60 of FIGS. And an integrator having an operational amplifier 73 and an integrating capacitor 74 for amplifying the output signal of the switched capacitor and an output signal of the 1-bit DA converter 66. A multiplier 78 that multiplies an analog signal as a feedback signal by a predetermined multiplier and supplies it to the connection terminal of the changeover switch 71 is provided between the operational amplifier 63 and the comparator 65.

  The changeover switch 71 selectively switches and connects the first electrode of the capacitor 77 to two terminals, a terminal 71 a connected to the output terminal of the operational amplifier 63 and a terminal 71 b connected to the output side of the multiplier 78. It is the switching means to do. The changeover switch 72 has two terminals: a terminal 72a connected to the inverting input terminal of the operational amplifier 73 and a terminal 72b connected to the reference potential of the same potential as the non-inverting input terminals of the operational amplifiers 63 and 73. 77 is a switching means for selectively switching and connecting the 77 second electrodes.

Since the operation of the first-order ΔΣ modulator 70 is the same as that in FIG. 8 and the description thereof is simplified, the transition states (a), (b), (a), (c), (a), (b), and (a) in FIG. ) (C)... (C)... By repeating the switching operation of each switch, the sampling operation in the sampling unit 11 and “0, 1, 0, −1, 0, 1, 0, − 1 ”and the operation of the ΔΣ modulator can be realized. Each transition state transitions every time (1 / f _S ) (f _S = 4f _B ).

1 is a block diagram of a ΔΣ AD converter 20 that is an embodiment of the present invention. FIG. 4 is a waveform for explaining the operation of the analog mixer 10. 1 is a circuit diagram of an analog mixer 10. FIG. 4 is a diagram for explaining a switching operation of the analog mixer 10. FIG. 2 is a block diagram of a first-order ΔΣ modulator 40. FIG. 2 is a circuit diagram of a primary ΔΣ modulator 40. FIG. FIG. 3 is a circuit diagram of a primary ΔΣ modulator 60 including a capacitor 67 that doubles as a capacitor 35 of the analog mixer 10 and a capacitor 57 of a switched capacitor circuit of the primary ΔΣ modulator 40. FIG. 6 is a diagram for explaining the operation of the primary ΔΣ modulator 60. FIG. 6 is a diagram for explaining the operation of the secondary ΔΣ modulator 70.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Analog mixer 11 Sampling part 12 Sine wave generator 13 Multiplier 20 ΔΣ type AD converter 22 ΔΣ modulator 30, 31, 32, 51, 52, 61, 62, 71, 72 Changeover switch 35, 57, 67, 77 Capacitor 40, 60, 70 ΔΣ modulator

Claims (6)

Sampling means for generating a first multi-level signal by sampling a modulated wave transmitted with a modulation signal on a carrier wave at a sampling frequency that is a multiple of at least two times the carrier frequency of the carrier wave;
A second multilevel signal is generated by sequentially multiplying the amplitude value of the first multilevel signal by a sample value sampled at each sampling period of the sampling from a periodic function having the same frequency as the carrier frequency. And a multiplier.   The mixer according to claim 1, wherein the multiple is four.   The mixer according to claim 2, wherein the sample value is a sine wave displacement of 1, 0, −1, 0. The sampling means and the multiplying means are:
A capacitor having at least a first electrode connectable to an input end to which the modulated wave is input and a second electrode connectable to an output end to which the second multi-value signal is output. ,
A state in which the connection destination of the first electrode is the input end and the connection destination of the second electrode is the output end and a reference potential is a first state,
A state in which the connection destination of the first electrode is the output terminal and the connection destination of the second electrode is the reference potential is a second state,
When the state where the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the output end is the third state,
The first state, the second state, the first state, and the third state are switched in order of the sampling period in the order of the first state, the second state, the first state, and the third state. The mixer according to claim 2, wherein the switching operation in which the third state is one cycle is repeated. A capacitor having a first electrode connectable to at least an input end to which a modulated wave transmitted by transmitting a modulation signal on a carrier wave is input, and a second electrode connectable to at least an output end;
A state in which the connection destination of the first electrode is the input end and the connection destination of the second electrode is the output end and a reference potential is a first state,
A state in which the connection destination of the first electrode is the output terminal and the connection destination of the second electrode is the reference potential is a second state,
When the state where the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the output end is the third state,
The first state, the second state, the first state, and the third state are switched at a switching frequency that is four times the carrier frequency of the carrier wave in the order of the first state, the first state, and the third state. 2. A mixer that repeats the switching operation in which the state of 2, the first state, and the third state are one cycle. An integrator;
A capacitor having at least a first electrode connectable to an input terminal to which a modulated wave transmitted by transmitting a modulation signal on a carrier wave is input, and a second electrode connectable to an input section of the integrator;
A quantizer that outputs a signal obtained by comparing the integrator output signal obtained by integrating the voltage of the input unit of the integrator with a reference potential as a reference with a predetermined threshold;
A DA converter that converts the output signal of the quantizer into an analog signal and outputs the analog signal;
A state in which the connection destination of the first electrode is the reference potential and the connection destination of the second electrode is the reference potential is a first state,
A state in which the connection destination of the first electrode is the output side of the DA converter and the connection destination of the second electrode is an input unit of the integrator is a second state,
A state in which the connection destination of the first electrode is the input terminal and the connection destination of the second electrode is the reference potential is a third state,
A state in which the connection destination of the first electrode is an input unit of the integrator and the connection destination of the second electrode is an output side of the DA converter is a fourth state,
The state that switches from the first state to the second state is a first transition state,
The state that switches from the third state to the second state is a second transition state,
When the state that switches from the third state to the fourth state is the third transition state,
In the order of the first transition state, the second transition state, the first transition state, and the third transition state, the transition state is transited at a transition frequency that is four times the carrier frequency of the carrier wave, and the first transition state A ΔΣ modulator that repeats a transition operation with one transition state, the second transition state, the first transition state, and the third transition state as one cycle.

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