JP6632425B2 - Incremental delta-sigma modulator, modulation method, and incremental delta-sigma AD converter - Google Patents

Description

  The present invention relates to an incremental delta-sigma modulator, a modulation method, and an incremental delta-sigma AD converter.

2. Description of the Related Art Conventionally, in an AD converter that has a plurality of integrating circuits and converts an analog signal into a digital signal, an incremental delta-sigma modulator and an incremental delta that reset charges stored in the integrating circuit at predetermined time intervals A sigma AD converter has been known (for example, see Patent Document 1).
Patent Document 1 International Publication No. 2013/136676

  When a plurality of integrating circuits provided in such an incremental type delta-sigma modulator and an AD converter are configured by an amplifier such as an operational amplifier, an offset error of the amplifier may be superimposed on an output signal.

According to a first aspect of the present invention, there is provided an analog integrator for integrating an analog input signal, a modulation processing unit for outputting a modulation signal according to an integration result of the analog integrator, and a chopper pattern generation unit. An analog integrator for amplifying and outputting signals input to the positive side input terminal and the negative side input terminal; and a first input terminal of the analog integrator connected to the positive side input terminal. A second connection state in which the second input terminal of the analog integrator is connected to the negative input terminal or a second connection state in which the first input terminal is connected to the negative input terminal and the second input terminal is connected to the positive input terminal; or to a connected state, have a input changeover switch for switching in response to chopper pattern chopper pattern generating section generates, includes a plurality of cycles in the period in which the reset unit resets, chopper The pattern generator generates a chopper pattern in which the first connection state is continuous or a chopper pattern in which the second connection state is continuous, and an input to the analog integrator gives a modulation signal in each cycle of the first connection state in the cycle. When the difference between the total weight and the total weight given to the modulation signal by the input to the analog integrator in each cycle of the second connection state in the cycle is alternately switched between the first connection state and the second connection state Provided is an incremental delta-sigma modulator, a modulation method, and an incremental delta-sigma A / D converter that generate a first chopper pattern that is smaller than that of the first embodiment.

  The above summary of the present invention does not list all of the necessary features of the present invention. Further, a sub-combination of these feature groups can also be an invention.

FIG. 1 shows an example of a block diagram of an incremental type delta-sigma AD converter 100 according to the present embodiment. 1 shows a configuration example of an incremental type delta-sigma AD converter 100 according to the present embodiment. 2 shows a configuration example of a sample hold unit 110 and a DA conversion unit 150 according to the present embodiment. 3 shows an example of a signal waveform in each section of the incremental type delta-sigma AD converter 100 according to the present embodiment. 4 shows a configuration example of an analog integrator 130 that executes control using a chopper pattern according to the present embodiment. 7 shows an example of a chopper pattern generated by a chopper pattern generation section 370 according to the present embodiment. 7 shows an example of a total value of weights when the analog integrator 130 according to the present embodiment alternately repeats the first connection state and the second connection state. 7 shows a first example of a chopper pattern generated by a chopper pattern generation section 370 according to the present embodiment. 7 shows a second example of a chopper pattern generated by the chopper pattern generation section 370 according to the present embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all combinations of the features described in the embodiments are necessarily essential to the solution of the invention.

  FIG. 1 shows an example of a block diagram of an incremental type delta-sigma AD converter 100 according to the present embodiment. The incremental delta-sigma AD converter 100 converts an input analog signal into a digital signal while resetting the inside before outputting a digital signal. The incremental type delta sigma AD converter 100 includes a sample hold unit 110, an addition unit 120, an analog integration unit 130, a modulation processing unit 140, a DA conversion unit 150, a digital operation unit 160, a reset unit 170, Is provided.

  The sample and hold unit 110 samples the amplitude value of the input analog signal and holds the sampled value. The sample hold unit 110 repeats sampling and holding using a sampling clock signal synchronized with a clock signal or the like. Here, it is desirable that the frequency of the sampling clock signal be several times to several tens times or more as compared with the frequency of the input signal. In this case, the sample-and-hold unit 110 oversamples the input analog signal. Will do. Note that the sampling clock signal may be a frequency-divided signal of the clock signal, and in this case, the frequency division ratio may be about one-hundredth to one hundredth. Note that such a clock signal and a sampling clock signal are generated by a clock signal generator or the like provided inside or outside the incremental type delta-sigma AD converter 100, and are generated inside the incremental type delta-sigma AD converter 100. Is supplied to each part.

  FIG. 1 shows an example in which the analog signal AIN input to the sample-and-hold unit 110 is sampled and a held value AIN ′ is output. The sample hold unit 110 outputs the held value AIN ′ to the addition unit 120.

  The adding unit 120 adds the feedback signal of the incremental delta-sigma AD converter 100 to the output of the sample and hold unit 110. The adding unit 120 receives, for example, the differential signal from the sample and hold unit 110, and adds a feedback signal having a different sign to each of a positive signal and a negative signal of the differential signal. The adder 120 supplies the addition result to the analog integrator 130.

  Analog integrator 130 has an analog integrator and integrates an analog input signal. Analog integrator 130 may include a plurality of analog integrators. Analog integrator 130 supplies the integration result to modulation processor 140.

  Modulation processing section 140 outputs a modulation signal according to the integration result of analog integration section 130. Modulation processing section 140 has a quantizer that quantizes the integration result of the analog integration section, and outputs a bit stream corresponding to the integration result as modulation signal MOD0. The bit stream is a sequence (serial digital code) of a predetermined number of 1-bit data (digital code), and a digital value whose integrated value is proportional to or approximately equal to the amplitude value of the input signal Becomes

  That is, the incremental-type delta-sigma AD converter 100 converts an analog input signal into a digital value every fixed conversion cycle, and the modulation processing unit 140 outputs a serial digital code corresponding to the analog input signal every conversion cycle. I do. As described above, the analog signal is converted into a digital value for each of a plurality of samples synchronized with the clock signal, and the number of samples for one conversion cycle is defined as an oversampling ratio. That is, the number of digital codes included in the serial digital code is equal to the oversampling ratio.

  For example, when the oversampling ratio of the incremental type delta-sigma AD converter 100 is 60, the modulation processing unit 140 outputs a serial digital code including 60 digital codes every one conversion cycle. Modulation processing section 140 may output modulation signal MOD0 in synchronization with the clock signal. Modulation processing section 140 supplies modulated signal MOD0 to DA conversion section 150 and digital operation section 160.

  The DA converter 150 converts the output of the quantizer included in the modulation processor 140 from DA to D / A conversion, and feeds it back to the analog integrator 130. The DA converter 150 converts the bit stream that is a digital signal output from the modulation processor 140 into a corresponding analog signal, and supplies the converted analog signal to the adder 120 as a feedback signal. The DA converter 150 may convert the analog signal into an analog signal in synchronization with the clock signal. For example, the DA converter 150 converts the reference voltage into an analog signal corresponding to a positive or negative reference voltage according to the digital code so that the reference voltage is added to or subtracted from the output of the sample-and-hold unit 110 in the adder 120. .

  Digital operation section 160 receives the modulation signal from modulation processing section 140, integrates the modulation signal, and outputs a digital value. The digital operation unit 160 may include, for example, a digital integration unit, and the digital integration unit may integrate digital codes and calculate a corresponding digital value. Further, the digital calculation unit 160 may calculate a digital value by multiplying the integrated value by a predetermined coefficient. The digital calculation unit 160 may calculate a digital value in synchronization with a clock signal.

  The digital operation unit 160 has a low-pass filter as an example, and reduces quantization noise generated in the modulation processing unit 140. Further, the digital operation section 160 may include a decimation filter to reduce the sampling frequency. The digital operation unit 160 outputs the digital value of the operation result as the conversion result DOUT of the incremental type delta sigma AD converter 100.

  The reset unit 170 resets the integral value held by the analog integrator 130. The reset unit 170 may further reset the digital integration unit of the digital operation unit 160. The reset unit 170 may reset the analog integrator 130 and the digital calculator 160 every time the incremental delta-sigma AD converter 100 converts the digital value. As an example, the reset unit 170 supplies a reset signal to the analog integrator 130 and the digital operation unit 160 to reset the digital value in each conversion cycle.

  As described above, the incremental type delta-sigma AD converter 100 according to the present embodiment performs the reset of the analog integrator 130 and the digital calculator 160 by the reset unit 170 and the conversion of the input analog signal to a digital value. Repeat in synchronization with the clock signal. Note that the incremental type delta-sigma AD converter 100 may operate as a delta-sigma AD converter if there is no reset operation by the reset unit 170.

  In addition, in the incremental type delta-sigma AD converter 100 in FIG. 1, a portion excluding the digital operation unit 160 is an example of the incremental type delta-sigma modulator 10. Note that the incremental delta-sigma modulator 10 may be a part other than the sample-and-hold unit 110 and the digital operation unit 160. In the present embodiment, the incremental delta-sigma modulator 10 includes a sample-and-hold unit 110, an addition unit 120, an analog integration unit 130, a modulation processing unit 140, a DA conversion unit 150, and a reset unit 170.

  Next, a more detailed configuration example of the above-described incremental type delta-sigma AD converter 100 will be described. FIG. 2 shows a configuration example of the incremental type delta-sigma AD converter 100 according to the present embodiment. FIG. 2 shows an example in which the incremental type delta-sigma AD converter 100 converts an input analog signal AIN into a digital value DOUT. Note that an example is shown in which the analog signal AIN is input as a differential signal based on the positive signal AINP and the negative signal AINN.

  The incremental type delta-sigma AD converter 100 shown in FIG. 2 shows a more detailed configuration example of the analog integrator 130 shown in FIG. The incremental delta-sigma AD converter 100 shown in FIG. 2 further includes a first feedforward unit 250, a second feedforward unit 260, a third feedforward unit 270, and a fourth feedforward unit 280. The sample and hold unit 110 and the DA conversion unit 150 will be described later and will not be described here.

  Analog integrator 130 has a plurality of analog integrators and a plurality of switched capacitors. 2 illustrates an example in which the analog integrator 130 includes three analog integrators of a first analog integrator 210, a second analog integrator 220, and a third analog integrator 230. Also, an example is shown in which the analog integrator 130 has two switched capacitors, a first switched capacitor 240 and a second switched capacitor 245.

  FIG. 2 shows an example in which three analog integrators each have two input terminals and two output terminals, input a differential signal, and output a differential signal. Note that one of the two input terminals of the analog integrator is a first input terminal, and the other is a second input terminal. One of the two output terminals of the analog integrator is a first output terminal, and the other is a second output terminal.

The analog integrator includes an analog amplifier, a feedback capacitor, and a reset switch, respectively. FIG. 2 shows an example in which the first analog integrator 210 includes a first analog amplifier 212, a positive feedback capacitor C _i1p , a negative feedback capacitor C _i1n , a positive reset switch 214, and a negative reset switch 216. The second analog integrator 220 includes a second analog amplifier 222, a positive feedback capacitor C _i2p , a negative feedback capacitor C _i2n , a positive reset switch 224, and a negative reset switch 226. An example in which the integrator 230 includes a third analog amplifier 232, a positive feedback capacitor C _i3p , a negative feedback capacitor C _i3n , a positive reset switch 234, and a negative reset switch 236 is shown.

  The analog amplifier amplifies and outputs signals input to the positive input terminal and the negative input terminal. The analog amplifier is, for example, a differential input type amplifier circuit. The analog amplifier may have a single-ended output, and may have a differential output instead. The analog amplifier is, for example, an OP amplifier. FIG. 2 shows an example in which three analog integrators of a first analog amplifier 212, a second analog amplifier 222, and a third analog amplifier 232 include differential input and differential output analog amplifiers, respectively. In FIG. 2, the positive input terminal of the analog amplifier is connected to the first input terminal of the analog integrator, and the negative input terminal is connected to the second input terminal.

The feedback capacitor sequentially accumulates the charge held by the sample and hold unit 110. The feedback capacitor sequentially accumulates electric charges from the previous stage to the subsequent stage, for example, for each sampling. As an example, the positive charge stored in the feedback capacitor C _i1p in the first clock is accumulated on the positive side feedback capacitor C _i2p in the next second clock, it accumulates the positive side feedback capacitor C _I3P in the next third clock Is done. Similarly, the negative charge stored in the feedback capacitor C _I1n in the first clock is accumulated on the negative side feedback capacitor C _i2n in the next second clock, accumulate the negative side feedback capacitor C _I3n in the next third clock Is done.

  The reset switch discharges the charge stored in the feedback capacitor and resets the analog integrator according to an instruction from the reset unit 170. The reset switch connects the terminals of the feedback capacitor according to a reset signal supplied from the reset unit 170, for example, and discharges the accumulated charge. In the example of FIG. 2, the positive reset switch 214, the negative reset switch 216, the positive reset switch 224, the negative reset switch 226, the positive reset switch 234, and the negative reset are performed in response to an instruction from the reset unit 170. The switch 236 is turned on, resetting the first analog amplifier 212, the second analog amplifier 222, and the third analog amplifier 232.

  The switched capacitor is provided between the analog integrators and transmits the electric charge accumulated in the analog integrator connected in the preceding stage to the analog integrator connected in the subsequent stage. The switched capacitor includes a charge / discharge capacitor and a switch provided at a stage preceding and succeeding the capacitor. The preceding switch switches the connection destination of one terminal of the capacitor to one of the preceding circuit of the switched capacitor and the reference potential. The latter switch switches the connection destination of the other terminal of the capacitor to one of the latter circuit of the switched capacitor and the reference potential. Here, the reference potential may be a predetermined potential, for example, 0V.

  For example, in one clock, the switched capacitor has one terminal of the capacitor connected to the analog integrator in the previous stage, and the other terminal of the capacitor connected to the reference potential, so that the analog integrator connected in the previous stage is connected. The output charge is charged by the capacitor. In this case, at the next clock, the switched capacitor connects the one terminal of the capacitor to the reference potential and connects the other terminal of the capacitor to the analog integrator at the subsequent stage, so that the charge charged by the capacitor is connected to the subsequent stage. Discharges to the analog integrator.

FIG. 2 shows that a first switched capacitor 240 is connected between a first analog integrator 210 and a second analog integrator 220, and a first-stage switch 242 and a second-stage switch 244 are used to connect a first-stage positive-side feedback capacitor C _i1p to the first-stage positive-side feedback capacitor C _i1p . the accumulated charge, the capacitor C _s2p is charged, an example of transmitting and discharged to the subsequent positive feedback capacitor C _i2p. In this case, similarly, in the first switched capacitor 240, the capacitor _Cs2n charges the electric charge accumulated in the negative feedback capacitor _Ci1n in the preceding stage, and discharges and transmits it to the negative feedback capacitor _{Ci2n in the subsequent} stage. I do.

FIG. 2 shows that a second switched capacitor 245 is connected between a second analog integrator 220 and a third analog integrator 230, and a front-stage positive feedback capacitor C the charge accumulated in the _i2p, capacitor C _S3P is charged, an example of transmitting and discharged to the subsequent positive feedback capacitor C _I3P. In this case, similarly, the second switched capacitor 245 causes the capacitor C _s3n to charge the electric charge accumulated in the previous-stage negative-side feedback capacitor C _i2n , and discharges and transmits the electric charge to the _subsequent- stage negative-side feedback capacitor C _i3n . I do.

  As described above, the analog integrator 130 includes a plurality of analog integrators connected in series, and transfers the charge held by the sample-and-hold unit 110 from the preceding analog integrator to the subsequent analog integrator at each clock. Store and transmit sequentially. Analog integrator 130 outputs the charge accumulated in the feedback capacitor of the last analog integrator to modulation processor 140. For example, since the analog integrator 130 shown in FIG. 2 has three stages of analog integrators, the electric charge accumulated in the first analog integrator 210 at the first clock is transferred to the third analog integrator 230 at the third clock. The signal is transmitted and output to modulation processing section 140.

  Although FIG. 2 illustrates an example in which the analog integrator 130 has three analog integrators, the analog integrator 130 may alternatively have two or four or more analog integrators. Good. In this case, one or three or more switched capacitors may be provided in the analog integrator 130 according to the number of analog integrators.

The first feedforward unit 250 includes one or more switched capacitors, and transmits the analog signals AINP and AINN input to the incremental type delta-sigma AD converter 100 to the modulation processing unit 140. FIG. 2 illustrates an example in which the first feedforward unit 250 includes a plurality of switched capacitors. The first feedforward unit 250 may include the same number of switched capacitors as the oversampling ratio. One switched capacitor included in the first feedforward unit 250 includes, for example, a first FF switch 252, a capacitor C _0ffpj , and a capacitor C _0ffnj . Note that j is a natural number from 1 to the number of oversampling ratios (for example, 60).

The first FF switch 252 switches one terminal of the capacitor _C0ffpj to one of an input terminal to which the analog signal AINP is input and a reference potential. _Further, the other terminal of the capacitor C _0ffpj is connected to the modulation processing unit 140. One terminal of the capacitor C _0ffpj is connected to the input terminal at the first timing, and charges the analog input signal. One terminal of the capacitor C _0ffpj is connected to the reference potential at the j-th timing from the first timing, and discharges the charged analog input signal to the modulation processing unit 140.

Similarly, the first FF switch 252 switches one terminal of the capacitor C _0ffnj to one of the input terminal to which the analog signal AINN is input and the reference potential. One terminal of the capacitor _C0ffnj is connected to the input terminal at the first timing, and charges the analog input signal. One terminal of the capacitor C _0ffnj is connected to the reference potential at the j-th timing from the first timing, and discharges the charged analog input signal to the modulation processing unit 140. That is, the plurality of switched capacitors respectively charge the analog input signal in the first clock, and sequentially discharge the charged analog input signal to the modulation processing unit 140 according to the corresponding clock signal after the first clock.

Second feedforward section 260 includes a switched capacitor, and transmits signals (for example, INT10P and INT10N) output from first analog integrator 210 to modulation processing section 140. Second feedforward section 260 may include a switched capacitor. The second feedforward unit 260 includes, for example, a second FF switch 262, a capacitor _C1ffp , and a capacitor _C1ffn .

The second FF switch 262 switches one terminal of the positive-side capacitor C _1ffp to one of a first output terminal from which the first analog integrator 210 outputs the signal INT10P and a reference potential. _Further, the other terminal of the capacitor C _1ffp is connected to the modulation processing unit 140. For example, in the first clock, one terminal of the capacitor C _1ffp is connected to the output terminal, and charges the signal INT10P. Then, in the second clock, one terminal of the capacitor C _1ffp is connected to the reference potential, and the charged signal is discharged to the modulation processing unit 140.

Similarly, the second FF switch 262 switches one terminal of the negative-side capacitor C _1ffn to one of the second output terminal from which the first analog integrator 210 outputs the signal INT10N and the reference potential. The other terminal of the capacitor C _1ffn is connected to the modulation processing unit 140. For example, in the first clock, one terminal of the capacitor C _1ffn is connected to the output terminal, and charges the signal INT10N. Then, one terminal of the capacitor C _1ffn is connected to the reference potential in the second clock, and the charged signal is discharged to the modulation processing unit 140.

The third feedforward unit 270 includes a switched capacitor, and transmits signals (for example, INT20P and INT20N) output from the second analog integrator 220 to the modulation processing unit 140. Third feedforward unit 270 may include a switched capacitor. The third feedforward unit 270 includes, for example, a third _FF switch 272, a capacitor _C2ffp , and a capacitor _C2ffn .

The third _FF switch 272 switches one terminal of the capacitor C _2ffp to one of a first output terminal from which the second analog integrator 220 outputs the signal INT20P and a reference potential. The other terminal of the capacitor _C2ffp is connected to the modulation processing unit 140. For example, in the first clock, one terminal of the capacitor _C2ffp is connected to the output terminal, and charges the signal INT20P. Then, in the second clock, one terminal of the capacitor C _2ffp is connected to the reference potential, and the charged signal is discharged to the modulation processing unit 140.

Similarly, the _{third FF} switch 272 switches one terminal of the capacitor C _2ffn to one of the second output terminal from which the second analog integrator 220 outputs the signal INT20N and the reference potential. For example, in the first clock, one terminal of the capacitor _C2ffn is connected to the output terminal, and charges the signal INT20N. Then, in the second clock, one terminal of the capacitor C _2ffn is connected to the reference potential, and the charged signal is discharged to the modulation processing unit 140.

The fourth feedforward unit 280 includes a switched capacitor, and transmits signals (for example, INT30P and INT30N) output from the third analog integrator 230 to the modulation processing unit 140. The fourth feedforward unit 280 may include a switched capacitor. The fourth feedforward unit 280 includes, for example, a fourth _FF switch 282, a capacitor _C3ffp , and a capacitor _C3ffn .

The fourth _FF switch 282 switches one terminal of the capacitor C _3ffp to one of the first output terminal from which the third analog integrator 230 outputs the signal INT30P and the reference potential. The other terminal of the capacitor C _3ffp is connected to the modulation processing unit 140. For example, in the first clock, one terminal of the capacitor C _3ffp is connected to the output terminal, and charges the signal INT30P. One terminal of the capacitor C _3ffp is connected to the reference potential in the second clock, and the charged signal is discharged to the modulation processing unit 140.

Similarly, the _{fourth FF} switch 282 switches one terminal of the capacitor C _3ffn to one of the second output terminal from which the third analog integrator 230 outputs the signal INT30N and the reference potential. For example, in the first clock, one terminal of the capacitor C _3ffn is connected to the output terminal, and charges the signal INT30N. Then, in the second clock, one terminal of the capacitor C _3ffn is connected to the reference potential, and the charged signal is discharged to the modulation processing unit 140.

  Thus, fourth feedforward section 280 transmits the output of analog integrator 130 to modulation processing section 140. In addition, the first feedforward section 250, the second feedforward section 260, and the third feedforward section 270 each include a signal input to the analog integrator 130 and a signal output by the analog integrator of the analog integrator 130. Is transmitted to the modulation processing unit 140 as a feedforward signal. With such a feedforward signal, the digital code output from the modulation processing unit 140 for each clock can be made to reflect the analog input signal at a higher speed.

  The incremental delta-sigma AD converter 100 according to the present embodiment is not limited to such a feedforward operation. That is, the first feedforward section 250, the second feedforward section 260, and the third feedforward section 270 may be omitted. Next, the sample hold unit 110 and the DA conversion unit 150 will be described.

  FIG. 3 shows a configuration example of the sample hold unit 110 and the DA conversion unit 150 according to the present embodiment. The sample hold unit 110 and the DA converter 150 shown in FIG. 2 show a more detailed configuration example of the sample hold unit 110 and the DA converter 150 shown in FIGS.

The sample and hold unit 110 includes one or a plurality of switched capacitors, and transmits the analog signals AINP and AINN input to the incremental type delta-sigma AD converter 100 to the analog integrator 130. FIG. 3 illustrates an example in which the sample and hold unit 110 includes a plurality of switched capacitors. The sample and hold unit 110 may include the same number of switched capacitors as the oversampling ratio. The plurality of switched capacitors each include a capacitor C _s1pj , a capacitor C _s1nj, and a changeover switch at a stage _before and after each capacitor. Note that j is a natural number from 1 to m, and m is the number of oversampling ratios (for example, 60).

The switch preceding the capacitor C _s1pj switches one terminal of the capacitor C _s1pj to one of an input terminal to which the analog signal AINP is input and a reference potential. The switch at the _subsequent stage of the capacitor C _s1pj switches the other terminal of the capacitor C _s1pj to one of the reference potential and the adding unit 120.

Each of the capacitors _C s1pj, (as an example, the signal phi _t is high potential) the first timing in, is connected to one terminal input AINP, and the other terminal is connected to a reference potential, charges the analog input signal I do. The j-th capacitor C _s1pj has one terminal connected to the reference potential and the other terminal connected to the adder 120 at a timing shifted from the first timing to the j-th timing (for example, when the signal φ _ij has a high potential). And sequentially discharges the charged analog input signal to the analog integrator 130.

Similarly, a switch preceding the capacitor _Cs1nj switches one terminal of the capacitor _Cs1nj to one of an input terminal to which the analog signal AINN is input and a reference potential. The switch at the _subsequent stage of the capacitor C _s1nj switches the other terminal of the capacitor C _s1nj to one of the reference potential and the adding unit 120.

Each of the capacitors C _S1nj, first timing (signal phi _t is high potential) in, is connected to one terminal input terminal AINN, the other terminal is connected to a reference potential, to charge the analog input signal. The j-th capacitor C _s1nj has one terminal connected to the reference potential and the other terminal connected to the addition unit 120 at the j-th timing shifted from the first timing (the signal φ _ij is at the high potential). Then, the charged analog input signals are sequentially discharged to the analog integrator 130.

  That is, the plurality of switched capacitors respectively charge the analog input signal in the first clock, and sequentially discharge the charged analog input signal to the analog integrator 130 according to the corresponding clock signal after the first clock. Accordingly, the sample-and-hold unit 110 can sequentially supply substantially the same analog value sampled by the plurality of switched capacitors in the first clock to the analog integrator 130 after the first clock. That is, even if the analog signal changes at high speed, the sample-and-hold unit 110 can hold the value of one timing and convert it to a digital value.

  Alternatively, the sample and hold unit 110 may include one switched capacitor and sample an analog signal for each clock. In this case, when fluctuations such as noise are superimposed on the analog signal, sampling is performed at each timing synchronized with the clock signal, so that fluctuations due to the noise can be averaged and reduced. Note that the number of switched capacitors included in the sample and hold unit 110 may be substantially the same as the number of switched capacitors included in the first feedforward unit 250.

The DA converter 150 includes a first reference voltage REFP, a second reference voltage REFN, a capacitor C _fbp , a capacitor C _fbn , a first switch 152, a second switch 154, and a third switch 156. And The first reference voltage REFP and the second reference voltage REFN have voltage values that have substantially the same absolute value and output voltages whose polarities are opposite to each other. As an example, the first reference voltage REFP outputs a positive voltage, and the second reference voltage REFN outputs a negative voltage.

The first switch unit 152 switches one terminal of the capacitor C _fbp to one of the first reference voltage REFP and the reference potential. In addition, the first switch unit 152 switches one terminal of the capacitor C _fbn to one of the second reference voltage REFN and the reference potential. The first switch unit 152 connects one terminal of the capacitor C _fbp to the first reference voltage REFP and connects one terminal of the capacitor C _fbn to the second reference voltage REFN, for example, at the timing when the signal φ _s is at the high potential. Connecting. In addition, the first switch unit 152 _connects one terminal of the capacitor C _fbp and one terminal of the capacitor C _fbn to the reference potential at the timing when the signal φ _i is at the high potential.

The second switch unit 154 performs switching as to whether or not the other terminal of the capacitor _{C fbp} and capacitor _{C fbn,} connected to a reference potential. The second switch unit 154 _connects the other terminal of the capacitor C _fbp and the other terminal of the capacitor C _fbn to the reference potential at the timing when the signal φ _s is at the high potential, and at the timing when the signal φ _i is at the high potential, for example, Disconnect the electrical connection between the terminal and the reference potential. The first switch unit 152 and the second switch 154, a capacitor C _fbp and capacitor C _fbn, at the timing of the signal phi _s high potential, is connected corresponding reference voltage and, respectively, according to the capacity of the reference voltage and the capacitor Charge is charged.

The third switch unit 156 switches whether to connect the other terminals of the capacitor C _fbp and the capacitor C _fbn to the adding unit 120. The third switch unit 156 _connects the other terminal of the capacitor C _fbp and the other terminal of the capacitor C _fbn to the addition unit 120 at the timing when the signal φ _i is at the high potential, for example, at the timing when the signal φ _s is at the high potential. And the electrical connection of the adder 120 is disconnected. Accordingly, the third switch unit 156 can supply the charge charged in the capacitor C _fbp and the capacitor C _fbn to the adding unit 120.

The third switch unit 156 switches the connection destination of the other terminal of the capacitor C _{fbp and} the other terminal of the capacitor C _fbn according to the modulation signal MOD0 supplied from the modulation processing unit 140. Here, the adder unit 120 to which the capacitor C _fbp and the capacitor C _fbn are connected corresponds to the differential signal received from the sample-and-hold unit 110, and respectively adds a feedback signal to the positive signal and the negative signal of the differential signal. Is transmitted.

For example, when the digital code of the modulation signal MOD0 is “0”, the third switch unit 156 adds a charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the positive signal of the differential signal. The connection is switched so that the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn is added to the negative signal of the differential signal. As an example, the third switch unit 156 sets the signal φ _ip to a high potential in response to the digital code “0”, _connects the other terminal of the capacitor C _fbp to the transmission line of the positive signal at the timing, The other terminal of C _fbn is connected to the transmission line of the negative signal.

Further, for example, when the digital code of the modulation signal MOD0 is “1”, the third switch unit 156 _converts a charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp into a negative signal of the differential signal. The connection is switched so that the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn is added to the positive signal of the differential signal. As an example, the third switch unit 156 sets the signal φ _in to a high potential _in response to the digital code “1”, and _connects the other terminal of the capacitor C _fbp to the transmission line of the negative signal at the timing. The other terminal of _Cfbn is connected to the transmission line of the positive signal.

  As described above, the DA conversion unit 150 adds the analog signal corresponding to the positive reference voltage as the feedback signal in response to the digital signal “0” obtained by the modulation processing unit 140 quantizing the integration result of the analog integration unit 130. 120, and the feedback signal is added to the differential signal. Further, the DA conversion unit 150 sends the analog signal corresponding to the negative reference voltage as a feedback signal to the addition unit 120 according to the digital signal “1” obtained by the modulation processing unit 140 quantizing the integration result of the analog integration unit 130. And outputs the feedback signal to the differential signal.

  That is, the incremental type delta-sigma AD converter 100 outputs a serial digital code while performing feedback control for adding or subtracting a reference voltage to or from the analog signal according to the quantization result of the integration result of the input analog signal. The operation of each unit according to the clock signal of the incremental type delta-sigma AD converter 100 will be described below.

  FIG. 4 shows an example of a signal waveform in each section of the incremental type delta-sigma AD converter 100 according to the present embodiment. The horizontal axis in FIG. 4 indicates time, and the vertical axis indicates a peak value (as an example, a voltage value). FIG. 4 shows “tracking” as a tracking phase in a time domain in which an input analog signal is sampled and held. Further, a time domain in which the held analog signal is converted into a digital signal is referred to as “conversion” as a conversion phase. Note that an example of an input analog signal is shown as a signal AIN (= AINP-AINN).

  The reset unit 170 resets the analog integrator 130 and the digital calculator 160 in the tracking phase. An example of the reset signal output by the reset unit 170 is shown as a signal φr in FIG. The signal φr has a high potential in the tracking phase.

  In the tracking phase, the sample hold unit 110 samples the analog signals AINP and AINN. That is, the plurality of switched capacitors of the sample-and-hold unit 110 charge the analog input signal according to the signal φt that becomes the high potential in the tracking phase of FIG. Note that the plurality of switched capacitors included in the first feedforward unit 250 may also charge the analog input signal according to the signal φt.

In the conversion phase, the sample-and-hold unit 110 sequentially discharges the charged analog input signal to the analog integrator 130. That is, the capacitor _{C S1pj} and capacitor _{C S1nj} included in the sample hold unit 110, the number of the conversion phase, different sequential signal .PHI.ij (j serving as a high-potential timing from 1 a natural number of m mutually, m is the oversampling ratio ), The charged analog input signals are sequentially discharged. Note that the plurality of switched capacitors included in the first feedforward unit 250 may also sequentially discharge the analog input signal according to the signal φt.

  Accordingly, analog integrator 130 integrates the analog input signals sequentially discharged from sample and hold unit 110, and modulation processor 140 quantizes the integration result and outputs the result as modulation signal MOD0. FIG. 4 shows an example of a modulation signal output from the modulation processing unit 140 as a signal MOD0.

FIG. 4 shows an example of the signals φs and φi that control the first switch unit 152 and the second switch unit 154 of the DA converter 150. The first switch unit 152 and the second switch unit 154 are controlled by the signal φs and the signal φi, so that the capacitors C _fbp and C _fbn are charged with electric charges corresponding to the corresponding reference voltages. FIG. 4 shows an example of the first reference voltage REFP and the second reference voltage REFN.

  FIG. 4 shows an example of a signal φip and a signal φin that control the third switch unit 156 of the DA converter 150 according to the signal MOD0. The signal φip is a signal having a high potential in response to the bit value of the signal MOD0 being 0, and the signal φin is a signal having a low potential in response to the bit value of the signal MOD0 being 1. is there. The third switch unit 156 is controlled by the signal φip and the signal φin, so that the adding unit 120 can add the feedback signal to the differential signal.

  When the number of stages of the analog integrator of the analog integrator 130 is L, the first (L-1) output of the conversion phase is a data transmission delay, and the analog integrator 130 sets the integration result to 0. . The analog input signal to the analog integrator 130 is sequentially input from the m switched capacitors according to the 1st to mth clock signals, and is output for the (m + 1) to (m + L-1) th clocks. May be undefined or 0 because it has no effect on.

  In the conversion phase, when all (that is, m) switched capacitors of the sample and hold unit 110 have completed discharging and the modulation processing unit 140 sequentially outputs m digital codes, the incremental type delta-sigma AD converter 100 May end one conversion cycle. That is, the incremental type delta-sigma AD converter 100 shifts from the conversion phase to the tracking phase, and the reset unit 170 resets the analog integrator 130 and the digital operation unit 160.

  As described above, the incremental delta-sigma AD converter 100 converts the analog input signal into a digital signal by repeating the conversion cycle including the tracking phase and the conversion phase. Unlike the delta-sigma AD converter, the incremental type delta-sigma AD converter 100 discharges and resets the electric charge accumulated in the analog integrator 130 in the tracking phase. This allows the digital value converted in one conversion cycle to be a value obtained by converting the value of the analog input signal more accurately without being affected by the charge accumulated in a cycle different from the one conversion cycle. Can be.

  In addition, since the incremental type delta-sigma AD converter 100 resets the analog integrator 130 every conversion cycle, in the conversion phase, the charge stored earlier is compared with the charge stored later, and Will have a greater effect on the digital signal.

  For example, as shown in FIG. 2, the analog integrator 130 of L = 3 sequentially accumulates the analog input signal input first after entering the conversion phase into three integrators, and outputs a third clock. Is output as an integration result in synchronization with. Since the first analog input signal is stored in the third analog integrator 230, it is included in all of the integration results output from the third clock in synchronization with the (m + 2) th clock from the third clock. Will have an effect. On the other hand, the m-th input analog input signal is only included in the integration result output by the analog integrator 130 in synchronization with the (m + 2) -th clock.

Therefore, the weight (weight or contribution) of the analog input signal input to the analog integrator 130 with respect to the serial digital code output from the modulation processor 140 differs depending on the input order. Here, assuming that the value of the analog input signal is normalized to be 1, the weight of the i-th input analog input signal will be integrated (L-1) times for the remaining (mi + 1) times. , Can be calculated as follows:

Note that the analog input signal is sequentially input in synchronization with the first to m-th clock signals after the conversion phase, and each is integrated in the (L-1) order, so that the overall weight is calculated as in the following equation. it can.

Therefore, when the weight of the i-th input analog input signal is normalized so that the gain of the transfer function of the analog input signal becomes 1, the following equation is obtained.

By rearranging equation (3), the following equation is obtained as the weight of the i-th input analog input signal.

  The above-described incremental delta-sigma AD converter 100 receives the analog input signal as a differential signal, and the analog integrator 130 integrates the differential signal. Therefore, the offset error is added to the positive signal and the negative signal of the differential signal. Is included, the offset error is accumulated, and an error occurs in the serial digital code. In such a case, a chopper circuit may be provided on the transmission line of the differential signal, and the differential signal may be chopped to reduce the offset error.

  For example, even if the positive signal of the differential signal includes a + V offset signal, the negative signal can include the + V offset signal by switching the positive transmission line to the negative transmission line by chopping. Thereby, the difference signal between the positive side signal and the negative side signal cancels out the + V offset signal, and ideally the offset error becomes zero. The reduction of the offset error due to such chopping can be achieved when the weight of the analog input signal with respect to the serial digital code of the conversion result is substantially the same, irrespective of the input order of the analog input signal, as in a delta-sigma AD converter. It is valid.

  However, in the incremental type delta-sigma AD converter 100, as described above, the weight of the analog input signal with respect to the serial digital code of the conversion result varies depending on the input order of the analog input signal. Therefore, for example, the weight of the analog input signal is different between the positive signal before chopping and the negative signal after chopping, so that these differential signals may not be able to cancel the offset error.

For example, a value obtained by subtracting the even-numbered sum of the weights from the odd-numbered sum of the weights from the equation (4) is calculated by the following equation. Note that Weight _{Δsum_even in} Expression (5) is a calculation result when L> 2 and m is an even number, and Weight _{Δsum_odd in} Expression (6) is a calculation result when L> 2 and m is an odd number. is there.

Also, the calculation result when L = 2 and m is an even number is shown in Expression (7), and the calculation result when L = 2 and m is an odd number is shown in Expression (8).

  From the equations (7) and (8), for example, when L = 2 and m = 60, even if chopping is performed, the incremental-type delta-sigma AD converter 100 outputs the positive signal of the differential signal and It can be seen that at least an offset error of about 1/60 of the offset error when the chopping operation included in the negative signal is not performed is generated. Thus, the incremental delta-sigma AD converter 100 according to the present embodiment executes chopping according to the chopper pattern to reduce such offset errors. Next, the analog integrator 130 that performs such control using the chopper pattern will be described.

FIG. 5 shows a configuration example of the analog integrator 130 that executes control using the chopper pattern according to the present embodiment. In the analog integrator 130 shown in FIG. 5, the same reference numerals are given to the same operations as those of the analog integrator 130 according to the present embodiment shown in FIG. 2, and the description will be omitted. In the analog integrator 130 according to the present embodiment, an example will be described in which the first analog integrator 210 has an offset error of V ₀₁ , the second analog integrator 220 has an offset error of V ₀₂ , and the third analog integrator 230 has an offset error of V ₀₃ .

  The analog integration section 130 according to the present embodiment further includes an input changeover switch, an output changeover switch, and a chopper pattern generation section 370. In FIG. 5, the first analog integrator 210 has a first input switch 310 and a first output switch 320, and the second analog integrator 220 has a second input switch 330 and a second output switch 340. Then, an example is shown in which the third analog integrator 230 has a third input changeover switch 350 and a third output changeover switch 360.

  Here, the first input terminal of the first analog integrator 210 to which the positive signal of the differential signal is input is connected to the positive input terminal of the first analog amplifier 212, and the negative signal of the differential signal is input. A state in which the second input terminal of the first analog integrator 210 is connected to the negative input terminal of the first analog amplifier 212 is referred to as a first connection state. The first input terminal of the first analog integrator 210 is connected to the negative input terminal of the first analog amplifier 212, and the second input terminal of the first analog integrator 210 is connected to the positive input terminal of the first analog amplifier 212. The state connected to the input terminal is referred to as a second connection state. The first input changeover switch 310 switches between the first connection state and the second connection state according to a chopper pattern.

  Similarly, the first input terminal of the second analog integrator 220 is connected to the positive input terminal of the second analog amplifier 222, and the second input terminal of the second analog integrator 220 is connected to the negative input terminal of the second analog amplifier 222. The state connected to the side input terminal is referred to as a first connection state. The first input terminal of the second analog integrator 220 is connected to the negative input terminal of the second analog amplifier 222, and the second input terminal of the second analog integrator 220 is connected to the positive input terminal of the second analog amplifier 222. The state connected to the input terminal is referred to as a second connection state. The second input changeover switch 330 switches between the first connection state and the second connection state according to the chopper pattern.

  Similarly, the third input switch 350 switches the third analog integrator 230 between the first connection state and the second connection state according to the chopper pattern. FIG. 5 shows an example in which the first analog integrator 210, the second analog integrator 220, and the third analog integrator 230 are in the first connection state. The first analog amplifier 212, the second analog amplifier 222, and the third analog amplifier 232 amplify signals input to the positive input terminal and the negative input terminal, and amplify the amplified signals to the positive output terminal and the negative output terminal. Output from each output terminal.

  Each of the output changeover switches switches the connection destination of the output of the analog amplifier between the first connection state and the second connection state. The first output switch 320 connects the positive output terminal of the first analog amplifier 212 to the first output terminal of the first analog integrator 210 and connects the negative output terminal of the first analog amplifier 212 in the first connection state. It is connected to the second output terminal of the first analog integrator 210. In the second connection state, the first output switch 320 connects the positive output terminal to the second output terminal and connects the negative output terminal to the first output terminal.

  The first input changeover switch 310 and the first output changeover switch 320 have a plurality of switches, and switch the connection state according to a chopper pattern including a signal instructing switching of the plurality of switches. In FIG. 5, the first input changeover switch 310 has a switch 312, a switch 314, a switch 316, and a switch 318, and the first output changeover switch 320 has a switch 322, a switch 324, a switch 326, and a switch 328. Here is an example. For example, the first input switch 310 and the first output switch 320 switch the connection state according to a chopper pattern including two signals, a signal φp1 and a signal φn1.

  FIG. 6 shows an example of a chopper pattern generated by the chopper pattern generator 370 according to the present embodiment. FIG. 6 shows an example of a chopper pattern that alternately switches between the first connection state and the second connection state. That is, the switch 312, the switch 314, the switch 326, and the switch 328 are turned on according to the timing of the high potential of the signal φp1, and are turned off according to the timing of the low potential. Further, the switches 316, 318, 322, and 324 are turned on in response to the timing of the signal φn1 at the high potential and turned off in response to the timing of the low potential.

  Similarly, the second output changeover switch 340 connects the positive output terminal of the second analog amplifier 222 to the first output terminal of the second analog integrator 220 in the first connection state, and connects the negative output of the second analog amplifier 222 to the second output terminal. The terminal is connected to the second output terminal of the second analog integrator 220. In the second connection state, the second output switch 340 connects the positive output terminal to the second output terminal and connects the negative output terminal to the first output terminal.

  Similarly, the third output changeover switch 360 connects the positive output terminal of the third analog amplifier 232 to the first output terminal of the third analog integrator 230 in the first connection state, and outputs the negative output of the third analog amplifier 232. The terminal is connected to the second output terminal of the third analog integrator 230. In the second connection state, the third output switch 360 connects the positive output terminal to the second output terminal and connects the negative output terminal to the first output terminal.

  Chopper pattern generation section 370 generates a chopper pattern that does not include switching between the first connection state and the second connection state in some continuous cycles. Chopper pattern generation section 370 generates a chopper pattern of a switching operation different from the chopping operation of alternately switching the first connection state and the second connection state. That is, the chopper pattern generation unit 370 generates a chopper pattern that reduces an error of a modulation signal caused by an offset error of the analog amplifier as compared with a case where the first connection state and the second connection state are alternately switched.

  Chopper pattern generation section 370 may include a storage section for storing a predetermined chopper pattern. Instead of this, the chopper pattern generation section 370 may include an arithmetic circuit that outputs a predetermined chopper pattern by an operation or the like. The chopper pattern generating section 370 converts the chopper pattern into a first input switch 310, a first output switch 320, a second input switch 330, a second output switch 340, a third input switch 350, and a third output. It may be supplied to the changeover switch 360.

  Note that the reset unit 170 resets the integrated value held by the analog integrator 130 for each predetermined cycle (ie, conversion phase). Here, the cycle reset by the reset unit 170 includes a plurality of cycles. Then, in each cycle of the first connection state in the cycle, the chopper pattern generation unit 370 calculates the sum of the weight given to the modulation signal MOD0 by the input to the analog integrator and the analog signal in each cycle of the second connection state in the cycle. A chopper pattern is generated which makes the difference between the input to the integrator and the total weight given to the modulation signal MOD0 smaller than when the first connection state and the second connection state are alternately switched.

That is, the chopper pattern generation unit 370 compares the weight of the first connection state and the total of the weights when the second connection state is alternately calculated, which is calculated by Expression (5) to Expression (8). A chopper pattern that reduces the total is generated. Here, as an example, an analog integrator stages L = 3, the oversampling ratio m = 8, as V ₀ the offset of the analog amplifier, the weight of the case of switching the first and second connection states alternately Calculate the sum.

  The analog integrator 130 is reset, and the first analog integrator 210 integrates the analog input signal in the first connection state with respect to the first, third, fifth, and seventh analog input signals. Then, the first analog integrator 210 integrates the analog input signals in the second connection state with respect to the j = 2, 4, 6, 6 and 8th analog input signals. Here, it is assumed that the first analog integrator 210 performs a chopping operation, the second analog integrator 220 and the third analog integrator 230 have no offset error and do not perform the chopping operation. FIG. 7 shows the sum of the weights given to the modulation signal MOD0 when the analog input signal is integrated by the analog integrator 130.

FIG. 7 shows an example of the total value of weights when the analog integrator 130 according to the present embodiment alternately repeats the first connection state and the second connection state. In FIG. 7, the first connection state is set to the chopper polarity “+”, and the second connection state is set to the chopper polarity “−”. As described above, in the incremental type delta-sigma AD converter 100, the weight of the analog input signal with respect to the serial digital code of the conversion result becomes smaller as the input order of the analog input signal is later. Therefore, it can be seen that the sum of the weights is 0.167V ₀ , and a value of about の of the offset error V ₀ of the differential signal remains as an error of the converted digital signal.

  Therefore, chopper pattern generation section 370 generates a chopper pattern that does not alternately repeat the first connection state and the second connection state. For example, the chopper pattern generation unit 370 generates a chopper pattern in which at least one of the first connection state and the second connection state is continuous at least once without being inverted. As an example, the chopper pattern generation unit 370 does not invert the third chopper polarity after inverting the first and second chopper polarities. In addition, the chopper pattern generation unit 370 may alternately repeat a set in which the chopper polarity is not inverted. As an example, the chopper pattern generation section 370 inverts the fourth chopper polarity and does not invert the fifth chopper polarity. Further, the chopper pattern generating section 370, for example, inverts the sixth chopper polarity and does not invert the seventh chopper polarity. FIG. 8 shows an example of such a chopper pattern.

FIG. 8 shows a first example of a chopper pattern generated by the chopper pattern generator 370 according to the present embodiment. The chopper pattern generator 370 switches the first connection state and the second connection state alternately at an early stage of inputting the analog input signal (for example, j = 1 and 2), and then switches the first connection state or the second connection state. The second connection state is continued. Thereby, the first example of the chopper pattern shown in FIG. 8 can reduce the total weight as compared with the chopping operation in which the first connection state and the second connection state shown in FIG. 7 are alternately repeated. In the example of FIG. 8, the sum of the weights can be set to 0.033V _0, and it can be seen that the error of the converted digital signal can be reduced.

  Further, the chopper pattern generation unit 370 calculates the sum of the weight given to the modulation signal by the input to the analog integrator in each cycle of the first connection state in the cycle, and the analog integrator in each cycle of the second connection state in the cycle. Chopper pattern that minimizes the difference between the input to the modulation signal and the total weight given to the modulation signal may be generated. The chopper pattern generation unit 370 does not invert the third chopper polarity, for example, after inverting the first and second chopper polarities. Then, the chopper pattern generating section 370, for example, inverts the fourth and fifth chopper polarities and does not invert the sixth chopper polarity. Further, the chopper pattern generation section 370 inverts, for example, the seventh chopper polarity. FIG. 9 shows an example of such a chopper pattern.

FIG. 9 shows a second example of the chopper pattern generated by the chopper pattern generator 370 according to the present embodiment. The second example of the chopper pattern shows an example in which the number of stages L = 3 and the oversampling ratio m = 7. The second example of the chopper pattern shown in FIG. 9 can reduce the total weight as compared with the chopping operation in which the first connection state and the second connection state shown in FIG. 8 are alternately repeated. In the example of FIG. 9, it can be seen that the total of the weights can be set to approximately 0V ₀ and the error of the converted digital signal is minimized.

  The chopper pattern generator 370 may supply the first analog integrator 210 with the chopper pattern and the like described in the examples of FIGS. Further, chopper pattern generation section 370 may supply the chopper pattern to second analog integrator 220 and / or third analog integrator 230. That is, the analog integrator 130 may include a plurality of analog integrators, and at least one of the plurality of analog integrators changes the first connection state and the second connection state according to the chopper pattern. You may switch.

In this case, the chopper pattern generation section 370 may supply substantially the same chopper pattern to a plurality of analog integrators. May be supplied. For example, each of two or more analog integrators among the plurality of analog integrators switches between a first connection state and a second connection state according to mutually different chopper patterns. Thus, more chopper patterns and combinations of different chopper patterns can be used, so that the degree of freedom in designing the chopper patterns can be improved. Thereby, for example, the analog integrator 130 illustrated in FIG. 5 can reduce the offset error V ₀₁ , the offset error V ₀₂ , and the offset error V ₀₃ .

  The chopper pattern generation section 370 may be capable of outputting a chopper pattern selected from a plurality of different chopper patterns. For example, the chopper pattern generation section 370 may be capable of outputting the alternately switched chopper pattern for alternately switching between the first connection state and the second connection state described with reference to FIG. Further, the chopper pattern generator 370 may be capable of outputting a minimum error chopper pattern for minimizing an error of a modulation signal caused by an offset error of the analog amplifier as described with reference to FIG.

  Also, the chopper pattern generation section 370 can output a switching reduction chopper pattern in which the number of times of connection state switching is smaller than that of the minimum error chopper pattern and the error of the modulation signal is smaller than that of the alternating switching chopper pattern as described in FIG. Is fine. The chopper pattern generation section 370 may be capable of outputting a non-switchable chopper pattern that is fixed in the first connection state or the second connection state.

  Also, the chopper pattern generation unit 370 generates a chopper pattern selected from a plurality of chopper patterns including at least one of an alternate switching chopper pattern, a minimum error chopper pattern, a switching reduction chopper pattern, and a non-switching chopper pattern. Output may be possible. The chopper pattern generation section 370 may select and output a chopper pattern according to the use environment, required specifications, temporal changes, etc. of the incremental type delta-sigma AD converter.

  The example in which the analog integrator 130 according to the present embodiment has a plurality of analog integrators that input a differential signal and output the differential signal has been described. Instead of this, the analog integrator 130 may include an analog integrator that inputs a differential signal and outputs a single-ended signal. In this case, the analog integrator outputs the output value of the analog amplifier according to the inputs of the positive input terminal and the negative input terminal in the first connection state, and outputs the positive input terminal and the negative input terminal in the second connection state. Output the inverted value of the output value of the analog amplifier in accordance with the input.

  As described above, the present invention has been described using the embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is apparent to those skilled in the art that various changes or improvements can be made to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

The execution order of each processing such as operation, procedure, step, and stage in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before”, “before”. It should be noted that they can be realized in any order as long as the output of the previous process is not used in the subsequent process. Even if the operation flow in the claims, the specification, and the drawings is described using “first,” “second,” or the like for convenience, it means that it is essential to perform the operation in this order. Not something.
According to the present application, the following items are also disclosed.
[Item 1]
An analog integrator having an analog integrator and integrating an analog input signal;
A modulation processing unit that outputs a modulation signal according to the integration result of the analog integration unit;
A reset unit that resets an integral value held by the analog integrator at every predetermined cycle;
With
The analog integrator is
An analog amplifier that amplifies and outputs a signal input to a positive input terminal and a negative input terminal;
The first input terminal of the analog integrator is connected to the positive input terminal and the second input terminal of the analog integrator is connected to the negative input terminal in a first connection state, or the first input terminal is connected An input changeover switch for switching according to a chopper pattern whether to be in a second connection state in which the second input terminal is connected to the negative input terminal and the second input terminal is connected to the positive input terminal,
Having,
Incremental delta-sigma modulator.
[Item 2]
2. The incremental delta-sigma modulator according to item 1, further comprising a chopper pattern generation unit that generates a chopper pattern in which the first connection state is continuous or a chopper pattern in which the second connection state is continuous.
[Item 3]
The chopper pattern generation unit generates the chopper pattern for reducing an error of the modulation signal caused by an offset error of the analog amplifier as compared with a case where the first connection state and the second connection state are alternately switched. 3. The incremental delta-sigma modulator according to item 2.
[Item 4]
The cycle in which the reset unit resets includes a plurality of cycles,
The chopper pattern generation unit is configured to calculate a sum of weights given to the modulation signal by the input to the analog integrator in each cycle of the first connection state in the cycle, and to calculate each cycle of the second connection state in the cycle. Generating the chopper pattern for reducing the difference between the input to the analog integrator and the sum of the weights given to the modulation signal as compared with the case where the first connection state and the second connection state are alternately switched. Do
Item 3. The incremental type delta-sigma modulator according to item 3.
[Item 5]
The chopper pattern generation unit is configured to calculate a sum of weights given to the modulation signal by the input to the analog integrator in each cycle of the first connection state in the cycle, and to calculate each cycle of the second connection state in the cycle. 5. The incremental delta-sigma modulator according to item 4, wherein the chopper pattern is generated so as to minimize a difference between the input to the analog integrator and the total weight given to the modulation signal.
[Item 6]
6. The incremental delta-sigma modulation according to any one of items 1 to 5, wherein the analog integrator has an output changeover switch for switching a connection destination of an output of the analog amplifier in the first connection state and the second connection state. vessel.
[Item 7]
7. The incremental delta-sigma modulator according to item 6, wherein the analog integrator is connected to a stage subsequent to the output changeover switch, and further includes amplifying means to which an output of the output changeover switch is input.
[Item 8]
The analog amplifier amplifies signals input to the positive input terminal and the negative input terminal and outputs the amplified signals from a positive output terminal and a negative output terminal,
In the first connection state, the output switch connects the positive output terminal of the analog amplifier to the first output terminal of the analog integrator, and connects the negative output terminal of the analog amplifier to the second output terminal of the analog integrator. Connecting the positive output terminal to the second output terminal and the negative output terminal to the first output terminal in the second connection state;
Item 8. The incremental type delta-sigma modulator according to item 6 or 7.
[Item 9]
The analog integrator has a plurality of the analog integrators,
9. The incremental type according to any one of items 1 to 8, wherein at least one analog integrator of the plurality of analog integrators switches the first connection state and the second connection state according to the chopper pattern. Delta-sigma modulator.
[Item 10]
Item 10. The incremental delta-sigma modulation according to item 9, wherein each of two or more analog integrators among the plurality of analog integrators switches between the first connection state and the second connection state according to the different chopper patterns. vessel.
[Item 11]
6. The incremental delta-sigma modulator according to any one of items 2 to 5, wherein the chopper pattern generation unit can output a chopper pattern selected from a plurality of different chopper patterns.
[Item 12]
The chopper pattern generator includes an alternate switching chopper pattern for alternately switching the first connection state and the second connection state, a minimum error chopper pattern for minimizing an error of the modulation signal caused by an offset error of the analog amplifier, A switching reduction chopper pattern in which the number of times of connection state switching is smaller than the minimum error chopper pattern and in which the error of the modulation signal is smaller than the alternating switching chopper pattern, and the first connection state or the second connection state is fixed. Item 12. The incremental delta-sigma modulator according to item 11, wherein a chopper pattern selected from the plurality of chopper patterns including at least one of the non-switching chopper patterns can be output.
[Item 13]
The modulation processing unit has a quantizer that quantizes the integration result of the analog integration unit,
The incremental type delta-sigma modulator further includes a DA converter for DA-converting the output of the quantizer and feeding it back to the analog integrator.
Item 13. The incremental delta-sigma modulator according to any one of Items 1 to 12.
[Item 14]
14. An incremental delta-sigma modulator according to any one of items 1 to 13,
A digital operation unit that integrates the modulation signal and outputs a digital value,
Comprising,
Incremental delta-sigma AD converter.
[Item 15]
Having an analog integrator and integrating an analog input signal;
Outputting a modulation signal according to the integration result of the analog input signal;
Resetting the integrated value held by the analog integrator every predetermined period;
With
The analog integrator is
An analog amplifier that amplifies and outputs a signal input to a positive input terminal and a negative input terminal;
The first input terminal of the analog integrator is connected to the positive input terminal and the second input terminal of the analog integrator is connected to the negative input terminal in a first connection state, or the first input terminal is connected An input changeover switch for switching according to a chopper pattern whether to be in a second connection state in which the second input terminal is connected to the negative input terminal and the second input terminal is connected to the positive input terminal,
Having,
Modulation method.

Reference Signs List 10 incremental delta-sigma modulator, 100 incremental delta-sigma AD converter, 110 sample-hold unit, 120 adder unit, 130 analog integrator, 140 modulation processor, 150 DA converter, 152 first switch unit, 154 second Switch section, 156 third switch section, 160 digital operation section, 170 reset section, 210 first analog integrator, 212 first analog amplifier, 214 positive reset switch, 216 negative reset switch, 220 second analog integrator, 222 second analog amplifier, 224 positive reset switch, 226 negative reset switch, 230 third analog integrator, 232 third analog amplifier, 234 positive reset switch, 236 negative reset switch, 240 first switch Chitocapacitor, 242 front switch, 244 rear switch, 245 second switched capacitor, 246 front switch, 248 rear switch, 250 first feedforward section, 252 first FF switch, 260 second feedforward section, 262 second FF switch, 270 3rd feedforward section, 272 3rd FF switch, 280 4th feedforward section, 282 4th FF switch, 310 1st input changeover switch, 312 switch, 314 switch, 316 switch, 318 switch, 320 1st output changeover switch, 322 Switch, 324 switch, 326 switch, 328 switch, 330 second input switch, 340 second output switch, 350 third input switch, 360 third Output switch, 370 Chopper pattern generator

Claims (12)

An analog integrator having an analog integrator and integrating an analog input signal;
A modulation processing unit that outputs a modulation signal according to the integration result of the analog integration unit;
A reset unit that resets an integral value held by the analog integrator at every predetermined cycle;
A chopper pattern generating section,
With
The analog integrator comprises:
An analog amplifier that amplifies and outputs a signal input to a positive input terminal and a negative input terminal;
A first connection state in which a first input terminal of the analog integrator is connected to the positive input terminal and a second input terminal of the analog integrator is connected to the negative input terminal, or the first input terminal is An input changeover switch that switches whether the second input terminal is connected to the negative input terminal and the second input terminal is connected to the positive input terminal in a second connection state according to a chopper pattern generated by the chopper pattern generation unit. Yes, and
The cycle in which the reset unit resets includes a plurality of cycles,
The chopper pattern generation unit generates a chopper pattern in which the first connection state is continuous or a chopper pattern in which the second connection state is continuous, and outputs the chopper pattern to the analog integrator in each cycle of the first connection state in the cycle. The difference between the sum of the weights given by the input of the analog integrator to the modulation signal and the sum of the weights given by the input to the analog integrator to the modulation signal in each cycle of the second connection state in the cycle is represented by the first Generating a first chopper pattern that is smaller than a case where the connection state and the second connection state are alternately switched;
Incremental delta-sigma modulator. The chopper pattern generation unit includes: a total of weights given to the modulation signal by the input to the analog integrator in each cycle of the first connection state in the cycle; and a cycle of the second connection state in the cycle. 2. The incremental delta-sigma modulator according to claim 1 , wherein a second chopper pattern that minimizes a difference between an input to the analog integrator and a total weight given to the modulation signal is generated. The analog integrator, the incremental delta-sigma modulator according to claim 1 or 2 having an output switching switch for switching a connection destination of the output of the analog amplifier in the second connection state to the first connection state. 4. The incremental delta-sigma modulator according to claim 3 , wherein the analog integrator is further connected to a subsequent stage of the output changeover switch, and further includes amplifying means to which an output of the output changeover switch is input. The analog amplifier amplifies a signal input to the positive input terminal and the negative input terminal and outputs the amplified signal from a positive output terminal and a negative output terminal.
In the first connection state, the output switch connects the positive output terminal of the analog amplifier to the first output terminal of the analog integrator, and connects the negative output terminal of the analog amplifier to the second output terminal of the analog integrator. 5. The incremental delta according to claim 3 , wherein the positive-side output terminal is connected to the second output terminal and the negative-side output terminal is connected to the first output terminal in the second connection state. 6. Sigma modulator. The analog integrator has a plurality of the analog integrators,
The incremental according to any one of claims 1 to 5 , wherein at least one analog integrator among the plurality of analog integrators switches the first connection state and the second connection state according to the chopper pattern. Type delta-sigma modulator. The incremental delta sigma according to claim 6 , wherein each of two or more analog integrators of the plurality of analog integrators switches the first connection state and the second connection state according to the different chopper patterns. Modulator. The incremental delta-sigma modulator according to claim 2 , wherein the chopper pattern generator is capable of outputting a chopper pattern selected from a plurality of different chopper patterns. The chopper pattern generating unit is configured to alternately switch the first connection state and the second connection state alternately, the first chopper pattern, the second chopper pattern, and the first connection state or the second connection state. The incremental delta-sigma modulator according to claim 8 , wherein a chopper pattern selected from the plurality of chopper patterns including at least one of the non-switching chopper patterns fixed in a connected state can be output. The modulation processing unit includes a quantizer that quantizes an integration result of the analog integration unit,
The incremental delta-sigma modulator according to any one of claims 1 to 9 , wherein the incremental delta-sigma modulator further includes a DA conversion unit that performs DA conversion of an output of the quantizer and feeds the output back to the analog integrator. Modulator. An incremental delta-sigma modulator according to any one of claims 1 to 10 ,
A digital operation unit that integrates the modulation signal and outputs a digital value,
An incremental type delta-sigma A / D converter. Having an analog integrator and integrating an analog input signal;
Outputting a modulation signal according to the integration result of the analog input signal;
A step of resetting an integrated value held by the analog integrator every predetermined period by a reset unit ;
A step in which the chopper pattern generating section generates a chopper pattern;
With
The analog integrator comprises:
An analog amplifier that amplifies and outputs a signal input to a positive input terminal and a negative input terminal;
A first connection state in which a first input terminal of the analog integrator is connected to the positive input terminal and a second input terminal of the analog integrator is connected to the negative input terminal, or the first input terminal is An input changeover switch that switches whether the second input terminal is connected to the negative input terminal and the second input terminal is connected to the positive input terminal in a second connection state according to a chopper pattern generated by the chopper pattern generation unit. Yes, and
The cycle in which the reset unit resets includes a plurality of cycles,
The chopper pattern generation unit generates a chopper pattern in which the first connection state is continuous or a chopper pattern in which the second connection state is continuous, and outputs the chopper pattern to the analog integrator in each cycle of the first connection state in the cycle. The difference between the sum of the weights given by the input of the analog integrator to the modulation signal and the sum of the weights given by the input to the analog integrator to the modulation signal in each cycle of the second connection state in the cycle is represented by the first Generating a first chopper pattern that is smaller than a case where the connection state and the second connection state are alternately switched;
Modulation method.

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