JP2018198407A - Incremental delta-sigma ad converter and ad conversion method - Google Patents

Abstract

To provide an incremental delta-sigma AD converter in which quantization error is reduced, while considering the residual component of an integrator accurately.SOLUTION: An incremental delta-sigma AD converter 10 includes a delta-sigma conversion part 100 outputting a modulation digital signal produced by performing delta-sigma modulation of an input analog signal, and a digital filter for filtering the modulation digital signal. The delta-sigma conversion part has an analog integration part having multiple analog integrators in cascade connection, and integrating a signal based on the input analog signal, and a reset part for not resetting an integration value held by the last stage analog integrator, but resetting integration values held by the remaining analog integrators excepting the analog integrator in the last stage, out of the multiple analog integrators, every predetermined period.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an incremental delta-sigma AD converter and an AD conversion method.

Conventionally, an incremental delta-sigma AD converter that has a plurality of integration circuits and converts an analog signal into a digital signal and resets the charge accumulated in the integration circuit at a predetermined time interval is known. (For example, refer to Patent Document 1).
Patent Document 1 International Publication No. 2013/136676

  Such an incremental type delta-sigma AD converter is known to have a residual component in the final stage integration circuit after the integration operation of a plurality of integration circuits. Incremental delta-sigma AD converters may cause quantization errors in the output digital signal when the residual component is taken into account. Thus, by feeding back the value corresponding to the residual component to a plurality of integration circuits, the quantization error is skipped to a high frequency, and the noise in the band is reduced by a digital filter or the like at the subsequent stage. However, it is difficult to generate an accurate feedback component corresponding to the residual component, and the cost is increased.

  In a first aspect of the present invention, a delta-sigma conversion unit that outputs a modulated digital signal obtained by delta-sigma modulation of an input analog signal, and a digital filter unit that filters the modulated digital signal, the delta-sigma conversion unit includes: It has a plurality of cascaded analog integrators, and the analog integrator that integrates the signal based on the input analog signal and the analog integrator at the final stage among the plurality of analog integrators is held for each predetermined period There are provided an incremental delta-sigma AD converter and an AD conversion method having a reset unit that does not reset an integration value to be reset and resets an integration value held by the remaining analog integrators other than the last-stage analog integrator.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 shows a configuration example of an incremental delta-sigma AD converter 10 according to the present embodiment. The structural example of the analog integration part 130 which concerns on this embodiment is shown. The comparative example of the delta-sigma conversion part 100 is shown. The structural example of the delta-sigma conversion part 100 which concerns on this embodiment is shown. An example of the timing chart of the incremental type delta-sigma AD converter 10 concerning this embodiment is shown. The modification of the incremental type delta-sigma AD converter 10 concerning this embodiment is shown. 2 shows a configuration example of the feedforward unit 140 and the quantization unit 150 of the incremental delta-sigma AD converter 10 according to the present embodiment. 2 shows a configuration example of a sample hold unit 110 and a DA conversion unit 160 according to the present embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

FIG. 1 shows a configuration example of an incremental delta-sigma AD converter 10 according to the present embodiment. The incremental type delta sigma AD converter 10 converts the analog signal A _in inputted from the input terminal 12 into a digital signal D _out and outputs it from the output terminal 14 while resetting an internal circuit. The incremental delta sigma AD converter 10 includes an input terminal 12, an output terminal 14, a delta sigma conversion unit 100, and a digital filter unit 190.

Input terminal 12 receives an input analog signal _{A in.} The input terminal 12 may be a single-ended input, or may be a differential input instead. When the input terminal 12 is a differential input, the input terminal 12 receives a positive signal A _inp from a positive input and a negative signal A _inn from a negative input. The input terminal 12 supplies the input signal A _in to the delta sigma conversion unit 100.

The output terminal 14 outputs the digital signal D _OUT converted by the incremental delta sigma AD converter 10 _in accordance with the input analog signal A _in . The output terminal 14 may be a single-ended output, or may be a differential output instead.

Delta sigma modulation section 100 outputs a modulated digital signal Y to the input analog signal A _in the delta-sigma modulation. The delta sigma conversion unit 100 includes an addition unit 120, an analog integration unit 130, a quantization unit 150, a DA conversion unit 160, a reset unit 170, and a control unit 180.

The adder 120 adds the feedback signal from the DA converter to the input analog signal A _in input from the input terminal 12. When the input terminal 12 is a differential input, the adder 120 may add feedback signals having different signs to the positive signal A _inp and the negative signal A _inp of the differential signal. The addition unit 120 supplies the addition result to the analog integration unit 130.

  The analog integration unit 130 includes a plurality of cascaded analog integrators, and integrates a signal based on an input analog signal. The analog integration unit 130 integrates the output of the addition unit 120. The analog integration unit 130 supplies the result of integration to the quantization unit 150 as an output signal.

  The quantization unit 150 quantizes the output signal of the analog integration unit 130. The quantization unit 150 quantizes the integration result of the analog integration unit 130 according to a clock signal or the like supplied from the outside, and outputs a bit stream corresponding to the integration result. The quantization unit 150 may include a 1-bit quantizer or a multi-bit quantizer. That is, the quantization unit 150 may quantize the output signal of the analog integration unit 130 into a binary or multilevel digital signal.

For example, when a 1-bit quantizer is used as the quantization unit 150, the bit stream is a predetermined number of 1-bit data (digital code) sequences (serial digital codes), and the digital codes are integrated. value is a digital value proportional or substantially equal to the amplitude value of the input signal a _in. The quantization unit 150 may compare the output signal with a predetermined threshold for each clock signal, and convert the output signal into a 1 or 0 digital code depending on whether the threshold is exceeded.

For example, when an M-bit quantizer is used as the quantization unit 150, the bit stream is a sequence (serial digital code) of a predetermined number of M-bit data (digital code). cumulative value becomes a digital value proportional or substantially equal to the amplitude value of the input signal a _in. For each clock signal, the quantization unit 150 compares the output signal with a predetermined M-bit threshold by a comparator for M bits, and outputs the output depending on whether each comparator exceeds the threshold. The signal may be converted to an M-bit digital code.

That is, the incremental type delta-sigma AD converter 10 converts the input signal A _in to a digital value every fixed conversion cycle, but the quantization unit 150 has an externally supplied clock signal that is faster than one conversion cycle. depending on the like, and outputs a serial digital code corresponding to the input signal a _in. In this way, the input signal A _in is converted into a digital value for each of a plurality of samples synchronized with the clock signal, and the number of samples for one conversion cycle is set as the oversampling ratio. That is, the number of digital codes included in the serial digital code is equal to the oversampling ratio.

  For example, when the oversampling ratio of the incremental delta-sigma AD converter 10 is 60, the quantization unit 150 outputs a serial digital code including 60 digital codes every conversion cycle. The quantization unit 150 supplies the quantized digital signal Y to the DA conversion unit 160 and the digital filter unit 190.

  The DA conversion unit 160 outputs a feedback signal based on the output of the quantization unit 150. The DA conversion unit 160 DA-converts the digital signal Y output from the quantization unit 150 into a corresponding analog signal, and supplies the converted analog signal to the addition unit 120 as a feedback signal. The feedback signal may be a predetermined reference voltage. The feedback signal will be described later. The DA converter 160 may convert the digital signal Y into an analog signal in synchronization with the clock signal.

The reset unit 170 resets the integration value held by the analog integration unit 130 every predetermined period. In addition, the reset unit 170 may reset the digital filter unit 190 at the timing when the analog integration unit 130 is reset. The reset unit 170 may reset the analog integration unit 130 and the digital filter unit 190 every time the incremental delta sigma AD converter 10 converts the input signal _Ain into a digital value. For example, the reset unit 170 resets the analog integration unit 130 and the digital filter unit 190 by supplying a reset signal for each conversion cycle to a digital value.

  The control unit 180 controls the operation of the delta sigma conversion unit 100. For example, the control unit 180 controls the operation of the analog integration unit 130. The control unit 180 may execute the control operation of the delta-sigma conversion unit 100 according to a clock signal or the like supplied from the inside or the outside. The control unit 180 may include a clock oscillator and execute control operations of the respective units.

  The digital filter unit 190 filters the modulated digital signal output from the quantization unit 150. The digital filter unit 190 filters and outputs the digital signal Y received from the quantization unit 150. The digital filter unit 190 may be an integration filter that integrates the bit stream of the digital signal Y and performs digital integration. In this case, the digital filter unit 190 may calculate a digital value by multiplying the integrated value by a predetermined coefficient. The digital filter unit 190 may calculate a digital value in synchronization with the clock signal. Further, the digital filter unit 190 may reset the integrated amount in response to receiving the reset signal from the reset unit 170.

Further, the digital filter unit 190 may have a low-pass filter and reduce quantization noise generated in the quantization unit 150. The digital filter unit 190 may have a decimation filter to reduce the sampling frequency. The digital filter unit 190 supplies the digital value of the calculation result to the output terminal 14. The output terminal 14 outputs the received digital value as the digital output D _OUT of the incremental delta sigma AD converter 10.

As described above, the incremental delta-sigma AD converter 10 according to the present embodiment performs the reset of the analog integration unit 130 and the digital filter unit 190 by the reset unit 170 and the conversion of the input signal A _{in to} the digital output. Repeat in synchronization with the clock signal. Note that the incremental type delta sigma AD converter 10 may operate as a delta sigma AD converter as long as there is no reset operation by the reset unit 170.

  FIG. 2 shows a configuration example of the analog integration unit 130 according to the present embodiment. FIG. 2 is an example of the analog integration unit 130 of the incremental delta-sigma AD converter 10 shown in FIG. FIG. 2 shows an example in which a differential signal based on the positive signal SP and the negative signal SN is input from the adder 120 to the analog integrator 130. The analog integration unit 130 includes a plurality of analog integrators and a plurality of switched capacitors.

  The analog integration unit 130 shown in FIG. 2 shows an example including three analog integrators: a first analog integrator 210, a second analog integrator 220, and a third analog integrator 230. In addition, the analog integration unit 130 shows an example having two switched capacitors, a first switched capacitor 240 and a second switched capacitor 245.

  FIG. 2 shows an example in which each of the three analog integrators has two input terminals and two output terminals, and inputs a differential signal and outputs a differential signal. One of the two input terminals of the analog integrator is a first input terminal, and the other is a second input terminal. One of the two output terminals of the analog integrator is a first output terminal, and the other is a second output terminal.

The analog integrator includes an analog amplifier, a feedback capacitor, and a reset switch, respectively. FIG. 2 shows an example where the first analog integrator 210 includes a first analog amplifier 212, a positive feedback capacitor C _i1p , a negative feedback capacitor C _i1n , a positive reset switch 214, and a negative reset switch 216. The second analog integrator 220 includes a second analog amplifier 222, a positive feedback capacitor C _i2p , a negative feedback capacitor C _i2n , a positive reset switch 224, and a negative reset switch 226, and a third analog An example in which the integrator 230 includes a third analog amplifier 232, a positive feedback capacitor C _i3p , a negative feedback capacitor C _i3n , a positive reset switch 234, and a negative reset switch 236 is shown.

  The analog amplifier amplifies and outputs signals input to the positive input terminal and the negative input terminal. The analog amplifier is, for example, a differential input type amplifier circuit. Further, the analog amplifier may be a single-ended output, and may instead be a differential output. As an example, the analog amplifier is an OP amplifier. FIG. 2 shows an example in which the three analog integrators of the first analog integrator 210, the second analog integrator 220, and the third analog integrator 230 each include differential input and differential output analog amplifiers. . In FIG. 2, the positive input terminal of the analog amplifier is connected to the first input terminal of the analog integrator, and the negative input terminal is connected to the second input terminal.

Each of the feedback capacitors sequentially accumulates charges corresponding to the input signal. For example, the feedback capacitor sequentially accumulates electric charges from the previous stage to the subsequent stage every sampling. As an example, in response to the positive signal SP, the positive charge stored in the feedback capacitor C _i1p in the first clock is accumulated on the positive side feedback capacitor C _i2p in the next second clock, in the next third clock Accumulated in the positive feedback capacitor C _i3p . Similarly, in response to the negative signal SN, charges accumulated in the negative feedback capacitor C _I1n in the first clock is accumulated on the negative side feedback capacitor C _i2n in the next second clock, in the next third clock Accumulated in the negative feedback capacitor C _i3n .

  In response to an instruction from the reset unit 170, the reset switch discharges the electric charge accumulated in the feedback capacitor and resets the analog integrators. For example, the reset switch connects between terminals of the feedback capacitor in accordance with a reset signal supplied from the reset unit 170 and discharges the accumulated charge. In the example of FIG. 2, a positive reset switch 214, a negative reset switch 216, a positive reset switch 224, a negative reset switch 226, a positive reset switch 234, and a negative reset according to an instruction from the reset unit 170. The switches 236 are turned on, respectively, to reset the first analog integrator 210, the second analog integrator 220, and the third analog integrator 230.

  The switched capacitor is provided between the analog integrators, and transmits the charges accumulated in the analog integrator connected to the preceding stage to the analog integrator connected to the succeeding stage. The switched capacitor includes a charge / discharge capacitor and a switch provided in the front stage and the rear stage of the capacitor. The front-stage switch switches the connection destination of one terminal of the capacitor to either the front-stage circuit of the switched capacitor or the reference potential. The latter-stage switch switches the connection destination of the other terminal of the capacitor to either the latter-stage circuit of the switched capacitor or the reference potential. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

  For example, in one clock, a switched capacitor is configured such that one terminal of a capacitor is connected to a previous analog integrator and the other terminal of the capacitor is connected to a reference potential, whereby an analog integrator connected to the previous stage is connected. The capacitor charges the output charge. In this case, in the switched capacitor, in the next clock, one terminal of the capacitor is connected to the reference potential, and the other terminal of the capacitor is connected to the subsequent analog integrator, so that the charge charged by the capacitor is transferred to the subsequent stage. To the analog integrator.

FIG. 2 shows an example in which the first switched capacitor 240 is connected between the first analog integrator 210 and the second analog integrator 220. The first switched capacitor 240 uses the front-stage switch 242 and the rear-stage switch 244, and the capacitor C _s2p charges the charge accumulated in the front-stage positive-side feedback capacitor C _i1p to the rear-stage positive-side feedback capacitor C _i2p . And discharge and transmit. In this case, similarly, the first switched capacitor 240, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _I1n, capacitor C _s2n is charged, and discharged to the subsequent negative feedback capacitor C _i2n To do.

FIG. 2 shows an example in which the second switched capacitor 245 is connected between the second analog integrator 220 and the third analog integrator 230. The second switched capacitor 245 uses the front-stage switch 246 and the rear-stage switch 248, and the capacitor C _s3p charges the charge accumulated in the front-stage positive feedback capacitor C _i2p to the rear-stage positive feedback capacitor C _i3p . And discharge and transmit. In this case, likewise, the second switched capacitor 245, transmits the pre-stage of the charge accumulated in the negative feedback capacitor C _i2n, capacitor C _S3N are charged, and discharged to the subsequent negative feedback capacitor C _I3n To do.

  As described above, the analog integrator 130 has a plurality of analog integrators connected in series, and charges the positive side signal SP and the negative side signal SN from the preceding analog integrator to the subsequent analog integrator every clock. Are sequentially accumulated and transmitted. The analog integration unit 130 outputs the electric charge accumulated in the feedback capacitor of the most subsequent analog integrator to the quantization unit 150. For example, the analog integrator 130 shown in FIG. 2 has a three-stage analog integrator, so that the charge accumulated in the first analog integrator 210 in the first clock is transferred to the third analog integrator 230 in the third clock. The signal is transmitted to the quantization unit 150.

  In addition, the control unit 180 supplies a control signal to the analog integration unit 130 to cause the analog integration unit 130 to execute the operation. For example, the controller 180 includes a clock oscillator that generates a clock signal having a predetermined frequency, and supplies the clock signal to the analog integrator 130. The control unit 180 may stop the supply of the clock signal to the analog integration unit 130 and stop the integration operation of the analog integration unit 130.

  Note that FIG. 2 illustrates an example in which the analog integrator 130 includes three analog integrators. Alternatively, the analog integrator 130 may include two or four or more analog integrators. Good. In this case, one or three or more switched capacitors may be provided in the analog integration unit 130 according to the number of analog integrators. Instead of this, the analog integrator 130 may include one analog integrator.

  The incremental delta-sigma AD converter 10 according to the above embodiment integrates an input analog signal, and adds or subtracts a reference voltage to the input analog signal according to the quantization result of the integration result. Execute. Thereby, the incremental type delta-sigma AD converter 10 can accurately output a serial digital code corresponding to the input analog signal. The incremental delta-sigma AD converter 10 can digitally process such a serial digital code and output a digital signal corresponding to the analog signal with high accuracy.

  Unlike the delta sigma AD converter, the incremental delta sigma AD converter 10 discharges and resets the electric charge accumulated in the analog integration unit 130 at a constant period. As a result, the digital value converted in one conversion cycle can be converted to a value obtained by converting the analog input signal value more accurately without being affected by the charge accumulated in a different cycle from the one conversion cycle. Can do.

The digital output voltage of the incremental delta sigma AD converter 10 will be described. Here, it is assumed that the input voltage from the input terminal 12 in the i-th clock signal from the reset signal supplied by the reset unit 170 is V _in (i) and the digital output of the quantization unit 150 is Y (i). The clock signal is generated m times in one conversion cycle. Here, assuming that an analog output that is output at the end of one conversion cycle by the integrator in the final stage of the analog integrator 130 is V _out (m), V _out (m) can be expressed by the following equation.
(Equation 1)
V _out (m) = ΣΣ [C ₁ · Σ {V _in (i) −Y (i)}]
= C ₁ · ΣΣΣ {V _in (i) −Y (i)}

Here, the analog voltage of the analog signal that the incremental delta-sigma AD converter 10 should convert into a digital signal in one conversion cycle is _Vana . For example, when the input voltage from the input terminal 12 is a substantially constant voltage that does not vary substantially in one conversion cycle, or is a substantially constant sampling voltage by a sample hold circuit or the like, the analog voltage _Vana is approximately constant. Voltage. When the input voltage from the input terminal 12 fluctuates in one conversion cycle, the analog voltage _Vana may be approximately the same value as the average value of the fluctuated voltage in one conversion cycle. That is, the analog voltage V _ana can be expressed by the following equation using the input voltage V _in (i) _in the i-th clock signal.
(Equation 2)
V _ana = C ₁ · ΣΣΣV _in (i) / (C ₁ · ΣΣΣ)

By transforming (Equation 1) and substituting it into (Equation 2), the following equation is obtained.
(Equation 3)
V _ana = {C ₁ · ΣΣΣY (i) + V _out (m)} / (C ₁ · ΣΣΣ)

The first term of the equation (3) corresponds to the result of the digital filter unit 190 integrating the digital signal Y (i) quantized by the quantization unit 150. That is, the incremental delta-sigma AD converter 10 shown in FIG. 1 outputs the first term of the formula (3) as an AD conversion result for the input analog voltage _Vana . Therefore, the incremental type delta sigma AD converter 10 theoretically outputs a value in which the second term of Expression (3) is insufficient, and the digital output may include a quantization error.

  Note that the second term of the equation (3) is an analog output output by the analog integration unit 130 at the end of one conversion cycle, which is represented by the equation (1). Accordingly, it is indicated that a residual component that can become quantization noise remains in the output of the final-stage integrator of the analog integrator 130. Note that the incremental delta-sigma AD converter 10 may continue the operation of the digital filter unit 190 according to the clock signal after the analog integration unit 130 outputs the residual component. As a result, the digital filter unit 190 integrates the residue components, so that the quantization error can be reduced.

  However, in this case, since the integration operation of the digital filter unit 190 is continued, the time interval of one conversion cycle is extended. Since it is desirable that the AD converter has a higher conversion speed, it is desirable to reduce the quantization error without changing the length of one conversion cycle. In this case, the incremental type delta-sigma AD converter 10 has a configuration in which the residual component of the analog integration unit 130 is fed back and added in order to reduce the quantization error without changing the length of one conversion cycle. . Next, such an incremental type delta sigma AD converter 10 will be described.

  FIG. 3 shows a comparative example of the delta-sigma conversion unit 100. In the delta sigma conversion unit 100 of the comparative example, the same reference numerals are given to the substantially same operations as those of the delta sigma conversion unit 100 shown in FIG.

  The analog integration unit 130 illustrated in FIG. 3 is illustrated in a simplified manner, but may have substantially the same configuration as the analog integration unit 130 illustrated in FIG. Instead, the analog integration unit 130 may have a configuration in which the differential signal of the analog integration unit 130 illustrated in FIG. 2 is changed to a single-ended signal. FIG. 3 also shows the amplification factors of the first analog integrator 210, the second analog integrator 220, and the third analog integrator 230 as b1, b2, and b3, respectively. The delta sigma conversion unit 100 according to the present modification further includes a gain adjustment unit 310 and a delay element 320.

  The gain adjustment unit 310 adjusts and outputs the signal output from the analog integration unit 130. The gain adjusting unit 310 may adjust the gain so as to attenuate the reciprocal of the amplification factor of the analog integrating unit 130. For example, when the amplification factor of the analog integration unit 130 is b1, b2, and b3, the gain adjustment unit 310 outputs the output of the analog integration unit 130 by approximately 1 / (b1 · b2 · b3) times.

  The delay element 320 supplies the signal adjusted by the gain adjusting unit 310 to the adding unit 120 after delaying a predetermined time. That is, the gain adjustment unit 310 and the delay element 320 adjust the output of the analog integration unit 130 and feed it back to the input side of the analog integration unit 130. Here, the gain adjustment unit 310 amplifies the signal component fed back by the analog integration unit 130 and outputs the signal voltage that is substantially equal to the voltage of the residual component of the third analog integrator 230 in the previous conversion cycle. Adjust the gain.

  In addition, the delay element 320 has a gain adjustment unit so that the output of the third analog integrator 230 in the previous conversion cycle before this time is superimposed on the output of the third analog integrator 230 in the current conversion cycle. The output of 310 is delayed. Thus, by providing the feedback path of the gain adjusting unit 310 and the delay element 320, the incremental delta-sigma AD converter 10 ideally includes the first term and the second term of Equation (3). Can be output as an AD conversion result.

An ideal example for feeding back such residual components will be described. First, Table 1 shows an example of signal output by an incremental delta-sigma AD converter without feedback.

  Here, the analog input signal is a DC signal corresponding to a digital signal output of 1.5 LSB (Least Significant Bit). In this case, the signal converted into a digital signal becomes 1LSB, and an analog signal corresponding to 0.5LSB remains as a residual component in the analog integrator in the final stage. Thus, the digital signal converted corresponding to the analog input signal is always 1 LSB regardless of the number of conversions, resulting in a quantization error.

On the other hand, Table 2 shows an example of a signal output by an incremental delta sigma AD converter in which the residual component is ideally fed back.

  In the example of Table 2, the analog input signal is a DC signal corresponding to 1.5 LSB of the digital signal output. In the first conversion, since the feedback signal is 0, the digital signal output is 1 LSB as in Table 1. However, in the second conversion, a signal corresponding to 0.5 LSB, which is a residual component of the analog integrator in the final stage, is fed back, so that the input signal is 2 LSB. Therefore, the second conversion result is 2LSB corresponding to the 2LSB analog input signal, and the residual component of the analog integrator in the final stage is 0.

  In the third conversion, since the feedback signal is 0, the result is the same as the first conversion result. In the fourth conversion, the feedback signal is 0.5 LSB, so the result is the same as the second conversion result. Thus, since the digital signal output converted corresponding to the analog input signal outputs 1 LSB and 2 LSB alternately, the average of the digital signal output is approximately 1.5 LSB.

  That is, it can be seen that by feeding back the residual component, it is possible to reduce the quantization error and obtain a conversion result closer to the input analog signal. The averaging process may be substantially the same as the low-pass filter process by the digital filter unit 190. Instead of or in addition to this, a digital circuit that executes the filtering process may be provided separately from the digital filter unit 190. The filtering process corresponds to obtaining a more accurate output code by reducing the noise modulated by the delta-sigma conversion unit 100 to a high frequency.

  The configuration shown in FIG. 3 is an example of an incremental delta-sigma AD converter 10 that feeds back such residual components. However, since the gain adjustment unit 310 and the delay element 320 in FIG. 3 reduce the minute signal less than 1 LSB to about 1 / (b1 · b2 · b3) times as a feedback signal, the feedback signal is accurate. May be difficult to transfer.

  For example, when a residual component is taken out from the final stage integration circuit of the analog integration unit 130, noise may be mixed because circuit wiring is added to the analog output of the integration circuit sensitive to noise. In this case, since the feedback signal fluctuates, the circuit operation may become unstable depending on the magnitude of noise. It also increases the cost of adding and adjusting the feedback circuit.

  Therefore, the incremental delta-sigma AD converter 10 according to the present embodiment reduces the quantization error by approaching an ideal feedback operation while preventing an increase in cost. Next, such an incremental type delta sigma AD converter 10 will be described.

  FIG. 4 shows a configuration example of the delta-sigma conversion unit 100 according to the present embodiment. In the delta-sigma conversion unit 100 of the present embodiment shown in FIG. 4, the same reference numerals are given to the substantially same operations as those of the delta-sigma conversion unit 100 shown in FIG.

  The analog integration unit 130 illustrated in FIG. 4 is illustrated in a simplified manner, but may have substantially the same configuration as the analog integration unit 130 illustrated in FIG. Instead, the analog integration unit 130 may have a configuration in which the differential signal of the analog integration unit 130 illustrated in FIG. 2 is changed to a single-ended signal. FIG. 4 also shows the amplification factors of the first analog integrator 210, the second analog integrator 220, and the third analog integrator 230 as b1, b2, and b3, respectively.

  The reset unit 170 of the present embodiment does not reset the integration value held by the last-stage analog integrator among a plurality of analog integrators every predetermined period, and excludes the last-stage analog integrator. Reset the integration value held by the remaining analog integrator. The reset unit 170 may supply a reset signal that causes the analog integrator other than the final-stage analog integrator to reset the integral value for each conversion cycle of the incremental delta-sigma AD converter 10. For example, in the example of FIG. 4, the reset unit 170 outputs a reset signal that causes the first analog integrator 210 and the second analog integrator 220 to reset the integration value every conversion cycle.

  As described above, the analog integrator at the final stage of the present embodiment does not reset even after one conversion cycle is completed, and carries the residual component to the next conversion cycle. Then, the analog integrator at the final stage of the analog integration unit 130 adds the integration value held in one conversion cycle to the integration value held in the next conversion cycle. In the example of FIG. 4, the third analog integrator 230 adds the integration value held in one conversion cycle to the quantization unit 150 in addition to the integration value held in the next conversion cycle.

  As a result, the residual component held by the last-stage analog integrator in one conversion cycle can be directly reflected in the value accumulated by the last-stage analog integrator in the next conversion cycle. That is, the delta-sigma conversion unit 100 according to the present embodiment reflects the residual component in one conversion cycle in the next conversion cycle without feeding back to the first-stage analog integrator. Mixing can be prevented. Next, a timing chart of the incremental delta sigma AD converter 10 will be described.

  FIG. 5 shows an example of a timing chart of the incremental delta-sigma AD converter 10 according to this embodiment. FIG. 5 shows the data processed by each unit or the timing signal of each unit in the time axis direction.

  In FIG. 5, a signal waveform indicated as “φrst” indicates an example of a reset signal that the reset unit 170 supplies to the first analog integrator 210 and the second analog integrator 220. For example, when the reset signal φrst is at a high potential, the first analog integrator 210 and the second analog integrator 220 are reset. Note that a period from when the reset signal φrst becomes a high potential until it becomes the next high potential may be defined as one conversion cycle. For example, in FIG. 5, a period from when the reset signal φrst indicated by n becomes a high potential until the reset signal φrst indicated by n + 1 becomes the next high potential is defined as one conversion cycle.

  In FIG. 5, signals indicated by “φs” and “φi” are examples of timing signals for operating a plurality of analog integrators. For example, the plurality of analog integrators sample a signal input at a timing when the signal φs is at a high potential, and transfer the charge sampled at a timing when the signal φi is at a high potential to the subsequent stage.

  In FIG. 5, signals indicated as “V1”, “V2”, and “V3” indicate examples of output voltages that are transferred to a subsequent stage by a plurality of analog integrators. For example, after the first analog integrator 210 is reset by the reset signal φrst, the voltage sampled in response to the signal φs becoming the first high potential is amplified by b1 times and then the voltage V1 (1 ). The first analog integrator 210 outputs the voltage V1 (1) in response to the signal φi having become the first high potential. As described above, the first analog integrator 210 determines that the signal φi has become the i-th high potential by using a voltage b1 times the voltage sampled in response to the signal φs having become the i-th high potential. In response, the voltage V1 (i) is output.

  The second analog integrator 220 amplifies the voltage V1 (1) sampled in response to the signal φs having become the second highest potential after being reset by the reset signal φrst by a factor of b2. Output as voltage V2 (1). The second analog integrator 220 outputs the voltage V2 (1) in response to the signal φi having the second highest potential. As described above, the second analog integrator 220 generates a voltage b2 times the voltage V1 (i−1) sampled in response to the signal φs being i + 1th high potential, and the signal φi is i + 1th high. In response to the potential, it is output as voltage V2 (i).

  Further, after the third analog integrator 230 is reset by the reset signal φrst, the voltage V2 (1) sampled in response to the signal φs becoming the third high potential is amplified by b3 times. Output as voltage V3 (1). The third analog integrator 230 outputs the voltage V3 (1) in response to the signal φi having the third highest potential. Here, since the third analog integrator 230 is not reset by the reset signal φrst, the residual component V3 (i) _n−1 in the previous conversion cycle is added to the voltage b3 · V2 (1) to obtain the voltage V3 (1). Output as.

  That is, the third analog integrator 230 amplifies the voltage V2 (i−1) sampled in response to the signal φs having become the (i + 2) th high potential by a factor of b3, and then the residual component V3 (i) _n. Add -1. Then, the third analog integrator 230 sets the voltage b3 · V2 (i−1) + V3 (i) _n−1 as the voltage V3 (i) in response to the signal φi becoming the i + 2th high potential. Output. The third analog integrator 230 holds the residual component in the current conversion cycle as V3 (i) _n.

  In this way, in the next conversion cycle, the third analog integrator 230 directly adds to the sampled voltage without converting the retained residual component into a smaller signal, so that the occurrence of errors can be reduced. . Further, the delta-sigma conversion unit 100 can output a calculation result similar to the feedback depending on the presence or absence of the reset signal without supplying a signal based on the residual component to the first analog integrator 210 in the first stage via the feedback path. Therefore, it is possible to adopt a configuration that is simple and reduces the generation of noise.

  In addition, although the 3rd analog integrator 230 demonstrated the example which adds the residual component of the last conversion cycle to the voltage sampled this time, it is not limited to this. The third analog integrator 230 may add the sampled voltage after performing an operation on the retained residue component. For example, the analog integrator at the final stage of the analog integration unit 130 amplifies the integral value held in one conversion cycle with a predetermined amplification degree and adds it to the integral value held in the next conversion cycle.

  As an example, when the incremental delta-sigma AD converter 10 samples and holds an input analog signal a plurality of times in one conversion cycle, the analog integrator in the final stage amplifies the residual component by the number of times of sample holding. As described above, the incremental delta-sigma AD converter 10 according to the present embodiment accurately considers the residual component of the integrator and adjusts the quantization error by adjusting the presence / absence of the reset signal and the amplification degree of the analog amplifier. Can be reduced.

  The incremental delta-sigma AD converter 10 according to the above-described embodiment may further include a feedforward circuit or the like. FIG. 6 shows a modification of the incremental delta-sigma AD converter 10 according to the present embodiment. FIG. 6 shows a configuration in which the incremental delta sigma AD converter 10 further includes a branching unit 112 and a feedforward unit 140.

  The branching unit 112 branches the transmission line that transmits the input analog signal, and inputs the branched one to the analog integrating unit 130. The branching unit 112 inputs the other branched part to the feedforward unit 140.

  The feedforward unit 140 transmits the input analog signal to the quantization unit 150. The feedforward unit 140 transmits the other input analog signal branched by the branching unit 112 to the quantization unit 150. When the analog integration unit 130 includes a plurality of analog integrators, the feedforward unit 140 may transmit a part of the integration results of the plurality of analog integrators to the quantization unit 150. Next, the feedforward unit 140 and the quantization unit 150 connected to the feedforward unit will be described.

FIG. 7 shows a configuration example of the feedforward unit 140 and the quantization unit 150 of the incremental delta-sigma AD converter 10 according to the present embodiment. The feedforward unit 140 transmits a differential signal based on the positive side signal AINP and the negative side signal AINN branched by the branching unit 112 to the quantization unit 150. The feedforward unit 140 includes a positive side capacitor C _sffp , a negative side capacitor C _sffn , a pre-stage switch 142, and a _post- stage switch 144.

The pre-stage switch 142 switches one terminal of the positive side capacitor C _sfp to either an input terminal to which the analog signal AINP is input or a reference potential in accordance with a control signal of the control unit 180. Further, the pre-stage switch 142 switches one terminal of the negative side capacitor C _sffn to either an input terminal to which the analog signal AINN is input or a reference potential in accordance with a control signal of the control unit 180.

For example, the front-stage switch 142 _connects one terminal of each of the positive-side capacitor C _sffp and the negative-side capacitor C _sffn to the input terminal at the timing when the signal φsff supplied by the control unit 180 is at a high potential. In this case, the pre-stage switch 142 disconnects each electrical connection between one terminal of the positive capacitor C _sffp and the negative capacitor C _sffn and the corresponding input terminal at the timing when the signal φsff is at a low potential. .

Further, the pre-stage switch 142 _connects one terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to the reference potential at the timing when the signal φiff supplied from the control unit 180 is high potential. In this case, the pre-stage switch 142 disconnects each electrical connection between one terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn and the reference potential at the timing when the signal φiff is at a low potential.

The _post- stage switch 144 switches the other terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to either the quantization unit 150 or the reference potential in accordance with the control signal of the control unit 180.

For example, the post-stage switch 144 _connects the other terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to the reference potential at the timing when the signal φsff is at the high potential, and at the timing when the signal φsff is at the low potential, Disconnect the electrical connection between the terminal and the reference potential. Further, the post-stage switch 144 connects, for example, the other terminals of the positive-side capacitor C _sffp and the negative-side capacitor C _sffn to the quantization unit 150 when the signal φiff is at a high potential, and the signal φsff is at a low potential. The electrical connection between the other terminal and the quantization unit 150 is cut off.

  As described above, the feedforward unit 140 repeats sampling and transfer of the input analog signal in accordance with the signal φsff and the signal φiff supplied from the control unit 180. Note that the control unit 180 may set the signal φiff to a low potential while the signal φsff is at a high potential and set the signal φiff to a high potential while the signal φsff is at a low potential, for example. That is, the feedforward unit 140 sets a period during which the signal φsff is high potential and the signal φiff is low potential as a sampling period, and sets a period when the signal φsff is low potential and the signal φiff is high potential as a transfer period. The signal φsff may be substantially the same signal as the signal φs shown in FIG. The signal φiff may be substantially the same signal as the signal φi shown in FIG.

  The quantization unit 150 includes a pre-stage circuit 152 and a quantizer 154. The pre-stage circuit 152 adds the signal supplied from the feedforward unit 140 and the signal supplied from the analog integration unit 130. The pre-stage circuit 152 includes a first circuit 250, a second circuit 260, a third circuit 270, and a fourth circuit 280.

First circuit 250 includes a switched capacitor and transmits analog signals AINP and AINN from feedforward unit 140 to quantizer 154. As an example, the switched capacitor of the first circuit 250 includes a first switch 252, a capacitor C _0ffp , and a capacitor C _0ffn .

For example, the first switch 252 switches one terminal of the capacitor C _0ffp to one of the input terminal to which the analog signal AINP is input and the reference potential in accordance with the control signal of the control unit 180. The other terminal of the capacitor C _0ffp is connected to the quantizer 154. As an example, the capacitor C _0ffp has one terminal connected to the input terminal at the first timing, and charges the analog input signal. The capacitor C _0ffp has one terminal connected to the reference potential at the second timing, and discharges the charged analog input signal to the quantizer 154.

Similarly, the first switch 252 switches one terminal of the capacitor C _0ffn to one of the input terminal to which the analog signal AINN is input and the reference potential in accordance with the control signal of the control unit 180. The capacitor C _0ffn has one terminal connected to the input terminal and charges the analog input signal at the first timing. The capacitor C _0ffn has one terminal connected to the reference potential at the second timing, and discharges the charged analog input signal to the quantizer 154.

  The second circuit 260, the third circuit 270, and the fourth circuit 280 each include a switched capacitor in substantially the same manner as the first circuit 250, and transmit an input signal to the quantizer 154. For example, the second circuit 260 transmits the analog output signals INT10P and INT10N of the first analog integrator 210 described in FIG. 2 to the quantizer 154. Further, the third circuit 270 may transmit the analog output signals INT20P and INT20N of the second analog integrator 220 described in FIG. 2 to the quantizer 154. Further, the fourth circuit 280 transmits the analog output signals INT30P and INT30N of the third analog integrator 230 described with reference to FIG. 2, that is, the output signal of the analog integrator 130, to the quantizer 154.

As an example, the second circuit 260 includes a second switch 262, a capacitor C _1ffp , and a capacitor C _1ffn . The second switch 262 is _connected to one terminal of the positive capacitor C _1ffp according to the control signal of the control unit 180, either the first output terminal from which the first analog integrator 210 outputs the signal INT10P or the reference potential. Switch to. The other terminal of the capacitor C _1ffp is connected to the quantizer 154. For example, the capacitor C _1ffp has one terminal connected to the output terminal and charges the signal INT10P at the first timing. Capacitor C _1ffp has one terminal connected to the reference potential at the second timing, and discharges the charged signal to quantizer 154.

Similarly, according to the control signal of the control unit 180, the second switch 262 is _connected to one terminal of the negative side capacitor C _1ffn , the second output terminal from which the first analog integrator 210 outputs the signal INT10N, and the reference potential. Switch to one of the following. _Further, the other terminal of the capacitor C _1ffn is connected to the quantizer 154. For example, the capacitor C _1ffn has one terminal connected to the output terminal and charges the signal INT10N at the first timing. Capacitor C _1ffn has one terminal connected to the reference potential at the second timing, and discharges the charged signal to quantizer 154.

For example, the third circuit 270 includes a third switch 272, a capacitor C _2ffp , and a capacitor C _2ffn . The third switch 272 is _connected to one terminal of the positive side capacitor C _2ffp according to the control signal of the control unit 180, either the first output terminal from which the second analog integrator 220 outputs the signal INT20P, or the reference potential. Switch to. _Further, the other terminal of the capacitor C _2ffp is connected to the quantizer 154. For example, the capacitor C _2ffp has one terminal connected to the output terminal and charges the signal INT20P at the first timing. Capacitor C _2ffp has one terminal connected to the reference potential at the second timing, and discharges the charged signal to quantizer 154.

Similarly, the third switch 272 is _connected to one terminal of the negative capacitor C _2ffn according to the control signal of the control unit 180, the second output terminal from which the second analog integrator 220 outputs the signal INT20N, and the reference potential. Switch to one of the following. The other terminal of the capacitor C _2ffn is connected to the quantizer 154. For example, the capacitor C _2ffn has one terminal connected to the output terminal and charges the signal INT20N at the first timing. The capacitor C _2ffn has one terminal connected to the reference potential at the second timing, and discharges the charged signal to the quantizer 154.

As an example, the fourth circuit 280 includes a fourth switch 282, a capacitor C _3ffp , and a capacitor C _3ffn . The fourth switch 282 is _connected to one terminal of the positive side capacitor C _3ffp according to the control signal of the control unit 180, either the first output terminal from which the third analog integrator 230 outputs the signal INT30P, or the reference potential. Switch to. The other terminal of the capacitor C _3ffp is connected to the quantizer 154. For example, the capacitor C _3ffp has one terminal connected to the output terminal and charges the signal INT30P at the first timing. Capacitor C _3ffp has one terminal connected to the reference potential at the second timing, and discharges the charged signal to quantizer 154.

Similarly, the fourth switch 282 is _connected to one terminal of the negative capacitor C _3ffn according to the control signal of the controller 180, the second output terminal from which the third analog integrator 230 outputs the signal INT30N, and the reference potential. Switch to one of the following. The other terminal of the capacitor C _3ffn is connected to the quantizer 154. For example, the capacitor C _3ffn has one terminal connected to the output terminal and charges the signal INT30N at the first timing. Then, at the second timing, one terminal of the capacitor C _3ffn is connected to the reference potential, and the charged signal is discharged to the quantizer 154.

  The quantizer 154 quantizes the signal supplied from the pre-stage circuit 152. The quantizer 154 may be a 1-bit quantizer or a multi-bit quantizer.

  As an example, the controller 180 charges the first circuit 250, the second circuit 260, the third circuit 270, and the fourth circuit 280 with a timing when the signal φi is at a high potential, and the signal φs is high. The discharge operation is executed at the timing of the potential. As described above, the feedforward unit 140 and the quantizer 154 convert the signal input to the incremental delta-sigma AD converter 10 and the signal output from the analog integrator included in the analog integration unit 130 into the feedforward signal. To the quantizer 154. With such a feedforward signal, the digital code output by the quantizer 154 for each clock can be made to reflect the analog input signal at a higher speed.

  Note that the second circuit 260 and the third circuit 270 may transmit a signal input via the feedforward unit 140 to the quantizer 154 as in the example of the first circuit 250. Instead, the first circuit 250 may transmit an input signal to the quantizer 154 without using the feedforward unit 140 as in the second circuit 260 and the third circuit 270.

  FIG. 7 shows an example in which a plurality of signals are feedforward signals, but the present invention is not limited to this. At least one of the input analog signal and the signal output from the analog integrator included in the analog integrator 130 may be transmitted to the quantizer 154 as a feedforward signal.

  The incremental delta-sigma AD converter 10 according to this embodiment may further include a sample hold circuit and the like. FIG. 8 shows a configuration example of the sample hold unit 110 and the DA conversion unit 160 according to the present embodiment. FIG. 8 shows an example of a feedforward circuit provided in the preceding stage of the incremental type delta sigma AD converter 10. Further, the DA conversion unit 160 illustrated in FIG. 8 illustrates a more detailed configuration example of the DA conversion unit 160 illustrated in FIG. FIG. 8 shows an example in which a differential signal is input to the sample hold unit 110.

The sample hold unit 110 includes one or a plurality of switched capacitors, and samples the input signals AINP and AINN input to the incremental delta sigma AD converter 10. The sample hold unit 110 may include a number of switched capacitors that is substantially the same as the oversampling ratio N. The plurality of switched capacitors have a capacitor C _s1pj , a capacitor C _s1nj, and a changeover switch at the front stage and the rear stage of each capacitor. Note that j is a natural number from 1 to m, and m is substantially the same value as the oversampling ratio N.

The switch in the _previous stage of the capacitor C _s1pj switches one terminal of the capacitor C _s1pj to either the input terminal to which the analog signal AINP is input or the reference potential. The switch at the _subsequent stage of the capacitor C _s1pj switches the other terminal of the capacitor C _s1pj to either the reference potential or the addition unit 120. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

Similarly, the switch in the _previous stage of the capacitor C _s1nj switches one terminal of the capacitor C _s1nj to either the input terminal to which the analog signal AINN is input or the reference potential. _Further , the switch at the _subsequent stage of the capacitor C _s1nj switches the other terminal of the capacitor C _s1nj to either the reference potential or the addition unit 120.

The control unit 180 controls each of the plurality of switched capacitors of the sample hold unit 110 by supplying a signal φt. For example, at the first timing (for example, the signal φt is a high potential), the control unit 180 connects one terminal of the capacitor C _s1pj to the input terminal AINP and connects the other terminal to the reference potential. Charge the analog input signal. In this case, at the first timing, the control unit 180 _connects one terminal of the capacitor C _s1nj to the input terminal AINN and connects the other terminal to the reference potential to charge the negative analog input signal.

  In the present embodiment, such a first timing is set as a tracking period. That is, the control unit 180 charges the input signals to the plurality of switched capacitors in a predetermined tracking cycle.

Further, the control unit 180 connects one terminal to the reference potential at the timing when the jth capacitor C _s1nj is shifted to the jth from the tracking cycle (the signal φij is a high potential), and the other terminal is connected to the adding unit 120. And the charged positive-side analog input signal is sequentially discharged to the analog integrator 130. Similarly, the control unit 180 connects the j-th capacitor C _s1pj to the reference potential at the timing shifted from the first timing to the j-th timing, and connects the other terminal to the adding unit 120 to charge. The negative analog input signals thus discharged are sequentially discharged to the analog integrator 130.

  In the present embodiment, the timing at which the control unit 180 discharges the plurality of switched capacitors in this way is defined as a conversion cycle. That is, the control unit 180 sequentially transfers the charges charged in the plurality of switched capacitors in a predetermined conversion cycle to the analog integration unit 130. Here, one conversion cycle (first period) is the sum of the tracking period and the conversion period.

  Further, the plurality of switched capacitors may perform N samplings and output N sampling results in the first period. The sample hold unit 110 may include the same number of switched capacitors as the oversampling ratio N that is the ratio of the number of samplings to the first period. In this case, the N switched capacitors may be sequentially executed so that the charge transfer operation to the analog integration unit 130 is completed within the conversion period. Note that the number N of switched capacitors may be the same as the number j of digital signals output from the quantization unit 150 in one conversion cycle.

  For example, the control unit 180 charges a plurality of switched capacitors with an analog input signal in the first clock, and supplies the charged analog input signal to the analog integration unit 130 according to a corresponding clock signal after the first clock. And discharge sequentially. As a result, the sample hold unit 110 sequentially supplies substantially the same analog value sampled by each of the plurality of switched capacitors in the first clock to the delta sigma conversion unit 100 as an input analog signal after the first clock. it can. That is, even if the analog signal changes at high speed, the sample hold unit 110 can hold the value of one timing and convert it to a digital value.

The DA converter 160 includes a first reference voltage REFP, a second reference voltage REFN, a capacitor C _fbp , a capacitor C _fbn , a first switch unit 162, a second switch unit 164, and a third switch unit 166. Have. The first reference voltage REFP and the second reference voltage REFN output voltages having substantially the same absolute voltage values and opposite polarities. As an example, the first reference voltage REFP outputs a positive voltage, and the second reference voltage REFN outputs a negative voltage.

The first switch unit 162 switches one terminal of the capacitor C _fbp to either the first reference voltage REFP or the reference potential. The first switch unit 162 switches one terminal of the capacitor C _fbn to either the second reference voltage REFN or the reference potential. For example, the signal φs supplies control unit 180 is in the timing of the high-potential, one terminal of the capacitor _{C fbp} connected to a first reference voltage REFP, one terminal of the capacitor _{C fbn} connected to the second reference voltage REFN . In this case, the timing of the control unit 180 is signal φi is high potential supplied, one terminal of one terminal and the capacitor C _fbn capacitor C _fbp, connected to a reference potential.

The second switch unit 164 switches whether to connect the other terminal of the capacitor C _fbp and the capacitor C _fbn to the reference potential. For example, the second switch unit 164 _connects the other terminal of the capacitor C _fbp and the capacitor C _fbn to the reference potential at the timing when the signal φs is at the high potential, and the other terminal at the timing when the signal φi is at the high potential. Disconnect the reference potential electrical connection. The control unit 180 controls the first switch unit 162 and the second switch unit 164 to _connect the capacitor C _fbp and the capacitor C _fbn to the corresponding reference voltage at the timing when the signal φs is at the high potential. And charge corresponding to the capacity of the capacitor is charged.

The third switch unit 166 switches whether to connect the other terminal of the capacitor C _fbp and the capacitor C _fbn to the adder unit 120. For example, the third switch unit 166 _connects the other terminal of the capacitor C _fbp and the capacitor C _fbn to the adding unit 120 at the timing when the signal φi is at a high potential, and the other terminal at the timing when the signal φs is at a high potential. And the electrical connection of the adder 120 is cut off. The control unit 180 controls the third switch unit 166 to supply the charges charged in the capacitor C _fbp and the capacitor C _fbn to the adding unit 120 according to the first reference voltage REFP and the second reference voltage REFN, respectively. .

The third switch unit 166 switches the connection destination of the other terminals of the capacitor C _fbp and the capacitor C _fbn according to the digital signal Y supplied from the quantization unit 150. Here, the adder 120, which is the connection destination of the capacitor C _fbp and the capacitor C _fbn , corresponds to the differential signal received from the sample hold unit 110, and provides feedback signals to the positive signal and the negative signal of the differential signal, respectively. Have a path for transmitting

For example, when the digital code of the digital signal Y is “0”, the third switch unit 166 _adds the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the positive signal of the differential signal. Switch the connection as follows. In this case, the third switch unit 166 switches the connection so that the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn is added to the negative signal of the differential signal. As an example, when the signal φip becomes a high potential according to the digital code of “0”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the positive signal at the timing. The other terminal of the capacitor C _fbn is connected to the negative signal transmission line.

For example, when the digital code of the digital signal Y is “1”, the third switch unit 166 _converts the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the negative signal of the differential signal. Switch the connection to add. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the positive signal of the differential signal. As an example, when the signal φin becomes a high potential according to the digital code “1”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the negative signal at the timing. The other terminal of the capacitor C _fbn is connected to the transmission line of the positive signal.

  As described above, the DA conversion unit 160 outputs an analog signal corresponding to the positive reference voltage to the addition unit 120 as a feedback signal in accordance with the digital signal “0” output from the quantization unit 150, and the feedback signal is output to the addition unit 120. Add to the differential signal. Further, the DA conversion unit 160 outputs an analog signal corresponding to the negative reference voltage to the adding unit 120 as a feedback signal according to the digital signal “1” output from the quantization unit 150, and the feedback signal is differentially output. Add to signal.

  As described above, the control unit 180 controls the sample hold unit 110 and the DA conversion unit 160 to superimpose the feedback signal for adding or subtracting the reference voltage on the input analog signal, and supplies it to the analog integration unit 130. . In FIG. 8, the positive signal supplied from the adder 120 to the analog integrator 130 is SP, and the negative signal is SN. As described above, the incremental delta-sigma AD converter 10 includes the sample-and-hold unit 110, so that a high-speed analog signal or the like can be sampled and converted into a digital signal.

  As shown in FIG. 8, when the sample and hold unit 110 includes a plurality of capacitors, the feedforward unit 140 and the first circuit 250 include a plurality of capacitors corresponding to the plurality of capacitors of the sample and hold unit 110. It's okay. For example, the feedforward unit 140 and the first circuit 250 may include the same number of switched capacitors as the oversampling ratio N. Then, in response to the plurality of capacitors of the sample and hold unit 110 being sequentially discharged according to the clock signal, the feed forward unit 140 and the corresponding switched capacitor of the first circuit 250 sequentially perform charging and discharging, and analog The input signal may be transmitted to the quantizer 154.

  The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. The blocks in the flowcharts and block diagrams may be expressed as (1) the stage of the process in which the operation is performed or (2) the “part” of the device responsible for performing the operation. Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor.

  Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor. Note that the dedicated circuit may include a digital and / or analog hardware circuit, and may include an integrated circuit (IC) and / or a discrete circuit. Programmable circuits may be logical products, logical sums, exclusive logical sums, negative logical products, negative logical sums, and other logical operations, such as field programmable gate arrays (FPGAs) and programmable logic arrays (PLA), for example. , Flip-flops, registers, and memory elements, including reconfigurable hardware circuitry.

  The computer readable storage medium may include any tangible device that can store instructions executed by a suitable device. Thereby, a computer readable storage medium having instructions stored on the tangible device comprises a product including instructions that can be executed to create a means for performing the operations specified in the flowchart or block diagram. become.

  Examples of computer readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of the computer-readable storage medium include a floppy disk, diskette, hard disk, random access memory (RAM), read only memory (ROM), and erasable programmable read only memory (EPROM or flash memory). Electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (registered trademark) disc, memory stick Integrated circuit cards and the like may be included.

  Computer readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, and the like. Computer-readable instructions also include object-oriented programming languages such as Smalltalk, JAVA, C ++, etc., and conventional procedural programming languages such as the “C” programming language or similar programming languages, or It may include source code or object code written in any combination of multiple programming languages.

  The computer readable instructions may be a processor of a general purpose computer, special purpose computer, or other programmable data processing device, either locally or via a wide area network (WAN) such as a local area network (LAN), the Internet, etc. Or it may be provided in a programmable circuit. This allows a general purpose computer, special purpose computer, or other programmable data processing device processor, or programmable circuit to generate means for performing the operations specified in the flowchart or block diagram, Computer readable instructions can be executed. Note that examples of the processor include a computer processor, a processing unit, a microprocessor, a digital signal processor, a controller, a microcontroller, and the like.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 Incremental Delta Sigma AD Converter, 12 Input Terminals, 14 Output Terminals, 100 Delta Sigma Conversion Unit, 110 Sample Hold Unit, 112 Branch Unit, 120 Adder Unit, 130 Analog Integration Unit, 140 Feed Forward Unit, 142 Pre-stage Switch, 144 Post-stage switch, 150 Quantizer, 152 Pre-stage circuit, 154 Quantizer, 160 DA converter, 162 First switch section, 164 Second switch section, 166 Third switch section, 170 Reset section, 180 Control section, 190 Digital filter unit, 210 first analog integrator, 212 first analog amplifier, 214 positive reset switch, 216 negative reset switch, 220 second analog integrator, 222 second analog amplifier, 224 positive reset switch, 226 Negative side reset switch, 230 Third analog integrator, 232 Third analog amplifier, 234 Positive side reset switch, 236 Negative side reset switch, 240 First switched capacitor, 242 Front stage switch, 244 Rear stage switch, 245 Second switched capacitor, 246 Pre-stage switch, 248 Post-stage switch, 250 1st circuit, 252 1st switch, 260 2nd circuit, 262 2nd switch, 270 3rd circuit, 272 3rd switch, 280 4th circuit, 282 4th switch, 310 Gain Adjustment unit, 320 delay element

Claims (11)

A delta-sigma converter that outputs a modulated digital signal obtained by delta-sigma modulation of an input analog signal;
A digital filter section for filtering the modulated digital signal;
With
The delta-sigma converter is
An analog integrator having a plurality of cascaded analog integrators and integrating a signal based on an input analog signal;
Of the plurality of analog integrators, the integration value held by the last-stage analog integrator is not reset and the remaining analog integrators excluding the last-stage analog integrator hold each predetermined period. An incremental delta-sigma AD converter having a reset unit for resetting an integral value. The reset unit supplies a reset signal for resetting an integration value to an analog integrator other than the final-stage analog integrator for each conversion cycle of the incremental delta-sigma AD converter.
2. The incremental delta-sigma AD converter according to claim 1, wherein the last-stage analog integrator of the analog integration unit adds the integration value held in one conversion cycle to the integration value held in the next conversion cycle. .   The final stage analog integrator of the analog integration unit amplifies the integral value held in one conversion cycle with a predetermined amplification degree, and adds it to the integral value held in the next conversion cycle. An incremental delta-sigma AD converter as described in 1. The delta-sigma converter is
A quantization unit for quantizing the output signal of the analog integration unit;
A DA converter that generates a feedback signal based on the output of the quantizer;
An adder for adding the feedback signal from the DA converter to the input analog signal;
Have
The incremental delta-sigma AD converter according to any one of claims 1 to 3, wherein the analog integration unit integrates an output of the addition unit. The analog integrator includes a first analog integrator, a second analog integrator, and a third analog integrator connected in cascade,
The reset unit supplies a reset signal that causes the first analog integrator and the second analog integrator to reset an integrated value every conversion cycle;
5. The incremental delta-sigma AD according to claim 4, wherein the third analog integrator outputs the integration value held in one conversion cycle to the quantization unit in addition to the integration value held in the next conversion cycle. converter.   The incremental delta-sigma AD converter according to claim 4 or 5, wherein the delta-sigma conversion unit includes a feedforward unit that transmits the input analog signal to the quantization unit.   The incremental delta-sigma AD converter according to claim 6, wherein the feedforward unit transmits a part of integration results of the plurality of analog integrators to the quantization unit.   The incremental delta-sigma AD converter according to claim 4, wherein the quantization unit quantizes the output signal of the analog integration unit into a binary or multilevel digital signal.   The incremental delta-sigma AD converter according to any one of claims 1 to 8, wherein the reset unit resets the digital filter unit at a timing of resetting the analog integration unit. A sample-and-hold unit that has one or a plurality of switched capacitors and samples an input signal;
The incremental delta-sigma according to any one of claims 1 to 9, wherein the sample-and-hold unit sequentially supplies values sampled by the one or more switched capacitors to the delta-sigma conversion unit as input analog signals. AD converter. Outputting a modulated digital signal obtained by delta-sigma modulating the input analog signal;
Filtering the modulated digital signal;
With
Outputting the modulated digital signal comprises:
Integrating a signal based on an input analog signal using a plurality of cascaded analog integrators;
Of the plurality of analog integrators, the integration value held by the last-stage analog integrator is not reset and the remaining analog integrators excluding the last-stage analog integrator hold each predetermined period. Resetting the integral value;
An AD conversion method comprising:

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