JP2018198408A - Incremental type delta sigma AD converter and AD conversion method - Google Patents

Abstract

To provide an incremental type Delta Sigma AD converter for converting a wide-band input analog signal into a digital signal.SOLUTION: An incremental type Delta Sigma AD converter and an AD conversion method are provided. The incremental type Delta Sigma AD converter comprises an analog integrator having an analog integration unit for integrating an input analog signal, a quantization unit for quantizing a signal based on an output signal of the analog integration unit, a feedforward unit for forwarding the input analog signal to the quantization unit, and a DA conversion unit for performing DA conversion of an output of the quantization unit to produce a feedback signal. The analog integration unit has: a plurality of switched capacitor units which sample the input analog signal in different periods, and transmit the samples in different periods; and an adder unit which adds a feedback signal from the DA conversion unit to the input analog signal transmitted by each switched capacitor unit.SELECTED DRAWING: Figure 4

Description

  The present invention relates to an incremental delta-sigma AD converter and an AD conversion method.

2. Description of the Related Art Conventionally, an incremental delta-sigma AD converter that has an integration circuit and converts an analog signal into a digital signal and resets charges accumulated in the integration circuit at a predetermined time interval has been known. (For example, refer to Patent Document 1).
Patent Document 1 International Publication No. 2013/136676

  Such an incremental type delta-sigma AD converter may convert an input analog signal into a digital signal via a sample and hold circuit for the purpose of widening the bandwidth. Incremental delta-sigma AD converters that do not use a sample-and-hold circuit cannot accurately perform AD conversion when the amplitude value of the input analog signal becomes high enough to fluctuate during one tracking hold period. It is because it may end up. That is, there has been a demand for an incremental delta-sigma AD converter that can realize a wide band without using a sample hold circuit.

  In the first aspect of the present invention, the analog integrator includes an analog integrator, integrates an input analog signal, a quantization unit that quantizes a signal based on the output signal of the analog integrator, and an input analog signal A feedforward unit that transmits to the quantization unit, and a DA conversion unit that DA-converts the output of the quantization unit to generate a feedback signal, and the analog integration unit samples the input analog signal in different periods, Incremental delta-sigma AD converter and AD conversion method having a plurality of switched capacitor units that are transferred in different periods, and an adder unit that adds a feedback signal from a DA converter to an input analog signal transferred by the switched capacitor unit I will provide a.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 shows a configuration example of an incremental delta-sigma AD converter 10 according to the present embodiment. An example of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 is shown. An example of a timing chart of the incremental delta-sigma AD converter 10 shown in FIGS. 1 and 2 is shown. The structural example of the analog integration part 130 of the incremental type delta-sigma AD converter 10 which concerns on this embodiment, the feedforward part 140, and the DA conversion part 160 is shown. An example of the timing chart of the incremental type delta-sigma AD converter 10 concerning this embodiment is shown. The 1st modification of the analog integration part 130 of the incremental type delta-sigma AD converter 10 which concerns on this embodiment, the feedforward part 140, and the DA conversion part 160 is shown. An example of the timing chart of the incremental type delta-sigma AD converter 10 which concerns on a 1st modification is shown. 2 shows a configuration example of the feedforward unit 140 and the quantization unit 150 of the incremental delta-sigma AD converter 10 according to the present embodiment. The 2nd modification of the analog integration part 130 of the incremental type delta-sigma AD converter 10 which concerns on this embodiment, the feedforward part 140, and the DA conversion part 160 is shown. An example of the timing chart of the incremental type delta-sigma AD converter 10 which concerns on a 2nd modification is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

FIG. 1 shows a configuration example of an incremental delta-sigma AD converter 10 according to the present embodiment. The incremental type delta sigma AD converter 10 converts the analog signal A _in inputted from the input terminal 12 into a digital signal D _out and outputs it from the output terminal 14 while resetting an internal circuit. The incremental delta sigma AD converter 10 includes an input terminal 12, an output terminal 14, a delta sigma conversion unit 100, and a digital filter unit 190.

Input terminal 12 receives an input analog signal _{A in.} The input terminal 12 may be a single-ended input, or may be a differential input instead. When the input terminal 12 is a differential input, the input terminal 12 receives a positive signal A _inp from a positive input and a negative signal A _inn from a negative input. The input terminal 12 supplies the input signal A _in to the delta sigma conversion unit 100.

The output terminal 14 outputs the digital signal D _OUT converted by the incremental delta sigma AD converter 10 _in accordance with the input analog signal A _in . The output terminal 14 may be a single-ended output, or may be a differential output instead.

Delta sigma modulation section 100 outputs a modulated digital signal Y to the input analog signal A _in the delta-sigma modulation. The delta sigma conversion unit 100 includes a branching unit 110, an analog integration unit 130, a feedforward unit 140, a quantization unit 150, a DA conversion unit 160, a reset unit 170, and a control unit 180.

  The branching unit 110 branches the transmission line that transmits the input analog signal, and inputs the branched one to the analog integrating unit 130. The branching unit 110 inputs the other branched part to the feedforward unit 140.

The analog integrator 130 outputs an integrated analog signal according to the input analog signal. The analog integrator 130 has an analog integrator and integrates an input analog signal. The analog integrator 130 may include one or a plurality of analog integrators connected in cascade. The analog integration unit 130 supplies the result of integration to the quantization unit 150 as an output signal _Aerr .

  The feedforward unit 140 transmits the input analog signal to the quantization unit 150. The feedforward unit 140 transmits the other input analog signal branched by the branching unit 110 to the quantization unit 150. When the analog integration unit 130 includes a plurality of analog integrators, the feedforward unit 140 may transmit a part of the integration results of the plurality of analog integrators to the quantization unit 150.

  The quantization unit 150 quantizes a signal based on the output signal of the analog integration unit 130. For example, the quantization unit 150 quantizes a signal obtained by adding the input analog signal transmitted by the feedforward unit 140 to the output signal of the analog integration unit 130. The quantization unit 150 quantizes the integration result of the analog integration unit 130 according to a clock signal or the like supplied from the outside, and outputs a bit stream corresponding to the integration result. The quantizer 150 may include a quantizer that functions as a 1-bit quantizer or a multi-bit quantizer. That is, the quantization unit 150 may quantize the output signal of the analog integration unit 130 into a binary or multilevel digital signal.

For example, when the quantization unit 150 includes a 1-bit quantizer, the bit stream is a sequence (serial digital code) of a predetermined number of 1-bit data (digital code), and a value obtained by integrating the digital code. There becomes a digital value proportional or substantially equal to the amplitude value of the input signal a _in. The quantization unit 150 compares the output signal of the analog integration unit 130 with a predetermined threshold value for each clock signal, and converts the output signal into a 1 or 0 digital code depending on whether the threshold value is exceeded. May be converted.

For example, when an M-bit quantizer is used as the quantization unit 150, the bit stream is a sequence (serial digital code) of a predetermined number of M-bit data (digital code). cumulative value becomes a digital value proportional or substantially equal to the amplitude value of the input signal a _in. For each clock signal, the quantization unit 150 compares the output signal with a predetermined M-bit threshold by a comparator for M bits, and outputs the output depending on whether each comparator exceeds the threshold. The signal may be converted to an M-bit digital code.

That is, the incremental type delta-sigma AD converter 10 converts the input signal A _in to a digital value every fixed conversion cycle, but the quantization unit 150 has an externally supplied clock signal that is faster than one conversion cycle. depending on the like, and outputs a serial digital code corresponding to the input signal a _in. In this way, the input signal A _in is converted into a digital value for each of a plurality of samples synchronized with the clock signal, and the number of samples for one conversion cycle is set as the oversampling ratio. That is, the number of digital codes included in the serial digital code is equal to the oversampling ratio.

  For example, when the oversampling ratio of the incremental delta-sigma AD converter 10 is 60, the quantization unit 150 outputs a serial digital code including 60 digital codes every conversion cycle. The quantization unit 150 supplies the quantized digital signal Y to the DA conversion unit 160 and the digital filter unit 190 as a modulated digital signal.

  The DA conversion unit 160 generates a feedback signal based on the output of the quantization unit 150. The DA conversion unit 160 DA-converts the digital signal Y output from the quantization unit 150 into a corresponding analog signal, and supplies the converted analog signal to the analog integration unit 130 as a feedback signal. The feedback signal may be a predetermined reference voltage. The feedback signal will be described later. The DA converter 160 may convert the digital signal Y into an analog signal in synchronization with the clock signal.

The reset unit 170 resets the integration value held by the analog integration unit 130 every predetermined period. In addition, the reset unit 170 may reset the digital filter unit 190 at the timing when the analog integration unit 130 is reset. The reset unit 170 may reset the analog integration unit 130 and the digital filter unit 190 every time the incremental delta sigma AD converter 10 converts the input signal _Ain into a digital value. For example, the reset unit 170 resets the analog integration unit 130 and the digital filter unit 190 by supplying a reset signal for each conversion cycle to a digital value.

  The control unit 180 controls the operation of the delta sigma conversion unit 100. The control unit 180 controls the operations of the analog integration unit 130 and the DA conversion unit 160, for example. In addition, the control unit 180 may control the feedforward unit 140 and the quantization unit 150. The control unit 180 may control the digital filter unit 190. The control unit 180 may execute the control operation of the delta-sigma conversion unit 100 according to a clock signal or the like supplied from the inside or the outside. The control unit 180 may include a clock oscillator and execute control operations of the respective units.

  The digital filter unit 190 filters the modulated digital signal Y output from the quantization unit 150. The digital filter unit 190 may be an integration filter that integrates the bit stream of the digital signal Y and performs digital integration. In this case, the digital filter unit 190 may calculate a digital value by multiplying the integrated value by a predetermined coefficient. The digital filter unit 190 may calculate a digital value in synchronization with the clock signal. Further, the digital filter unit 190 may reset the integrated amount in response to receiving the reset signal from the reset unit 170.

Further, the digital filter unit 190 may have a low-pass filter and reduce quantization noise generated in the quantization unit 150. The digital filter unit 190 may have a decimation filter to reduce the sampling frequency. The digital filter unit 190 supplies the digital value of the calculation result to the output terminal 14. The output terminal 14 outputs the received digital value as the digital output D _OUT of the incremental delta sigma AD converter 10. The digital filter unit 190 may output a filtered digital signal at predetermined intervals.

As described above, the incremental delta-sigma AD converter 10 according to the present embodiment performs the reset of the analog integration unit 130 and the digital filter unit 190 by the reset unit 170 and the conversion of the input signal A _{in to} the digital output. Repeat in synchronization with the clock signal. Note that the incremental type delta sigma AD converter 10 may operate as a delta sigma AD converter as long as there is no reset operation by the reset unit 170.

  FIG. 2 shows an example of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160. FIG. 2 illustrates an example in which a differential signal based on the positive side signal AINP and the negative side signal AINN is input to the analog integration unit 130 as an input analog signal. The analog integration unit 130 includes an addition unit 120, an analog integrator 210, and a first switched capacitor unit 310.

Addition unit 120 is provided between the first switched capacitor 310 and an analog integrator 210 adds the feedback signal from the DA conversion unit 160 to the input signal _{A in} which input from the input terminal 12. That is, the adder 120 adds the feedback signal from the DA converter 160 to the input analog signal transferred by the first switched capacitor unit 310. When the input terminal 12 is a differential input, the adder 120 may add feedback signals having different signs to the positive signal AINP and the negative signal AINN of the differential signal. The addition unit 120 supplies the addition result to the analog integrator 210.

FIG. 2 shows an example in which the analog integrator 210 has two input terminals and two output terminals, and inputs a differential signal and outputs a differential signal. One of the two input terminals of the analog integrator 210 is a first input terminal, and the other is a second input terminal. The analog integrator 210 includes an analog amplifier 212, a positive feedback capacitor C _i1p , a negative feedback capacitor C _i1n , a positive reset switch 214, and a negative reset switch 216.

  The analog amplifier 212 amplifies and outputs signals input to the positive input terminal and the negative input terminal. The analog amplifier 212 is, for example, a differential input type amplifier circuit. In addition, the analog amplifier 212 may be a single-ended output, and may instead be a differential output. The analog amplifier 212 is an OP amplifier as an example. FIG. 2 shows an example in which the analog amplifier 212 is a differential input and differential output analog amplifier. In FIG. 2, the positive input terminal of the analog amplifier 212 is connected to the first input terminal of the analog integrator 210, and the negative input terminal is connected to the second input terminal.

Each of the feedback capacitors repeats charge and discharge according to the input signal. The feedback capacitor switches between charging and discharging every sampling, for example. As an example, the positive feedback capacitor C _i1p discharges the charge charged in the first clock to the quantization unit 150 in the next second clock in response to the positive signal AINP, and in the next third clock, Charging the charge. Similarly, the negative feedback capacitor C _i1n discharges the electric charge charged in the first clock to the quantization unit 150 in the next second clock in response to the negative signal AINN, and the next in the next third clock. Charging the charge.

  In response to an instruction from the reset unit 170, the reset switch discharges the electric charge accumulated in the feedback capacitor and resets the analog integrators. For example, the reset switch connects between terminals of the feedback capacitor in accordance with a reset signal supplied from the reset unit 170 and discharges the accumulated charge. FIG. 2 shows an example in which the reset unit 170 resets the analog integrator 210 by switching the positive side reset switch 214 and the negative side reset switch 216 to the ON state.

The first switched capacitor unit 310 is provided in the preceding stage of the adding unit 120 and transmits the electric charge accumulated in the analog integrator 210 connected in the subsequent stage. The first switched capacitor unit 310 includes a positive side capacitor C _sp , a negative side capacitor C _sn , a pre-stage switch 312, and a post-stage switch 314.

Primary switch 312, in response to the control signal of the control unit 180, switches the one terminal of the positive-side capacitor C _sp, to one of input terminals and a reference potential analog signal AINP inputs. Further, the pre-stage switch 312 switches one terminal of the negative side capacitor C _sn to either the input terminal to which the analog signal AINN is input or the reference potential in accordance with the control signal of the control unit 180. Here, the reference potential may be a predetermined potential, and is 0 V as an example.

Primary switch 312, for example, signals φs and supplies the control unit 180 is in the timing of the high-potential, connects the one terminal of the positive-side capacitor C _sp and negative capacitor C _sn, each input terminal. In this case, the pre-stage switch 312 disconnects each electrical connection between one terminal of the positive capacitor C _sp and the negative capacitor C _sn and the corresponding input terminal at the timing when the signal φs is at a low potential. .

Further, primary switch 312, the signal φi supplies control unit 180 is in the timing of the high-potential, one terminal of the positive side capacitor C _sp and negative capacitor C _sn, respectively connected to a reference potential. In this case, the pre-stage switch 312 disconnects each electrical connection between one terminal of the positive capacitor C _sp and the negative capacitor C _sn and the reference potential at the timing when the signal φi is at a low potential.

Secondary switch 314, in response to the control signal of the control unit 180, the other terminal of the positive side capacitor C _sp and negative capacitor C _sn, switches respectively to one of the addition unit 120 and a reference potential.

For example, the post-stage switch 314 connects the other terminal of the positive capacitor C _sp and the negative capacitor C _sn to the reference potential at the timing when the signal φs is at the high potential, and the other switch 314 at the timing when the signal φs is at the low potential. Disconnect the electrical connection between the terminal and the reference potential. Further, the post-stage switch 314 connects, for example, the other terminal of the positive capacitor C _sp and the negative capacitor C _sn to the adder 120 at the timing when the signal φi is at a high potential, and at the timing when the signal φs is at a low potential. The electrical connection between the other terminal and the adding unit 120 is cut off.

  As described above, the first switched capacitor unit 310 repeats sampling and transfer of the input analog signal according to the signal φs and the signal φi supplied from the control unit 180. Note that the control unit 180 may set the signal φi to a low potential while the signal φs is at a high potential, and set the signal φi to a high potential while the signal φs is at a low potential. That is, the first switched capacitor unit 310 uses a period during which a high potential signal φs and a low potential signal φi are supplied as a sampling period, and a period during which a low potential signal φs and a high potential signal φi are supplied as a transfer period. And

The DA converter 160 includes a first reference voltage REFP, a second reference voltage REFN, a capacitor C _fbp , a capacitor C _fbn , a first switch unit 162, a second switch unit 164, and a third switch unit 166. Have. The first reference voltage REFP and the second reference voltage REFN output voltages having substantially the same absolute voltage values and opposite polarities. As an example, the first reference voltage REFP outputs a positive voltage, and the second reference voltage REFN outputs a negative voltage.

The first switch unit 162 switches one terminal of the capacitor C _fbp to either the first reference voltage REFP or the reference potential. The first switch unit 162 switches one terminal of the capacitor C _fbn to either the second reference voltage REFN or the reference potential. For example, the signal φs supplies control unit 180 is in the timing of the high-potential, one terminal of the capacitor _{C fbp} connected to a first reference voltage REFP, one terminal of the capacitor _{C fbn} connected to the second reference voltage REFN . In this case, the timing of the control unit 180 is signal φi is high potential supplied, one terminal of one terminal and the capacitor C _fbn capacitor C _fbp, connected to a reference potential.

The second switch unit 164 switches whether to connect the other terminal of the capacitor C _fbp and the capacitor C _fbn to the reference potential. For example, when the signal φs is at a high potential, the second switch unit 164 _connects the other terminal of the capacitor C _fbp and the capacitor C _{fbn to} the reference potential, and when the signal φi is at a high potential, Disconnect the reference potential electrical connection. The control unit 180 controls the first switch unit 162 and the second switch unit 164 to _connect the capacitor C _fbp and the capacitor C _fbn to the corresponding reference voltage at the timing when the signal φs is at the high potential. And charge corresponding to the capacity of the capacitor is charged.

The third switch unit 166 switches whether to connect the other terminal of the capacitor C _fbp and the capacitor C _fbn to the adder unit 120. For example, the third switch unit 166 _connects the other terminal of the capacitor C _fbp and the capacitor C _fbn to the adding unit 120 at the timing when the signal φi is at a high potential, and the other terminal at the timing when the signal φs is at a high potential. And the electrical connection of the adder 120 is cut off. The control unit 180 controls the third switch unit 166 to supply the charges charged in the capacitor C _fbp and the capacitor C _fbn to the adding unit 120 according to the first reference voltage REFP and the second reference voltage REFN, respectively. .

The third switch unit 166 switches the connection destination of the other terminals of the capacitor C _fbp and the capacitor C _fbn according to the digital signal Y supplied from the quantization unit 150. Here, the addition unit 120, which is the connection destination of the capacitor C _fbp and the capacitor C _fbn , corresponds to the differential signal received from the first switched capacitor unit 310, respectively to the positive side signal and the negative side signal of the differential signal. A path for transmitting the feedback signal;

For example, when the digital code of the digital signal Y is “0”, the third switch unit 166 _adds the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the positive signal of the differential signal. Switch the connection as follows. In this case, the third switch unit 166 switches the connection so that the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn is added to the negative signal of the differential signal. As an example, when the signal φip becomes a high potential according to the digital code of “0”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the positive signal at the timing. The other terminal of the capacitor C _fbn is connected to the negative signal transmission line.

For example, when the digital code of the digital signal Y is “1”, the third switch unit 166 _converts the charge corresponding to the first reference voltage REFP charged in the capacitor C _fbp to the negative signal of the differential signal. Switch the connection to add. In this case, the third switch unit 166 switches the connection so as to add the charge corresponding to the second reference voltage REFN charged in the capacitor C _fbn to the positive signal of the differential signal. As an example, when the signal φin becomes a high potential according to the digital code “1”, the third switch unit 166 _connects the other terminal of the capacitor C _fbp to the transmission line of the negative signal at the timing. The other terminal of the capacitor C _fbn is connected to the transmission line of the positive signal.

  As described above, the DA conversion unit 160 outputs an analog signal corresponding to the positive reference voltage to the addition unit 120 as a feedback signal in accordance with the digital signal “0” output from the quantization unit 150, and the feedback signal is output to the addition unit 120. Add to the differential signal. Further, the DA conversion unit 160 outputs an analog signal corresponding to the negative reference voltage to the adding unit 120 as a feedback signal according to the digital signal “1” output from the quantization unit 150, and the feedback signal is differentially output. Add to signal.

  As described above, the control unit 180 controls the first switched capacitor unit 310 and the DA conversion unit 160 to superimpose the feedback signal for adding or subtracting the reference voltage on the input analog signal to the analog integrator 210. Supply. In FIG. 2, SP is the positive signal supplied from the adder 120 to the analog integrator 210, and SN is the negative signal. As described above, the incremental delta-sigma AD converter 10 can sample the input analog signal and convert it into a digital signal in accordance with the control signal from the control unit 180.

The feedforward unit 140 transmits a differential signal based on the positive side signal AINP and the negative side signal AINN branched by the branching unit 110 to the quantization unit 150. The feedforward unit 140 may have the same configuration as the first switched capacitor unit 310. That is, the feedforward unit 140 includes a positive side capacitor C _sffp , a negative side capacitor C _sffn , a pre-stage switch 142, and a _post- stage switch 144.

The pre-stage switch 142 switches one terminal of the positive side capacitor C _sfp to either an input terminal to which the analog signal AINP is input or a reference potential in accordance with a control signal of the control unit 180. Further, the pre-stage switch 142 switches one terminal of the negative side capacitor C _sffn to either an input terminal to which the analog signal AINN is input or a reference potential in accordance with a control signal of the control unit 180.

For example, the front-stage switch 142 _connects one terminal of each of the positive-side capacitor C _sffp and the negative-side capacitor C _sffn to the input terminal at the timing when the signal φsff supplied by the control unit 180 is at a high potential. In this case, the pre-stage switch 142 disconnects each electrical connection between one terminal of the positive capacitor C _sffp and the negative capacitor C _sffn and the corresponding input terminal at the timing when the signal φsff is at a low potential. .

Further, the pre-stage switch 142 _connects one terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to the reference potential at the timing when the signal φiff supplied from the control unit 180 is high potential. In this case, the pre-stage switch 142 disconnects each electrical connection between one terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn and the reference potential at the timing when the signal φiff is at a low potential.

The _post- stage switch 144 switches the other terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to either the quantization unit 150 or the reference potential in accordance with the control signal of the control unit 180.

For example, the post-stage switch 144 _connects the other terminal of the positive side capacitor C _sffp and the negative side capacitor C _sffn to the reference potential at the timing when the signal φsff is at the high potential, and at the timing when the signal φsff is at the low potential, Disconnect the electrical connection between the terminal and the reference potential. Further, the post-stage switch 144 connects, for example, the other terminals of the positive-side capacitor C _sffp and the negative-side capacitor C _sffn to the quantization unit 150 when the signal φiff is at a high potential, and the signal φsff is at a low potential. The electrical connection between the other terminal and the quantization unit 150 is cut off.

  As described above, the feedforward unit 140 repeats sampling and transfer of the input analog signal in accordance with the signal φsff and the signal φiff supplied from the control unit 180. Note that the control unit 180 may set the signal φiff to a low potential while the signal φsff is at a high potential and set the signal φiff to a high potential while the signal φsff is at a low potential, for example. That is, the feedforward unit 140 sets a period during which the signal φsff is high potential and the signal φiff is low potential as a sampling period, and sets a period when the signal φsff is low potential and the signal φiff is high potential as a transfer period.

  The incremental delta sigma AD converter 10 described above converts a signal obtained by adding the signal obtained by tracking and holding the input analog signal from the input terminal 12 by the first switched capacitor unit 310 and the feedback signal into a digital signal. Here, the input analog signal from the first switched capacitor unit 310 is input to the adder unit 120 after one tracking hold period. On the other hand, since the feedback signal passes through the first switched capacitor unit 310 or the feedforward unit 140 and the DA conversion unit 160, the feedback signal is input to the adding unit 120 after two tracking hold periods. .

  Therefore, if the input analog signal greatly fluctuates during one tracking hold period, the incremental delta sigma AD converter 10 cannot generate an accurate feedback signal. That is, the incremental type delta-sigma AD converter 10 cannot accurately perform AD conversion when the amplitude value of the input analog signal becomes high enough to fluctuate during one tracking hold period. The bandwidth was sometimes limited. Next, the operation of the incremental delta sigma AD converter 10 in such a case will be described.

  FIG. 3 shows an example of a timing chart of the incremental delta-sigma AD converter 10 shown in FIGS. In FIG. 3, the horizontal axis indicates time, and the vertical axis indicates signal intensity. The controller 180 outputs a control signal according to the CLK signal shown in FIG. The signal φsff and the signal φiff indicate examples of control signals that the control unit 180 supplies to the feedforward unit 140. Signal φs and signal φi are examples of control signals supplied from control unit 180 to analog integration unit 130 and DA conversion unit 160. FIG. 3 shows an example in which the signal φsff, the signal φiff, the signal φs, and the signal φi have substantially the same period as the clock signal.

  As described with reference to FIG. 2, the control unit 180 sets a period during which the high potential signal φsff and the low potential signal φiff are supplied to the feedforward unit 140 as a sampling period, and the low potential signal φsff and the high potential signal φiff. The period for supplying the data is the transfer period. Similarly, the control unit 180 sets the first switched capacitor unit 310 to a sampling period during which the high potential signal φs and the low potential signal φi are supplied, and supplies the low potential signal φs and the high potential signal φi. The period is the transfer period.

For example, the control unit 180 uses the period from time t ₂ to t ₃ of the feedforward unit 140 and the first switched capacitor unit 310 as a sampling period, and sets the period from time t ₃ to t ₄ as a transfer period. The waveform of the output voltage of the positive side capacitor C _sffp , the negative side capacitor C _sffn , the positive side capacitor C _sp , and the negative side capacitor C _sn in FIG. 2 shows an example of a signal output according to such a control signal.

  FIG. 2 shows an example of the amplitude voltage of the input analog signal as the input voltage. Here, an example in which the input voltage increases linearly with the passage of time is shown. The input voltage represents an example of a signal whose amplitude value changes twice or more during one tracking hold period. In FIG. 2, one tracking hold period is the sum of one sampling period and one transfer period. In FIG. 2, one tracking hold period is substantially the same as one clock period.

That is, the feedback signal output from the DA converter 160 is one signal from the signal transferred from the feedforward unit 140 to the quantization unit 150 or the signal transferred from the first switched capacitor unit 310 to the adding unit 120. The output is delayed by the tracking hold period. For example, according to the signal transferred from the feedforward unit 140 to the quantization unit 150 in the period from time t ₃ to t ₄ , the feedback signal output from the DA conversion unit 160 is transmitted in the period from time t ₅ to t ₆ . Is output.

  Therefore, even if the addition unit 120 adds the signal transferred from the first switched capacitor unit 310 and the feedback signal in the same period, if the input voltage changes at high speed, an appropriate timing is given due to a timing shift that gives feedback. It will no longer be feedback. Thus, the higher the frequency of the input analog signal, the greater the difference between the signal transferred from the first switched capacitor unit 310 and the feedback signal, making it impossible to accurately perform AD conversion. Sometimes. The analog integrator 210 outputs an output voltage corresponding to the difference during the transfer period as shown in FIG. In addition, the analog integrator 210 may oscillate when the output signal exceeds a specified value, and may not be able to perform AD conversion.

  Therefore, the incremental delta-sigma AD converter 10 in the present embodiment adjusts the timing at which the signal transferred from the first switched capacitor unit 310 and the feedback signal are supplied to the adder unit 120, respectively, so that the broadband input AD conversion corresponding to the signal can be executed. Such an incremental type delta sigma AD converter 10 will be described next.

  FIG. 4 shows a configuration example of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 of the incremental delta sigma AD converter 10 according to the present embodiment. In the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 shown in FIG. 4, the operations of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 shown in FIG. Are denoted by the same reference numerals, and description thereof is omitted.

  The analog integration unit 130 according to the present embodiment has a plurality of switched capacitor units. The plurality of switched capacitor units sample the input analog signal in different periods and transfer them in different periods. In this case, the control unit 180 controls the conversion period of the DA conversion unit 160 and the sampling periods and transfer periods of the plurality of switched capacitor units.

FIG. 4 shows an example in which the analog integration unit 130 has two switched capacitor units, a first switched capacitor unit 310 and a second switched capacitor unit 320. Since the first switched capacitor unit 310 has already been described with reference to FIG. 2, the description thereof is omitted here. In FIG. 4, the capacitors included in the first switched capacitor unit 310 are a positive-side capacitor C _sp1 and a negative-side capacitor C _sn1 . Further, signals for controlling the first switched capacitor unit 310 by the control unit 180 are signals φs1 and φi1.

The second switched capacitor unit 320 is connected in parallel with the first switched capacitor unit 310 between the input terminal of the analog integration unit 130 and the addition unit 120. The second switched capacitor unit 320 includes a positive capacitor C _sp2 , a negative capacitor C _sn2 , a front switch 322, and a rear switch 324. The capacitors and switches included in the second switched capacitor unit 320 may be substantially the same size as the capacitors and switches included in the first switched capacitor unit 310, or may be different sizes.

The pre-stage switch 322 switches one terminal of the positive side capacitor _Csp2 to either an input terminal to which the analog signal AINP is input or a reference potential in accordance with a control signal from the control unit 180. Further, the pre-stage switch 322 switches one terminal of the negative side capacitor C _sn2 to one of the input terminal to which the analog signal AINN is input and the reference potential in accordance with the control signal of the control unit 180.

For example, the front-stage switch 322 _connects one terminal of the positive-side capacitor C _sp2 and the negative-side capacitor C _sn2 to the input terminal at the timing when the signal φs2 supplied by the control unit 180 is high potential. In this case, the pre-stage switch 322 electrically disconnects one terminal of the positive capacitor C _sp2 and the negative capacitor C _{sn2 from} the input terminal at the timing when the signal φs2 is at a low potential.

The pre-stage switch 322 _connects one terminal of the positive capacitor C _sp2 and the negative capacitor C _sn2 to the reference potential at the timing when the signal φi2 supplied by the control unit 180 is high potential. In this case, primary switch 322, the signal φi2 is at the timing of the low potential, one terminal of the positive side capacitor C _sp2 and negative capacitor C _sn2, to electrically disconnect the respective reference potential.

The _post- stage switch 324 switches the other terminal of the positive side capacitor C _sp2 and the negative side capacitor C _sn2 to either the addition unit 120 or the reference potential in accordance with the control signal of the control unit 180.

The post-stage switch 324 connects, for example, the other terminal of the positive capacitor C _sp2 and the negative capacitor C _sn2 to the reference potential at the timing when the signal φs2 is at the high potential, and the other switch 324 at the timing when the signal φs2 is at the low potential. Disconnect the electrical connection between the terminal and the reference potential. Further, the post-stage switch 324 connects, for example, the other terminals of the positive-side capacitor C _sp2 and the negative-side capacitor C _sn2 to the adder 120 when the signal φi2 is at a high potential, and the signal φs2 is at a timing when the signal φs2 is at a low potential. The electrical connection between the other terminal and the adding unit 120 is cut off.

  As described above, the control unit 180 of the incremental delta-sigma AD converter 10 according to the present embodiment periodically switches the sampling period and the transfer period of the plurality of switched capacitor units. Next, the operation of the incremental delta sigma AD converter 10 by the control unit 180 will be described.

  FIG. 5 shows an example of a timing chart of the incremental delta sigma AD converter 10 according to the present embodiment shown in FIGS. 1 and 3. In FIG. 5, the horizontal axis indicates time, and the vertical axis indicates signal intensity. The control unit 180 outputs a control signal according to the CLK signal shown in FIG. The signal φsff and the signal φiff indicate examples of control signals supplied from the control unit 180 to the feedforward unit 140. The signal φs1, the signal φi1, the signal φs2, and the signal φi2 are examples of control signals that the control unit 180 supplies to the analog integration unit 130.

  In addition, the control unit 180 supplies the signal φs and the signal φi illustrated in FIG. That is, the DA converter 160 outputs one feedback signal according to one clock cycle. FIG. 5 also shows an example in which one tracking hold period and one clock period are substantially the same period.

That is, the signal φsff and φiff supplied to the feedforward unit 140 by the control unit 180 and the signal φs and signal φi supplied to the DA conversion unit 160 are substantially the same as the timing in FIG. Therefore, the waveform of the positive-side capacitor C _Sffp and negative capacitor C _Sffn output voltage shown in FIG. 5, the waveform of the output voltage of the DA converter portion 160, substantially the same as the waveform of the timing chart shown in FIG. 3 .

  The control unit 180 supplies the first switched capacitor unit 310 with the high potential signal φs1 and the low potential signal φi1 to set the sampling period, and supplies the low potential φs1 and the high potential signal φi1 with the transfer period. And In addition, the control unit 180 provides an interval period for holding the sampled charge between the sampling period and the transfer period. For example, the control unit 180 sets a period for supplying the high potential signal φs1 and the low potential signal φi1 to the first switched capacitor unit 310 as an interval period.

  In addition, the control unit 180 makes the interval period of one switched capacitor unit coincide with the sum of the sampling period and the transfer period of the one switched capacitor unit. That is, the control unit 180 holds the charge charged in one switched capacitor unit for one tracking hold period, and then transfers it to the adding unit 120.

In FIG. 5, the control unit 180 sets the period from time t ₄ to t ₅ of the first switched capacitor unit 310 as a sampling period, sets the period from time t ₅ to t ₇ as an interval period, and sets the period from time t ₇ to t ₈ . An example in which the period is the transfer period is shown. The controller 180 may periodically repeat such sampling period, interval period, and transfer period.

  Similarly to the first switched capacitor unit 310, the control unit 180 uses the period during which the high potential signal φs2 and the low potential signal φi2 are supplied to the second switched capacitor unit 320 as a sampling period, and the low potential signal φs2 A period during which the high-potential signal φi2 is supplied is a transfer period. Further, the control unit 180 sets a period during which the high potential signal φs2 and the low potential signal φi2 are supplied to the second switched capacitor unit 320 as an interval period.

5, the control unit 180, the second switched capacitor 320, the period of _{t 3} to a sampling period from time _{t 2, the} from time _{t 3} to the time period _{t 5} and the interval period from time _{t 5} the _{t 6} An example in which the period is the transfer period is shown. The controller 180 may periodically repeat such sampling period, interval period, and transfer period.

The controller 180 transfers the charge held by the first switched capacitor unit 310 and sets the second switched capacitor unit 320 as an interval period in a period for sampling the next input analog signal. For example, the control unit 180 transfers the period from time t ₃ to t ₅ when the first switched capacitor unit 310 transfers the previously sampled charge and samples the next input analog signal, and the interval period of the second switched capacitor unit 320. And

In addition, the control unit 180 transfers the charge held by the second switched capacitor unit 320 and sets the first switched capacitor unit 310 as an interval period in a period during which the next input analog signal is sampled. For example, the control unit 180 transfers the period from time t ₅ to t ₇ when the second switched capacitor unit 320 transfers the previously sampled charge and samples the next input analog signal, and the interval period of the first switched capacitor unit 310. And

  In this way, the control unit 180 controls the plurality of switched capacitor units so that one of the plurality of switched capacitor units becomes the sampling period in one tracking and holding cycle. The adder 120 adds the input analog signal transferred by the other of the plurality of switched capacitor units and the feedback signal from the DA converter 160 in one tracking hold period.

  As described above, the control unit 180 adjusts the sampling period and the transfer period of the plurality of switched capacitor units with respect to the conversion period of the DA conversion unit 160. That is, the control unit 180 adjusts the sampling period and the transfer period with respect to the conversion period so that the period in which the DA conversion unit 160 outputs the feedback signal and the transfer period of any of the plurality of switched capacitor units match. . Then, the control unit 180 reduces the difference between the feedback signal of the DA conversion unit 160 in one period and the analog transfer signal transferred by any of the plurality of switched capacitor units in the one period, respectively. Adjust the period.

For example, the control unit 180, a charge first switched capacitor 310 is sampled in the sampling period from time _{t 1,} until time _{t 3} is held, and from time _{t 3} to the adder 120 during the time period from _{t 4} Transfer To do. As described above, the controller 180 causes the charge sampled by the first switched capacitor unit 310 to be delayed by one tracking hold period and transferred to the adding unit 120.

On the other hand, the feedback signal transferred by the DA converter 160 is input to the adder 120 after two tracking and holding cycles. Therefore, the feedback signal to be transferred to the adder 120 during the time period from t ₄ DA conversion unit 160 from the time t ₃ is a signal corresponding to the electric charge feedforward module 140 is sampled in the sampling period from time t ₁ .

Similarly, the control unit 180 adds the charges second switched capacitor 320 is sampled in the sampling period from time _{t 2} to time _{t 3,} is held until time _{t 5,} from time _{t 5} to the time period from _{t 6} The data is transferred to the unit 120. The feedback signal DA conversion unit 160 is transferred to the adder 120 during the time period from t ₆ from the time t ₅ is to charge sampled respectively in the sampling period of the feedforward section 140 from time t ₂ to time t ₃ The corresponding signal.

  As described above, the control unit 180 performs the feedback signal passing through the feedforward unit 140 and the DA conversion unit 160 and the first switched capacitor unit 310 or the second switched capacity according to the input analog signal sampled in substantially the same period. The signal transferred from the data unit 320 is supplied to the adding unit 120 in substantially the same period. Accordingly, the adder 120 adds the signal transferred from the first switched capacitor unit 310 or the second switched capacitor unit 320 and the feedback signal in the same period, thereby giving an appropriate feedback to the input analog signal. be able to.

  That is, the incremental delta sigma AD converter 10 according to the present embodiment follows the digital signal even if the input analog signal becomes a high frequency whose amplitude value fluctuates several times during one tracking hold period. Can be converted to In the above-described incremental type delta-sigma AD converter 10 according to the present embodiment, the analog integration unit 130 has two switched capacitor units. However, the present invention is not limited to this. The analog integration unit 130 may include three or more switched capacitor units.

  FIG. 6 shows a first modification of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 of the incremental delta-sigma AD converter 10 according to the present embodiment. In the analog integration unit 130, the feed forward unit 140, and the DA conversion unit 160 of the first modification, the operations are substantially the same as the operations of the analog integration unit 130, the feed forward unit 140, and the DA conversion unit 160 shown in FIG. Are denoted by the same reference numerals and description thereof is omitted.

  The analog integration unit 130 according to the first modification is an example including a first switched capacitor unit 310, a second switched capacitor unit 320, and a third switched capacitor unit 330. Since the first switched capacitor unit 310 and the second switched capacitor unit 320 have already been described with reference to FIGS. 2 and 4, description thereof will be omitted here. The third switched capacitor unit 330 may have substantially the same configuration as the first switched capacitor unit 310 and the second switched capacitor unit 320.

That is, the third switched capacitor unit 330 is connected in parallel with the first switched capacitor unit 310 and the second switched capacitor unit 320 between the input terminal of the analog integration unit 130 and the addition unit 120. The third switched capacitor unit 330 includes a positive side capacitor C _sp3 , a negative side capacitor C _sn3 , a front stage switch 332, and a rear stage switch 334. The capacitors and switches included in the third switched capacitor unit 330 may be substantially the same size as the capacitors and switches included in the first switched capacitor unit 310 and / or the second switched capacitor unit 320, and may be different sizes. There may be. Next, the operation of the incremental delta sigma AD converter 10 of the first modification will be described.

  FIG. 7 shows an example of a timing chart of the incremental delta-sigma AD converter 10 according to the first modification. In the timing chart shown in FIG. 7, the same reference numerals are given to the substantially same operations as those in the timing chart shown in FIG. The controller 180 outputs a control signal according to the CLK signal shown in FIG. The signal φsff and the signal φiff indicate examples of control signals supplied from the control unit 180 to the feedforward unit 140. The signal φs1, the signal φi1, the signal φs2, the signal φi2, the signal φs3, and the signal φi3 are examples of control signals that the control unit 180 supplies to the analog integration unit 130.

  The control unit 180 provides a standby period between the transfer period and the sampling period of each of the first switched capacitor unit 310, the second switched capacitor unit 320, and the third switched capacitor unit 330. That is, the control unit 180 controls each switched capacitor unit to be in one of a sampling period, a holding period, a transfer period, and a standby period. For example, the control unit 180 sets a period during which the low-potential signal φs1 and the high-potential signal φi1 are supplied to the first switched capacitor unit 310 as a standby period. That is, the control unit 180 sets a period during which the state of the transfer period of the first switched capacitor unit 310 is maintained as a standby period.

  Further, the control unit 180 makes the sum of the transfer period and the standby period of one switched capacitor unit coincide with the sampling period and interval period of the one switched capacitor unit. For example, the control unit 180 sets the transfer period and the standby period to substantially the same time interval. In addition, the control unit 180 sets the sampling period and the interval period to a time interval that is twice the transfer period. Thereby, the control unit 180 provides one transfer period in three tracking hold periods, and transfers the charge charged in one switched capacitor unit to the adder unit 120 in the transfer period.

7, the control unit 180, the first switched capacitor portion 310, from the time _{t 1} the period _{t 3} as an interval period from the time _{t 3} as the transfer period during the time _{t 4,} from time _{t 4} of _{t 5} period and the standby period, showing an example of a sampling period during the time t ₇ from the time t _5.

Similarly to the first switched capacitor unit 310, the control unit 180 sets a period during which the low potential signal φs2 and the high potential signal φi2 are supplied to the second switched capacitor unit 320 as a standby period. In FIG. 7, the control unit 180 sets the period from time t ₁ to t ₃ of the second switched capacitor unit 320 as a sampling period, sets the period from time t ₃ to t ₅ as an interval period, and sets the period from time t ₅ to t ₆ . period and the transfer period, the period t ₇ from the time t ₆ shows an example of the waiting period.

Further, the control unit 180 controls the third switched capacitor unit 330 in the same manner as the first switched capacitor unit 310 and the second switched capacitor unit 320. That is, the period for supplying the high potential signal φs3 and the low potential signal φi3 is set as the sampling period and the interval period, and the period for supplying the low potential signal φs3 and the high potential signal φi3 is transferred to the third switched capacitor unit 330. Period and waiting period. In FIG. 7, the control unit 180 sets the period from time t ₃ to t ₅ of the third switched capacitor unit 330 as a sampling period, sets the period from time t ₅ to t ₇ as an interval period, and sets the period from time t ₇ to t ₈ . the term as the transfer period, the period t ₉ from time t ₈ shows an example of a waiting period.

  The control unit 180 may periodically repeat the sampling period, interval period, transfer period, and standby period of the switched capacitor unit. In addition, the control unit 180 includes the remaining switched capacitors during a period in which one of the first switched capacitor unit 310, the second switched capacitor unit 320, and the third switched capacitor unit 330 samples the input analog signal. One of the units is an interval period, and the other of the remaining switched capacitor units is a transfer period and a standby period.

7, the control unit 180, in the period _{t 3} from time _{t 1,} the second switched capacitor 320 and the sampling period, the first switched capacitor 310 and the interval period, the transfer period of the third switched capacitor 330 An example of the standby period is shown. In addition, the control unit 180 sets the third switched capacitor unit 330 as a sampling period, the second switched capacitor unit 320 as an interval period, and sets the first switched capacitor unit 310 as a transfer period and a standby period during a period from time t ₃ to time t _5. Period.

The control unit 180, in the period _{t 7} from the time _{t 5,} the first switched capacitor 310 and the sampling period, the third switched capacitor 330 and the interval period, the transfer period and waits for a second switched capacitor portion 320 Period. In this manner, the control unit 180 sequentially switches the three states of the sampling period, the interval period, the transfer period, and the standby period for each switched capacitor unit for each tracking hold period. In addition, the control unit 180 switches the three switched capacitor units to one of different states among the sampling period, the interval period, the transfer period, and the standby period for each tracking hold period.

That is, the control unit 180 performs control so that the transfer period starts after two tracking hold periods from the time when one switched capacitor unit starts the sampling period. In addition, the control unit 180 controls the three switched capacitor units to sequentially transfer the input analog signal every tracking and holding period. As a result, the first switched capacitor unit 310 transfers the charge sampled during the period from time t ₁ to the adder unit 120 from time t ₃ , and the second switched capacitor unit 320 operates from time t ₁ to time t _3. to transfer the charge, sampling from time t ₅ to the time period, the third switched capacitor 330 transfers charge sampled in the period from time t ₃ to time t ₅ the time t _7.

On the other hand, the feedback signal to be transferred to the addition unit 120 during the time period from t ₄ DA conversion unit 160 from the time t ₃ is a signal corresponding to the charges feedforward module 140 is sampled in the sampling period from time t ₁ . Similarly, the feedback signal of the period of time t ₆ from the time t ₅ is a signal corresponding to the charge sampled in the period from time t ₂ to time t _3, the feedback from the time t ₇ the period of time t ₈ signal is a signal corresponding to the charge sampled in the period from time t ₄ to time t _5.

  As described above, the control unit 180 transfers the feedback signal that passes through the feedforward unit 140 and the DA conversion unit 160 according to the input analog signal sampled in substantially the same period, and any one of the plurality of switched capacitor units. Are supplied to the adding unit 120 in substantially the same period. Therefore, the adder 120 adds the signal transferred from the first switched capacitor unit 310, the second switched capacitor unit 320, or the third switched capacitor unit 330 and the feedback signal in the same period, so that the input analog Appropriate feedback can be given to the signal.

  Further, the incremental delta-sigma AD converter 10 of the first modification can extend the sampling period to the same extent as the tracking hold period. Therefore, for example, when a buffer circuit or the like is provided before the incremental delta sigma AD converter 10 or inside the incremental delta sigma AD converter 10, the settling time of the buffer circuit can be extended.

  Although the incremental type delta-sigma AD converter 10 of the first modification shown in FIG. 6 has been described as having three switched capacitor units, the present invention is not limited to this. The incremental type delta-sigma AD converter 10 may have more switched capacitor units by switching the respective switched capacitor units to a sampling period, an interval period, a transfer period, and a standby period.

  FIG. 8 shows a configuration example of the feedforward unit 140 and the quantization unit 150 of the incremental delta-sigma AD converter 10 according to the present embodiment. Note that the feedforward unit 140 has been described with reference to FIGS. The quantization unit 150 may be controlled by the control unit 180. The quantization unit 150 includes a pre-stage circuit 152 and a quantizer 154.

  The pre-stage circuit 152 adds the signal supplied from the feedforward unit 140 and the signal supplied from the analog integration unit 130. The pre-stage circuit 152 includes a first circuit 250 and a second circuit 280.

First circuit 250 includes a switched capacitor and transmits analog signals AINP and AINN from feedforward unit 140 to quantizer 154. As an example, the switched capacitor of the first circuit 250 includes a first switch 252, a capacitor C _0ffp , and a capacitor C _0ffn .

For example, the first switch 252 switches one terminal of the capacitor C _0ffp to one of the input terminal to which the analog signal AINP is input and the reference potential in accordance with the control signal of the control unit 180. The other terminal of the capacitor C _0ffp is connected to the quantizer 154. As an example, the capacitor C _0ffp has one terminal connected to the input terminal at the first timing, and charges the analog input signal. The capacitor C _0ffp has one terminal connected to the reference potential at the second timing, and discharges the charged analog input signal to the quantizer 154.

Similarly, the first switch 252 switches one terminal of the capacitor C _0ffn to one of the input terminal to which the analog signal AINN is input and the reference potential in accordance with the control signal of the control unit 180. The capacitor C _0ffn has one terminal connected to the input terminal and charges the analog input signal at the first timing. The capacitor C _0ffn has one terminal connected to the reference potential at the second timing, and discharges the charged analog input signal to the quantizer 154.

Second circuit 280 includes a switched capacitor, and transmits signals output from analog integrator 130 (for example, INTP and INTN) to quantizer 154. As an example, the second circuit 280 includes a second switch 282, a capacitor C _3ffp , and a capacitor C _3ffn .

The second switch 282 switches one terminal of the positive capacitor C _3ffp to either the output terminal from which the analog integration unit 130 outputs the signal INTP or the reference potential in accordance with the control signal of the control unit 180. The other terminal of the capacitor C _3ffp is connected to the quantizer 154. For example, the capacitor C _3ffp has one terminal connected to the output terminal and charges the signal INTP at the first timing. Capacitor C _3ffp has one terminal connected to the reference potential at the second timing, and discharges the charged signal to quantizer 154.

Similarly, according to the control signal of the control unit 180, the second switch 282 _connects one terminal of the negative side capacitor C _3ffn to either the output terminal from which the analog integration unit 130 outputs the signal INTN or the reference potential. Switch. The other terminal of the capacitor C _3ffn is connected to the quantizer 154. For example, the capacitor C _3ffn has one terminal connected to the output terminal and charges the signal INTN at the first timing. Then, at the second timing, one terminal of the capacitor C _3ffn is connected to the reference potential, and the charged signal is discharged to the quantizer 154.

  The quantizer 154 quantizes the signal supplied from the pre-stage circuit 152. The quantizer 154 may be a 1-bit quantizer or a multi-bit quantizer.

  As an example, control unit 180 causes first circuit 250 and second circuit 280 to perform a charging operation at a first timing when signal φi is at a high potential and a discharging operation at a second timing when signal φs is at a high potential. . As described above, the quantization unit 150 adds and quantizes the signal from the feedforward unit 140 and the signal output from the analog integration unit 130. In this way, by superimposing the feedforward signal on the signal output from the analog integrator 130, the digital code output from the quantizer 154 for each clock should reflect the analog input signal at a higher speed. Can do.

  In the incremental delta-sigma AD converter 10 according to the above-described embodiment, the example in which the plurality of switched capacitors included in the analog integration unit 130 are connected in parallel has been described. However, the present invention is not limited to this. The plurality of switched capacitors may be connected in series and sequentially transfer the input analog signal to the subsequent stage. That is, the timing at which the last switched capacitor of a plurality of switched capacitors connected in series transfers the input analog signal to the adder 120 and the timing at which the feedback signal via the feedforward unit 140 reaches the adder 120. By substantially matching, it is possible to give appropriate feedback to the input analog signal. Such an incremental type delta sigma AD converter 10 will be described next.

  FIG. 9 shows a second modification of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 of the incremental delta-sigma AD converter 10 according to the present embodiment. In the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 of the second modification, the operations are substantially the same as those of the analog integration unit 130, the feedforward unit 140, and the DA conversion unit 160 shown in FIG. Are denoted by the same reference numerals and description thereof is omitted. The analog integration unit 130 of the second modified example shows an example in which a plurality of switched capacitors are arranged in series.

FIG. 9 shows an example in which the analog integration unit 130 includes two switched capacitor units, a first switched capacitor unit 310 and a second switched capacitor unit 320, and a hold unit 340 that holds a signal transferred from the first switched capacitor unit 310. Indicates. Since the first switched capacitor unit 310 has already been described with reference to FIG. 2, the description thereof is omitted here. In FIG. 4, the capacitors included in the first switched capacitor unit 310 are a positive-side capacitor C _sp1 and a negative-side capacitor C _sn1 . Further, signals for controlling the first switched capacitor unit 310 by the control unit 180 are signals φs1 and φi1.

  The hold unit 340 is provided between the first switched capacitor unit 310 and the second switched capacitor unit 320, holds the potential output from the first switched capacitor unit 310, and transfers the potential to the second switched capacitor unit 320. The hold unit 340 may have a configuration similar to that of the analog integrator 210. The hold unit 340 includes an analog amplifier 342, a positive reset switch 344, a negative reset switch 346, and a feedback capacitor.

  The analog amplifier 342 amplifies the signals input to the positive input terminal and the negative input terminal and outputs the amplified signals. The analog amplifier 342 is, for example, a differential input type amplifier circuit. The analog amplifier 212 may be an amplifier circuit similar to the analog amplifier 212. The positive side reset switch 344 and the negative side reset switch 346 discharge the charges accumulated in the feedback capacitor in accordance with an instruction from the reset unit 170 to reset the analog amplifiers.

Each of the feedback capacitors repeats charge and discharge according to the input signal. The feedback capacitor switches between charging and discharging every sampling, for example. As an example, the positive feedback capacitor C _hp from the positive side capacitor C _sp1 of the first switched capacitor portion 310 which signal φi1 high potential becomes supplied with transfer period, sampled on the positive side capacitor C _sp1 charge Is transferred. Similarly, the negative-side feedback capacitor C _hn is transferred with the sampled charge from the negative-side capacitor C _sn1 of the first switched capacitor unit 310 that is in the transfer period when the high-potential signal φi1 is supplied.

Also, the positive feedback capacitor C _hp, the signal φs2 high potential to the positive side capacitor C _sp2 of the second switched capacitor 320 becomes supplied with the sampling period, transferring the charges charged. Similarly, the negative feedback capacitor C _hn transfers the charged charge to the negative capacitor C _sn2 of the second switched capacitor unit 320 that is in the sampling period when the high potential signal φi2 is supplied.

The second switched capacitor unit 320 is connected between the hold unit 340 and the addition unit 120. The second switched capacitor unit 320 includes a positive capacitor C _sp2 , a negative capacitor C _sn2 , a front switch 322, and a rear switch 324. The capacitors and switches included in the second switched capacitor unit 320 may be substantially the same size as the capacitors and switches included in the first switched capacitor unit 310, or may be different sizes.

The pre-stage switch 322 switches one terminal of the positive side capacitor _Csp2 to either the positive side output terminal of the hold unit 340 or the reference potential in accordance with the control signal of the control unit 180. Further, the pre-stage switch 322 switches one terminal of the negative side capacitor C _sn2 to either the negative side output terminal of the hold unit 340 or the reference potential in accordance with the control signal of the control unit 180.

For example, the front-stage switch 322 _connects one terminal of the positive-side capacitor C _sp2 and the negative-side capacitor C _sn2 to the output terminal of the hold unit 340 at the timing when the signal φs2 supplied by the control unit 180 is at a high potential. In this case, the pre-stage switch 322 electrically disconnects one terminal of the positive capacitor C _sp2 and the negative capacitor C _{sn2 from} the output terminal of the hold unit 340 at the timing when the signal φs2 is at a low potential.

The pre-stage switch 322 _connects one terminal of the positive capacitor C _sp2 and the negative capacitor C _sn2 to the reference potential at the timing when the signal φi2 supplied by the control unit 180 is high potential. In this case, primary switch 322, the signal φi2 is at the timing of the low potential, one terminal of the positive side capacitor C _sp2 and negative capacitor C _sn2, to electrically disconnect the respective reference potential.

The _post- stage switch 324 switches the other terminal of the positive side capacitor C _sp2 and the negative side capacitor C _sn2 to either the addition unit 120 or the reference potential in accordance with the control signal of the control unit 180.

The post-stage switch 324 connects, for example, the other terminal of the positive capacitor C _sp2 and the negative capacitor C _sn2 to the reference potential at the timing when the signal φs2 is at the high potential, and the other switch 324 at the timing when the signal φs2 is at the low potential. Disconnect the electrical connection between the terminal and the reference potential. Further, the post-stage switch 324 connects, for example, the other terminals of the positive-side capacitor C _sp2 and the negative-side capacitor C _sn2 to the adder 120 when the signal φi2 is at a high potential, and the signal φs2 is at a timing when the signal φs2 is at a low potential. The electrical connection between the other terminal and the adding unit 120 is cut off.

  As described above, the control unit 180 of the incremental delta-sigma AD converter 10 according to the present embodiment periodically switches the sampling period and the transfer period of the plurality of switched capacitor units. Next, the operation of the incremental delta sigma AD converter 10 of the second modified example by the control unit 180 will be described.

  FIG. 10 shows an example of a timing chart of the incremental delta-sigma AD converter 10 according to the second modification. In FIG. 10, the horizontal axis indicates time, and the vertical axis indicates signal intensity. The control unit 180 outputs a control signal in accordance with the CLK signal shown in FIG. The signal φsff and the signal φiff indicate examples of control signals supplied from the control unit 180 to the feedforward unit 140. Signal φs 1, signal φi 1, signal φs 2, signal φi 2, and signal φr 1 are examples of control signals that control unit 180 supplies to analog integration unit 130.

  In addition, the control unit 180 supplies the signal φs and the signal φi illustrated in FIG. That is, the DA converter 160 outputs one feedback signal according to one clock cycle. FIG. 10 also shows an example in which one tracking hold period and one clock period are substantially the same period.

That is, the signal φsff and φiff supplied to the feedforward unit 140 by the control unit 180 and the signal φs and signal φi supplied to the DA conversion unit 160 are substantially the same as the timing in FIG. Therefore, the waveform of the positive-side capacitor C _Sffp and negative capacitor C _Sffn output voltage shown in FIG. 10, the waveform of the output voltage of the DA converter portion 160, substantially the same as the waveform of the timing chart shown in FIG. 3 .

  The control unit 180 supplies the first switched capacitor unit 310 with the high potential signal φs1 and the low potential signal φi1 to set the sampling period, and supplies the low potential φs1 and the high potential signal φi1 with the transfer period. And Here, the period in which the signal φs1 and the signal φs2 are at a high potential may be shorter than the period in which the signal φsff is at a high potential. The hold unit 340 may be reset by setting the signal φr1 to the high potential in the period in which the signal φs1 and the signal φs2 are in the low potential in the period in which the signal φsff is in the high potential. The controller 180 may periodically repeat such a sampling period and a transfer period.

  Similarly to the first switched capacitor unit 310, the control unit 180 uses the period during which the high potential signal φs2 and the low potential signal φi2 are supplied to the second switched capacitor unit 320 as a sampling period, and the low potential signal φs2 A period during which the high-potential signal φi2 is supplied is a transfer period. The controller 180 may periodically repeat such a sampling period and a transfer period.

  As described above, the control unit 180 adjusts the sampling period and the transfer period of the plurality of switched capacitor units with respect to the conversion period of the DA conversion unit 160. That is, the control unit 180 performs sampling for the conversion period so that the timing at which the DA conversion unit 160 outputs the feedback signal and the timing at which the second switched capacitor unit 320 transfers the output signal substantially match in the addition unit 120. Adjust period and transfer period. Then, the control unit 180 reduces the difference between the feedback signal of the DA conversion unit 160 in one period and the analog transfer signal transferred by the second switched capacitor unit 320 in the one period. Adjust.

For example, the control unit 180 transfers the charge sampled by the first switched capacitor unit 310 during the sampling period until time t ₁ to the hold unit 340 during the period until time t ₂ . Then, the charges transferred to the holding unit 340 is transferred to the period from time _{t 3} to the second switched capacitor 320 is transferred to the adding unit 120 from the time _{t 3} during the time period from _{t 4.} As described above, the control unit 180 transfers the charge sampled by the first switched capacitor unit 310 to the adding unit 120 with a delay of one tracking hold period.

On the other hand, the feedback signal transferred by the DA converter 160 is input to the adder 120 after two tracking and holding cycles. Therefore, the feedback signal to be transferred to the adder 120 during the time period from t ₄ DA conversion unit 160 from the time t ₃ is a signal corresponding to the electric charge feedforward module 140 is sampled in the sampling period from time t ₁ .

  As described above, the control unit 180 controls the feedback signal that passes through the feedforward unit 140 and the DA conversion unit 160, the first switched capacitor unit 310, and the hold unit 340 according to the input analog signal sampled in substantially the same period. And the signal transferred through the second switched capacitor unit 320 are supplied to the adder unit 120 in substantially the same period. Therefore, the adder 120 adds the signal transferred from the second switched capacitor unit 320 and the feedback signal in the same period, so that appropriate feedback can be given to the input analog signal.

  That is, the incremental type delta-sigma AD converter 10 according to the second modified example follows the digital signal even if the input analog signal becomes a high frequency whose amplitude value fluctuates several times during one tracking hold period. Can be converted to a signal. In the incremental delta-sigma AD converter 10 according to the second modified example described above, the analog integration unit 130 has two switched capacitor units. However, the present invention is not limited to this. The analog integration unit 130 may include three or more switched capacitor units. In this case, the analog integration unit 130 may arrange a plurality of switched capacitor units in series and in parallel.

  The various embodiments of the present invention described above may be described with reference to flowcharts and block diagrams. The blocks in the flowcharts and block diagrams may be expressed as (1) the stage of the process in which the operation is performed or (2) the “part” of the device responsible for performing the operation. Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor.

  Certain stages and “parts” are provided with dedicated circuitry, programmable circuitry supplied with computer readable instructions stored on a computer readable storage medium, and / or computer readable instructions stored on a computer readable storage medium. It may be implemented by a processor. Note that the dedicated circuit may include a digital and / or analog hardware circuit, and may include an integrated circuit (IC) and / or a discrete circuit. Programmable circuits may be logical products, logical sums, exclusive logical sums, negative logical products, negative logical sums, and other logical operations, such as field programmable gate arrays (FPGAs) and programmable logic arrays (PLA), for example. , Flip-flops, registers, and memory elements, including reconfigurable hardware circuitry.

  The computer readable storage medium may include any tangible device that can store instructions executed by a suitable device. Thereby, a computer readable storage medium having instructions stored on the tangible device comprises a product including instructions that can be executed to create a means for performing the operations specified in the flowchart or block diagram. become.

  Examples of computer readable storage media may include electronic storage media, magnetic storage media, optical storage media, electromagnetic storage media, semiconductor storage media, and the like. More specific examples of the computer-readable storage medium include a floppy disk, diskette, hard disk, random access memory (RAM), read only memory (ROM), and erasable programmable read only memory (EPROM or flash memory). Electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), compact disc read only memory (CD-ROM), digital versatile disc (DVD), Blu-ray (registered trademark) disc, memory stick Integrated circuit cards and the like may be included.

  Computer readable instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, and the like. Computer-readable instructions also include object-oriented programming languages such as Smalltalk, JAVA, C ++, etc., and conventional procedural programming languages such as the “C” programming language or similar programming languages, or It may include source code or object code written in any combination of multiple programming languages.

  The computer readable instructions may be a processor of a general purpose computer, special purpose computer, or other programmable data processing device, either locally or via a wide area network (WAN) such as a local area network (LAN), the Internet, etc. Or it may be provided in a programmable circuit. This allows a general purpose computer, special purpose computer, or other programmable data processing device processor, or programmable circuit to generate means for performing the operations specified in the flowchart or block diagram, Computer readable instructions can be executed. Note that examples of the processor include a computer processor, a processing unit, a microprocessor, a digital signal processor, a controller, a microcontroller, and the like.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

10 Incremental Delta Sigma AD Converter, 12 Input Terminals, 14 Output Terminals, 100 Delta Sigma Conversion Unit, 110 Branching Unit, 120 Addition Unit, 130 Analog Integration Unit, 140 Feed Forward Unit, 142 Pre-stage Switch, 144 Post-stage Switch, 150 Quantizer, 152 Pre-stage circuit, 154 Quantizer, 160 DA converter, 162 First switch, 164 Second switch, 166 Third switch, 170 Reset, 180 Control, 190 Digital filter, 210 Analog integrator, 212 Analog amplifier, 214 Positive reset switch, 216 Negative reset switch, 250 First circuit, 252 First switch, 280 Second circuit, 282 Second switch, 310 First switched capacitor unit, 312 , 314 rear stage switch, 320 second switched capacitor section, 322 front stage switch, 324 rear stage switch, 330 third switched capacitor section, 332 front stage switch, 334 rear stage switch, 340 hold section, 342 analog amplifier, 344 positive side reset switch 346 Negative reset switch

Claims (18)

An analog integrator having an analog integrator and integrating an input analog signal;
A quantization unit that quantizes a signal based on the output signal of the analog integration unit;
A feedforward unit for transmitting the input analog signal to the quantization unit;
A DA converter that generates a feedback signal based on the output of the quantizer;
With
The analog integrator is
A plurality of switched capacitor units that sample the input analog signal in different periods and transfer in different periods;
An adder for adding the feedback signal from the DA converter to the input analog signal transferred by the plurality of switched capacitor units;
An incremental type delta-sigma AD converter. A control unit for controlling a sampling period and a transfer period of the plurality of switched capacitor units;
The control unit reduces the difference between the feedback signal of the DA conversion unit in one period and an analog transfer signal transferred by any one of the plurality of switched capacitor units in the one period. The incremental delta-sigma AD converter according to claim 1, wherein a sampling period and the transfer period are adjusted.   The control unit adjusts the sampling period and the transfer period so that a period during which the DA conversion unit outputs the feedback signal and a transfer period of any of the plurality of switched capacitor units match. The incremental delta-sigma AD converter according to claim 2.   The incremental delta-sigma AD converter according to claim 2 or 3, wherein at least some of the plurality of switched capacitor units are connected in parallel. The controller is
Periodically switching the sampling period and the transfer period of each of the plurality of switched capacitor units;
The incremental delta-sigma AD converter according to any one of claims 2 to 4, wherein an interval period for holding the sampled charge is provided between each of the sampling period and the transfer period.   The incremental delta-sigma AD converter according to claim 5, wherein the control unit matches the interval period of one switched capacitor unit with a sum of the sampling period and the transfer period of the one switched capacitor unit. The analog integration unit includes a first switched capacitor unit and a second switched capacitor unit,
The controller is
In the period for transferring the charge held by the first switched capacitor unit and sampling the next input analog signal, the second switched capacitor unit is set as the interval period,
7. The incremental delta according to claim 5, wherein the first switched capacitor unit is set as the interval period in a period in which a charge held by the second switched capacitor unit is transferred and a next input analog signal is sampled. Sigma AD converter. The analog integration unit includes a first switched capacitor unit, a second switched capacitor unit, and a third switched capacitor unit,
6. The control unit according to claim 5, wherein the control unit provides a waiting period between the transfer period and the sampling period of each of the first switched capacitor unit, the second switched capacitor unit, and the third switched capacitor unit. Incremental delta-sigma AD converter.   The incremental delta-sigma AD according to claim 8, wherein the control unit matches the sum of the transfer period and the standby period of one switched capacitor unit with the sampling period and the interval period of the one switched capacitor unit. converter. The controller is
Among the first switched capacitor unit, the second switched capacitor unit, and the third switched capacitor unit, one switched capacitor unit samples an input analog signal.
One of the remaining switched capacitor parts is set as the interval period,
The incremental delta-sigma AD converter according to claim 8 or 9, wherein the other switched capacitor unit is set as the transfer period and the standby period.   The incremental delta-sigma AD converter according to claim 1, wherein at least some of the plurality of switched capacitor units are connected in series. A control unit for controlling a sampling period and a transfer period of the plurality of switched capacitor units;
The control unit includes the feedback signal of the DA conversion unit in one period, an analog transfer signal transferred by the last switched capacitor unit of the plurality of switched capacitor units connected in series in the one period, and The incremental delta-sigma AD converter according to claim 1, wherein the sampling period and the transfer period are adjusted so as to reduce a difference between the sampling period and the transfer period.   The control unit adjusts the sampling period and the transfer period so that a period during which the DA conversion unit outputs the feedback signal and a transfer period of the last-stage switched capacitor unit coincide with each other. 12. Incremental delta-sigma AD converter according to item 12. The controller is
The incremental delta-sigma AD converter according to claim 12 or 13, wherein the sampling period and the transfer period of each of the plurality of switched capacitor units are periodically switched. Branching the transmission line for transmitting the input analog signal, comprising a branching unit for inputting one of the branched to the analog integration unit,
The feedforward unit transmits the other input analog signal branched by the branching unit to the quantization unit,
The incremental delta according to any one of claims 1 to 14, wherein the quantization unit quantizes a signal obtained by adding the input analog signal transmitted by the feedforward unit to an output signal of the analog integration unit. Sigma AD converter.   The incremental delta-sigma AD converter according to any one of claims 1 to 15, further comprising a reset unit that resets an integration value held by the analog integration unit for each predetermined period. A digital filter unit for filtering the output of the quantization unit;
The incremental type delta-sigma AD converter according to claim 16, wherein the reset unit resets the digital filter unit at a timing of resetting the analog integration unit. Integrating the input analog signal;
Quantizing a signal obtained by integrating the input analog signal;
DA conversion of the quantized signal to generate a feedback signal;
With
Integrating the input analog signal is
Sampling the input analog signal in different periods using a plurality of switched capacitor units and transferring in different periods;
Adding the feedback signal to the transferred analog input signal;
An AD conversion method comprising:

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