KR101725834B1

KR101725834B1 - Delta-sigma modulator

Info

Publication number: KR101725834B1
Application number: KR1020160062571A
Authority: KR
Inventors: 최정훈; 윤광섭
Original assignee: 인하대학교 산학협력단
Priority date: 2016-05-23
Filing date: 2016-05-23
Publication date: 2017-04-11

Abstract

The present invention suggests a delta-sigma modulator. The delta-sigma modulator of the present invention comprises: an integrating unit; an adding unit to add an output of a feed-forwarded integrating unit; and a comparing unit for performing analog-digital conversion on a signal added in the adding unit. Therefore, the complexity in a circuit design is reduced, and the same operation can be performed with a smaller amount of consumption power than that of the existing adder based on a calculation amplifier.

Description

Delta-sigma modulator {DELTA-SIGMA MODULATOR}

The present invention relates to a delta-sigma modulator, and more particularly to an analog-to-digital converter for solving the summation problem in a delta-sigma modulator having a multi-bit and feedforward structure to reduce power consumption and increase resolution at low OSR will be.

An analog-to-digital converter using a delta-sigma modulation method converts an analog signal into a digital signal using an operational amplifier, a switch-capacitor circuit, a comparator and a digital circuit. Is used in the device for.

Among them, the delta-sigma modulator can minimize the quantization noise of the signal band by oversampling and noise modification, and push out the noise of the high frequency component included in the input signal out of the bandwidth.

Therefore, the delta-sigma A / D converter using the delta-sigma modulation method is determined by various structures and circuit implementation methods of the delta-sigma modulator such as low power and high resolution.

However, due to the high performance conditions of the operational amplifier due to oversampling, there is a limitation in improving the power efficiency of the delta-sigma modulator.

Therefore, the proposed delta-sigma modulator using the feedforward and multi-bit structure has a structure in which the output of the integrator composed of each operational amplifier is summed and converted by the analog-to-digital converter inside the modulator.

However, a multi-bit structure versus a single bit structure can obtain a high resolution at a low oversampling rate, but when used with a feedforward structure, an adder for additional signal summing is required, which increases the power consumption.

Korean Patent Registration No. 10-1559456

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide an adder for summing signals before an internal analog-digital converter by summing an output signal fed-forwarded by an inverter-based integrator through an inverter-based adder, Inverter-based integrator circuit is applied and low-power circuit with reduced power consumption compared to existing op-amp-based adder circuit is provided.

A delta-sigma modulator according to the present invention comprises:

Integral part; An adder for summing the outputs of the feed forward integrators; And a comparator for analog-to-digital converting the summed signal in the adder.

Advantageously, said delta-sigma modulator can utilize a multi-bit and feedforward structure.

Advantageously, said integrator comprises an inverter-based integrator.

Advantageously, the adder may comprise an analog adder for summing the outputs of the integrator that are fed forward.

Advantageously, the comparator may include a 1.5 bit comparator for analog-to-digital conversion of the summed signal in the adder.

Advantageously, said 1.5 bit comparator comprises two latch comparators and may be a flash analog-to-digital converter architecture.

According to the present invention, it is possible to reduce the complexity of the circuit design and perform the same operation at a power consumption lower than that of an existing operational amplifier based adder.

BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate preferred embodiments of the invention and, together with the description of the invention given below, serve to further understand the technical idea of the invention. And should not be construed as limiting.
1 is a configuration diagram of a delta-sigma modulator according to an embodiment of the present invention;
2 is a circuit diagram of a delta-sigma modulator according to an embodiment of the present invention;
3 is a circuit diagram of an analog adder according to an embodiment of the present invention;
4 is a circuit diagram of a 1.5 bit comparator according to one embodiment of the present invention.
5 is a signal flow diagram of a delta-sigma modulator according to an embodiment of the present invention.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

The specific structure or functional description presented in the embodiment of the present invention is merely illustrative for the purpose of illustrating an embodiment according to the concept of the present invention, and embodiments according to the concept of the present invention can be implemented in various forms.

And should not be construed as limited to the embodiments set forth herein, but should be understood to include all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

FIG. 1 is a block diagram showing a configuration of a delta-sigma modulator 1 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an overall circuit diagram of a delta-sigma modulator 1 according to an embodiment of the present invention. to be.

The delta-sigma modulator 1 according to the embodiment of the present invention includes an integrating unit 10, an adding unit 20, and a comparing unit 30.

The integrator (10) may include an inverter-based integrator (100).

The adder 20 may include an analog adder 200.

The comparator 30 may include a 1.5 bit comparator 300.

That is, the entire circuit of the delta-sigma modulator 1 includes a three-stage inverter-based integrator 100, an analog adder 200 for summing the outputs of the feed-forwarded integrator, and a 1.5 to analog- And a bit comparator 300. [

The inverter-based integrator 100 receives an external voice signal (analog signal) to be digitally converted as a differential signal by receiving it as vinp and vinn.

This signal can go through a filter consisting of inverter-based integrator 100 and delta analog adder 200 for delta-sigma modulation.

Where each inverter-based integrator 100 may have a transfer function such as.

3 is a circuit diagram of an analog adder 200 according to an embodiment of the present invention.

The analog adder 200 uses the same structure by applying the inverter-based integrator 100 circuit, thereby reducing the power consumption and the complexity of the circuit compared to the operational amplifier-based adder.

Feedforward is a way of predicting future indications by calculation and controlling based on the information. The feedback is to manipulate the target value to be controlled to the desired purpose when the objective value to be controlled deviates from the objective, It is interpreted to give information and control the future before signs of departure from the purpose.

Unlike a single bit delta-sigma modulator, the use of a feed-forward scheme in a multi-bit delta-sigma modulator requires additional circuitry to sum the feed-forwarded signals.

In the single bit structure, only the +/- sign of the common mode signal of the summed signal needs to be used, so that there is no problem even if a summation circuit using a switch-capacitor is used without an additional active element.

However, in a multi-bit structure, a single bit structure switch-capacitor summing circuit can not be used because the sum of the signals needs to be compared with the signal size through the ADC to determine the output code.

The inverter-based analog adder 200 is designed to add the input value in the next integration period by initializing the previous integration value stored in the integral capacitor in the sampling interval of the integrator 100. [

In the p1 clock that performs the sampling, both ends of the integral capacitor Ci connected to the inverter can be short-circuited to discharge the previously stored addition value

And can also sample the output signal of the feed-forwarded integrator 100 to the capacitors C1-Cn.

At the same time, the offset voltage Vos generated in the inverter can be stored in the capacitor Cc.

In the p1 clock that performs the add operation, the voltage of the Vc node may become almost equal to the common mode voltage due to the Vos voltage stored in the capacitor Cc at p2.

Because of this auto zeroing, the same effect as virtual ground can be obtained. At this time, the total amount of charges charged in the capacitors C1, C2, C3, and C4 is expressed by the following equation.

The current flows to make the Vc node a common-mode voltage, so the voltage across the integrated capacitor Ci is as follows.

As in the case of the integrator 100, the feedforward coefficient can be determined through the ratio of the sampling capacitor to the integral capacitor, and since the capacitor to be driven is very small, an inverter much smaller than the inverter used in the integrator 100 can be used.

Therefore, the circuit area and power consumption can be minimized compared with the operational amplifier based adder. The use of a circuit having the same structure as the inverter-based integrator 100 can greatly simplify the circuit design.

4 is a circuit diagram of a 1.5 bit comparator 300 according to an embodiment of the present invention.

To implement the 1.5 bit comparator 300, a flash analog-to-digital converter structure is used and two latch comparators 301 and 302 can be used.

The reference voltage generated through the resistor array and the output of the analog adder 200 can be compared and analog-to-digital conversion can be performed using a three-level digital signal using the two comparators 301 and 302.

5 is a signal flow diagram of a delta-sigma modulator according to an embodiment of the present invention.

The signal flow shown in FIG. 5 is analyzed as follows.

The present invention has been described in detail with reference to preferred embodiments. It will be apparent to those skilled in the art that the present invention is not limited to the embodiments described above and that various modifications and changes may be made by one of ordinary skill in the art without departing from the scope of the present invention, It is to be understood that the technical idea of the present invention extends to the extent possible.

Claims

An integrating unit having a multi-bit and a feedforward structure and outputting an integral value with respect to an input value;
An adder for summing the outputs of the integrating unit feed-forwarded; And a comparator for analog-to-digital converting the summed signal in the adder,
Wherein the integrator comprises an inverter-based integrator,
Wherein the adder comprises an analog adder for summing the outputs of the integrator that are fed forward,
Wherein the comparator comprises a 1.5 bit comparator for analog to digital conversion of the summed signal in the adder and the 1.5 bit comparator comprises a two latch comparator and is a flash analog to digital converter structure. Modulator.

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