JP2010171484A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology where characteristics of a transfer function of signal do not have frequency dependency, capable of making an adder at input of a quantifying device unnecessary at a multi-bit delta-sigma modulator. <P>SOLUTION: A delta sigma version A/D converter 1 adds a signal multiplied by gain of a feed forward factor k and a signal obtained from an input signal of one period delayed (Z<SP>-1</SP>) clock signal and multiplied by a gain factor c-k, as a feed forward path of input signal X. The converter 1 performs the addition as an input of an integrator 8. According to the feed forward path of input signal X, the integrator 8 can have original integration facility and a summer, as well as buffer facility for input signals, as shown in Fig.2. Thereby, the same effect can be acquired as the input signal X is directly added to a quantifying device input. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a highly accurate signal conversion technique in an A / D (Analog / digital) converter, and more particularly to a technique effective for improving transfer characteristics by a delta-sigma modulator.

  Some semiconductor integrated circuit devices include an A / D converter that converts an analog input signal into a digital signal. As one of the A / D converters, for example, there is one using a first-order delta-sigma modulator shown in FIG.

  The first-order delta-sigma modulator 100 includes a feedback DA converter 101, an integrator 102, and a comparator 103 as shown in the figure. Here, when the analog input signal is VIN, the quantization noise generated when quantizing by the comparator is Q, and the modulator output signal is VDS, the following relationship is known. Here, the integrator is described as a function, and z in the equation represents the z function. Q is generally expressed as white noise.

From the above equation, it can be seen that the signal VIN is a signal delayed by one sampling frequency, does not change anything, and the quantization noise Q is multiplied by the term (1-z ⁻¹ ) and can be expressed by a first-order differentiation. Here, when the sampling frequency fs and the frequency are expressed as f, it is known that the following equation holds.

  That is, the low frequency region has a value close to 0 and can be expressed by a sine wave that is maximum at fs / 2. That is, quantization noise due to delta-sigma modulation is unevenly distributed around fs / 2, and if high-frequency noise is removed by the digital filter in FIG. 10, the energy of the quantization noise is reduced and the AD conversion result with high resolution is obtained. Is known to be possible.

  Furthermore, by connecting the integrators in multiple stages, the noise transfer function of Equation 2 is raised to the power of the integrator order, increasing the effect of unevenly distributing the quantization noise around fs / 2, and high at a low oversampling rate. A signal / quantization noise ratio can be obtained.

  In addition, this type of A / D converter includes a feedforward type delta-sigma type A / D converter for suppressing the output amplitude of the integrator, particularly the first integrator having high sensitivity. A feed forward path is added by a third integrator input (for example, see Non-Patent Document 1), or outputs of all integrators are added by a quantizer, and an input signal is also added by a quantizer (for example, And non-patent document 2).

  Furthermore, in the multibit-delta sigma A / D converter, it is possible to achieve high accuracy and wide bandwidth without increasing the oversample ratio or the order of the analog integrator (see Non-Patent Document 3). It has been known.

Coban et al., "A New Forth-Order Single-Loop Delta-Sigma Modurator for Audio", IEEE ISCAS '96, vol.1, pp461-464, May, 1996 Richard Schreier, G.C.Temes, "Understanding Delta-Sigma Data Converters", IEEE Press, pp122, 2005 Richard Schreier, G.C.Temes, "Understanding Delta-Sigma Data Converters", IEEE Press, pp179-181, 2005

  However, the present inventors have found that the analog / digital conversion technology using the delta-sigma modulator as described above has the following problems.

  That is, in the delta-sigma modulator of Non-Patent Document 1, the signal transfer function has frequency dependence, and the gain increases. For this reason, it is necessary to lower the noise transfer function gain in order to maintain the stability, which causes a problem of lowering the SNR (Signal to Noise Ratio).

  Further, in the delta-sigma modulator according to Non-Patent Document 2, an adder is arranged at the quantizer input, and in the case of a multi-bit quantizer, it is necessary to provide a charge addition circuit in the addition amplifier or the comparator. There is a problem that the layout area increases and the power consumption increases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique in which a signal transfer function characteristic does not have frequency dependence in a multi-bit delta sigma modulator, and an adder at a quantizer input is not necessary.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention provides a delta-sigma type A / D converter having first to nth (n ≧ 2) integrators and a quantizer that converts an input signal into a digital signal and quantizes the digital signal. The A / D converter includes: a feedforward path that feeds forward an input signal input to the A / D converter to an input of an nth integrator that is a final stage; A feedback path for feeding back the quantizer output signal of the A / D converter to an input of the nth integrator, and the feedforward path includes a signal obtained by multiplying the input signal by the first coefficient and an arbitrary signal A signal obtained by multiplying the input signal delayed by the clock period and the signal multiplied by the second coefficient is output, and the feedback path outputs a signal obtained by multiplying the output signal delayed by an arbitrary period by the third coefficient, The nth integrator is the input signal Is made of than not delay constitutes a.

  Moreover, the outline | summary of the other invention of this application is shown briefly.

  According to the present invention, the feedforward path includes a first delay circuit that outputs an input signal with an arbitrary delay, and a first gain that is output by multiplying a signal delayed by the delay circuit by a first coefficient; A second gain that is output by multiplying the input signal by a second coefficient, and an adder that adds the signals output from the first and second gains.

  Further, according to the present invention, the feedback path outputs a second delay circuit that outputs an output signal with an arbitrary delay, and outputs a signal obtained by multiplying the signal delayed by the second delay circuit by a third coefficient. And a D / A converter that converts the digital signal output from the third gain into an analog signal.

  In the present invention, the first delay circuit delays the input signal by one period of the clock signal.

  Furthermore, in the present invention, the first to (n-1) -th integrators are configured to delay an input signal at an arbitrary period.

  In the present invention, the first delay circuit delays the input signal by a half cycle of the clock signal.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the signal transfer function characteristics do not have frequency dependence and the gain can be 1, stable SNR can be realized.

  (2) Since an adder connected to the input unit of the quantizer can be eliminated, the circuit area can be reduced and the power consumption can be reduced.

It is a circuit diagram which shows an example of the circuit structure of the delta-sigma type A / D converter by Embodiment 1 of this invention. FIG. 2 is a circuit diagram illustrating an example of a circuit configuration of a final-stage integrator provided in the delta-sigma A / D converter of FIG. 1. It is a circuit diagram which shows an example of the 3rd-order delta-sigma modulator which is one system of the feedforward type which this inventor examined. It is explanatory drawing which shows an example of the absolute value of the signal transfer function in the delta-sigma modulator of FIG. FIG. 6 is a circuit diagram showing another example of a third-order delta-sigma modulator examined by the present inventors. FIG. 6 is an explanatory diagram illustrating a circuit configuration example of an adder and a quantizer when the delta-sigma modulator of FIG. 5 is n-order. It is explanatory drawing which shows an example of the absolute value of the signal transfer function in the delta-sigma type A / D converter of FIG. It is a circuit diagram which shows an example of the circuit structure of the delta-sigma type A / D converter by Embodiment 2 of this invention. It is a circuit diagram which shows an example of the circuit structure of the delta-sigma type A / D converter by Embodiment 3 of this invention. It is explanatory drawing which shows an example of the A / D converter using the 1st-order delta-sigma modulator which this inventor examined.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a circuit diagram showing an example of a circuit configuration of a delta-sigma A / D converter according to Embodiment 1 of the present invention, and FIG. 2 is a final diagram provided in the delta-sigma A / D converter of FIG. FIG. 3 is a circuit diagram illustrating an example of a third-order delta-sigma modulator, which is one of the feedforward types studied by the present inventors, and FIG. FIG. 5 is an explanatory diagram showing an example of an absolute value of a signal transfer function in the delta sigma modulator of FIG. 3, FIG. 5 is a circuit diagram showing another example of a third-order delta sigma modulator examined by the present inventor, and FIG. FIG. 7 is an explanatory diagram showing a circuit configuration example of an adder and a quantizer when the delta sigma modulator of FIG. 5 is n-th order, and FIG. 7 is a signal transfer function in the delta sigma type A / D converter of FIG. It is explanatory drawing which shows an example of the absolute value of.

  In the first embodiment, the delta-sigma A / D converter 1 is used as an A / D converter of a semiconductor integrated circuit device used for, for example, automobile engine control.

  As shown in FIG. 1, the delta sigma A / D converter 1 includes subtractors 2 to 4, an adder 5, integrators 6 to 8, a quantizer 9, and a D / A (Digital / Analog) converter 10. 11, feedback gain 12, feedforward gains 13 and 14, delay circuits 15 and 16, and gains 17 to 20.

  An analog input signal X is input to one input unit of the subtracter 2, the input unit of the delay circuit 15 as the first delay circuit, and the input unit of the feedforward gain 14 serving as the second gain. Are connected to each. The input unit of the integrator 6 is connected to the output unit of the subtractor 2, and one input unit of the subtracter 3 and the input unit of the feedforward gain 13 are connected to the output unit of the integrator 6. It is connected.

  The output unit of the subtractor 3 is connected to the input unit of the integrator 7, and the output unit of the integrator 7 is connected to the input unit of the gain 17. The delay circuit 15 has an output section connected to an input section of a gain 18 serving as a first gain. The output section of the gain 18 and the output section of the feedforward gain 14 have different inputs of the adder 5. Each part is connected.

  Different input units of the subtractor 4 are connected to the output unit of the adder 5, the output unit of the gain 17, the output unit of the feedforward gain 13, and the output unit of the D / A converter 11. The output unit of the subtractor 4 is connected to the input unit of the integrator 8. The output unit of the integrator 8 is connected to the input unit of the gain 20 and the input unit of the feedback gain 12. .

  Further, the other input section of the subtractor 3 is connected to the output section of the feedback gain 12. The input unit of the quantizer 9 is connected to the output unit of the gain 20, and the input unit of the D / A converter 10 is connected to the input unit of the quantizer 9.

  The other input part of the subtracter 2 is connected to the output part of the D / A converter 10. The output unit of the quantizer 9 becomes the output unit of the delta-sigma A / D converter 1, and the digital output signal Y is output.

  The subtractor 2 calculates the difference between the analog input signal X and the analog signal output from the D / A converter 10. The integrator 6 integrates the calculation result of the subtracter 2. The subtractor 3 calculates a difference between the integration result of the integrator 6 and a value obtained by multiplying the integration result of the integrator 8 by the feedback gain 12 by an arbitrary feedback coefficient (g).

The integrator 7 integrates the calculation result of the subtracter 3. The gain 17 multiplies the integration result of the integrator 7 by an arbitrary gain coefficient (b) and outputs the result. The delay circuit 15 delays the input signal X for a period of Z ⁻¹ (one cycle of the clock signal) and outputs it to the gain 18.

  The feedforward gain 14 multiplies the input signal X by an arbitrary feedback coefficient (k that is the second coefficient). The feedforward gain 13 multiplies the integration result of the integrator 6 by an arbitrary feedforward coefficient (a) and outputs the result.

  The gain 18 is multiplied by an arbitrary feedback coefficient (c−k serving as the first coefficient) and output. The adder 5 adds the calculation result of the gain 18 and the calculation result of the feedforward gain 14 and outputs the result to the subtractor 4.

  The subtractor 4 calculates the difference between the calculation result of the adder 5, the calculation result of the gain 17, the calculation result of the feedforward gain 13, and the calculation result of the D / A converter 11. The integrator 8 integrates the calculation result of the subtracter 4.

  The feedback gain 12 multiplies the integration result of the integrator 8 by an arbitrary feedback coefficient (g). The gain 20 multiplies the integration result of the integrator 8 by an arbitrary gain coefficient (d). The quantizer 9 converts the signal input through the gain into a digital output signal Y and quantizes it.

The D / A converter 10 converts the digital signal output from the quantizer 9 into an analog signal. The delay circuit 16 as the second delay circuit delays the digital signal output from the quantizer 9 for a period of Z ⁻¹ (one cycle of the clock signal) and outputs the delayed signal.

  The gain 19 as the third gain is output by multiplying the delay signal output from the delay circuit 16 by an arbitrary gain coefficient (c serving as the third coefficient). The D / A converter 11 converts a digital signal input via the gain 19 into an analog signal.

  Further, as shown in FIG. 2, the integrator 8 includes switches SW <b> 1 to SW <b> 6 that operate with a clock signal φ <b> 1 (shown below in FIG. 2), and SW <b> 7 that operates with a clock signal φ <b> 2 (shown below in FIG. 2). It comprises SW12, D / A converter DAC, capacitance elements C1 to C5, Cs, and amplifier ap.

  The inputs of the integrator 8 are an analog input signal X, an output of the integrator 6, and an output of the integrator 7. The integrator 8 generates values corresponding to the coefficients a, b, c, k in FIG. 1 by the ratio of the capacitance elements C1, C2, C3, C4, C5 and the capacitance element Cs.

  Since the adder is composed of a switched capacitor circuit, it operates on the same circuit as the integrator, so that a special operational amplifier for the adder can be dispensed with.

  Here, an example of a third-order delta-sigma modulator, which is a feedforward type system studied by the present inventors, will be described with reference to FIG.

  As shown, the delta sigma modulator 54 includes integrators 55 to 57, a quantizer 58, subtractors 59 to 61, D / A converters 62 and 63, feed forward gain 64, gains 65 to 67, and feedback. It consists of a gain 68.

  The analog signal X is input to the delta sigma modulator 54, and the digital output signal Y is output. Integrators 55 to 57 are arranged in three stages in series, and a quantizer 58 that converts an analog signal into a digital signal is provided at the final stage.

  The quantizer 58 generally has a 1-bit one and a resolution of about 2 to 5 bits called multi-bit. The outputs of the integrator 55 and the integrator 56 are multiplied by arbitrary gains (a, b), added to the input of the integrator 57, and used as the input of the quantizer 58.

  The feedback path from the integrator 57 to the input of the integrator 56 is for giving a zero point to the noise transfer function.

  The delta-sigma modulator 54 is characterized in that each integrator feedforward path is added at the input of the integrator 57. Thus, the output of the integrator 57 is directly input to the quantizer 58 without providing an adder in the previous stage of the quantizer 58.

This has a great effect when the quantizer 58 has a multi-bit configuration. In the case of a multi-bit configuration, normally, a quantizer uses a flash type that arranges 2 ^M comparators (M is the number of quantizer bits) and performs A / D conversion in one clock. This is because in a delta-sigma modulator, the delay of the quantizer affects the stability, and a flash type with a small delay is generally used.

  At this time, if an adder is required for the quantizer, it is necessary to use an addition amplifier or use a capacitively coupled charge adding circuit as many as the number of comparators, which is disadvantageous in terms of power and area. Further, the output of the integrator 55 is a differentiation of the input signal, and for a signal frequency sufficiently lower than the sampling frequency, the input signal is hardly visible at the output of the integrator 55, and is a signal obtained by integrating quantization noise. Becomes dominant.

  The method of the delta-sigma modulator 54 is known to increase the gain on the high frequency side as shown in FIG. This is an area outside the normal signal band, but when a signal with a frequency that becomes the gain peak of the signal transfer function is input, it seems that an excessive signal is input to the quantizer, which may make the loop unstable. There is.

  Further, in order to make the loop stable with respect to an arbitrary frequency, it is necessary to lower the gain of the noise transfer function and make the loop stable, resulting in a factor of deteriorating the SNR.

  FIG. 5 shows another example of a third-order delta-sigma modulator investigated by the present inventors.

  As shown, the delta sigma modulator 69 includes integrators 70 to 72, a quantizer 73, subtracters 74 and 75, an adder 76, a D / A converter 77, feedforward gains 78 and 79, a gain 80, And a feedback gain 81.

  In this case, the outputs of all the integrators 70 to 72 are added at the input of the quantizer 73, and the input signal X is also added at the preceding stage of the quantizer 73. In this configuration, since the input signal X is directly quantized, unlike the delta sigma modulator 54 shown in FIG. 3, the transfer function of the signal is 1 and has no gain.

  However, since it is necessary to add in the previous stage of the quantizer 73, in the multi-bit configuration, it is necessary to configure an adder amplifier in the adder or a charge adder at the input of each comparator in the quantizer 73. It is difficult to increase the area, which is disadvantageous in terms of power consumption.

  FIG. 6 is an explanatory diagram showing a circuit configuration example of the adder 76 and the quantizer 73 when the delta-sigma modulator 69 of FIG.

The adder 76 is operated by a switch SW50 _{1 to} SW50 _{n + 1} , SW51, SW54 operated by a clock signal φ1 (shown in the lower part of FIG. 6), and SW52 ₁ to SW52 operated by a clock signal φ2 (shown by the lower part of FIG. 6). _n + 1, SW53, and a capacitive element _{C50 1 ~C50 n + 1, C0} , and an operational amplifier OP50. The quantizer 73 includes a voltage generator VR that generates a reference voltage, 2 ^M comparators CP _{1 to} CP _M , and an encoder ENC.

  The analog input signal X and the outputs of the integrators 70 to 72 are added by an adder 76 using an operational amplifier OP50, and converted to a digital value by a quantizer 73 at the subsequent stage. The quantizer of the delta sigma modulator is often a flash type with a small delay.

  Thus, in the case of the configuration using the adder 76 in front of the quantizer 73, the operational amplifier OP50 is required as shown in FIG. 6, and the current consumption and area of the operational amplifier OP50 are problematic. It was.

  However, as described above, in the integrator 8 shown in FIG. 2, since the adder is configured by a switched capacitor circuit, it is only necessary to have a capacitive element that functions as an adder, and the circuit operates as the same circuit as the integrator. Therefore, a special operational amplifier for the adder can be dispensed with.

  Next, the operation of the delta-sigma A / D converter 1 according to this embodiment will be described.

The delta-sigma A / D converter 1 uses, as a feedforward path of the input signal X, a gain coefficient c to an input signal obtained by multiplying a gain multiplied by a feedforward coefficient k and a clock signal by one cycle delay (Z ⁻¹ ). Signals multiplied by −k are added and added as an input of the integrator 8.

  By the feedforward path (feedforward gain 14, gain 18, delay circuit 15, and adder 5) of the input signal X, the integrator 8 has an original integration function, an adder, The input signal buffer function can also be provided, and the same effect can be obtained as when the input signal X is added directly to the quantizer input.

  The signal transfer function STF (z) of the delta-sigma A / D converter 1 is as follows.

  Here, when k = 1 / d and a bg value satisfying 3-bg≈3 is selected, STF (Signal Transfer Function) = 1 and the frequency dependency is lost. The coefficient multiplication bg is a coefficient for constructing a zero point in the noise transfer function in an actual design. When the oversampling rate is sufficiently high, it is a value of about 0.01 or less, and 3-bg≈3 There is no problem.

  FIG. 7 is an explanatory diagram illustrating an example of a signal transfer function in the delta-sigma A / D converter 1. As shown in the figure, it is apparent that the transfer function has almost no frequency dependence and is 1 time (0 dB). The signal transfer function is the same as that of the delta sigma modulator 69 shown in FIG. 5, and the digital output signal Y can be expressed by the following equation.

  Here, NFT (z) is a noise transfer function, and Q is quantization noise generated by the quantizer.

  Therefore, since only the quantization noise component is input to the integrator 6 and the integrator 7 and the calculation is performed, it is possible to obtain an effect that distortion due to input hardly occurs.

  In addition, since the outputs of the integrators 6 and 7 are mostly signals obtained by integrating quantization noise, in the case of a multi-bit quantizer, the signal amplitude is small, the integrator is not easily distorted, and the settling time and slew rate of the integration amplifier are also reduced. It can be mitigated.

  As described above, the configuration using the delta-sigma A / D converter 1 is characterized in that since only the quantization noise component is input to the integrators 6 and 7 and calculation is performed, distortion due to input is less likely to occur. In addition, since most of the signals obtained by integrating the quantization noise are also output from the integrators 6 and 7, in the case of a multi-bit quantizer, the signal amplitude is small, the integrator is not easily distorted, and the settling time and slew rate of the integrating amplifier are reduced. Can also be eased.

  Thus, according to the first embodiment, the gain can be set to 1 without the signal transfer function having frequency dependence. Therefore, if the gain of the noise transfer function that is stable at the maximum input signal amplitude is set. It is possible to reduce the decrease in SNR.

  In addition, since an adder is not required at the input section of the quantizer 9, the layout area and power consumption can be reduced.

  Further, since only the quantization noise component is input to the integrator 7 and the integrator 8 and the calculation is performed, distortion due to the input is hardly generated, and the calculation can be performed with high accuracy. Since most of these outputs are integrated signals with quantization noise, the signal amplitude is small, the integrator is not easily distorted, and the settling time and slew rate of the integrating amplifier can be reduced.

(Embodiment 2)
FIG. 8 is a circuit diagram showing an example of a circuit configuration of the delta-sigma A / D converter according to the second embodiment of the present invention.

  In the first embodiment, a third-order delta-sigma A / D converter having three or more integrators has been described. For example, as shown in FIG. 8, a second-order, fourth-order, or fifth-order or more, etc. The present invention can be applied to an n-th order delta-sigma A / D converter.

The n-th order delta-sigma A / D converter 1a includes subtractors 2 to 4, adder 5, n integrators 21 _{1 to} 21 _n , quantizer 9, D / A converters 10 and 11, and feedback. The gain 12 includes n-2 feedforward gains 13 _{1 to} 13 _n-2 , a feedforward gain 14, delay circuits 15 and 16, and gains 17 to 20.

In this case, the output of the subtractor 2, the input of the integrator 21 ₁ is connected. Further, between the integrator 21 ₁ and the subtractor 3, integrators 21 _{2 to} 21 _n-2 are connected in series. Further, input portions of feedforward gains 13 _{1 to} 13 _n-2 are respectively connected to output portions of the integrators 21 _{1 to} 21 _n-2 , and outputs of these feed forward gains 13 _{1 to} 13 _n-2 are respectively connected. The different input sections of the subtracter 4 are connected to the sections.

Further, the output of the integrator 21 _n-2, is connected to one input of the subtracter 3, the output of the subtracter 3, the input of the integrator 21 _n-1 are connected ing. An input section of gain 17 is connected to the output section of this integrator 21 _n-1 . The output unit of the subtracter 4 is connected to the input unit of the integrator 21 _n .

  Since other connection configurations and operations are the same as those in FIG. 1 of the first embodiment, description thereof is omitted.

As described above, the integrator 21 _n in the preceding stage of the quantizer 9 is configured as an adder / integrator of the outputs of the integrators 21 ₁ to 21 _n−1 , and the input signal X is input to the integrator 21 _n. Therefore, it can be applied if the order n satisfies n ≧ 2 without depending on the order of the delta-sigma.

(Embodiment 3)
FIG. 9 is a circuit diagram showing an example of a circuit configuration of the delta-sigma A / D converter according to the third embodiment of the present invention.

In the third embodiment, as shown in FIG. 9, the delta sigma type A / D converter 1b includes subtracters 2 to 4, adders 5, and n pieces as in FIG. 8 of the second embodiment. Integrators 211 to 32n, quantizer 9, D / A converters 10 and 11, feedback gain 12, n-2 feed forward gains 13 _{1 to} 13 _n -2, feed forward gain 14, delay circuits 15 and 16 , And a gain of 17 to 20, differing from the delta sigma type A / D converter 1a of the second embodiment except that the input delay of the delay circuit 15 is Z ⁻¹ (one cycle of the clock signal). It is not a delay but Z ^−0.5 (clock signal 0.5 period delay).

  In this way, even if the delay is half the sampling time, although there is an increase in STF gain in the high frequency region, the increase in STF gain can be suppressed more than in the delta-sigma modulator 54 of FIG.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a highly accurate A / D conversion technique in a multi-bit delta-sigma modulator.

DESCRIPTION OF SYMBOLS 1 Delta sigma type A / D converter 1a Delta sigma type A / D converter 1b Delta sigma type A / D converter 2 Subtractor 3 Subtractor 4 Subtractor 5 Adder 6 Integrator 7 Integrator 8 Integrator 9 Quantum 10 D / A converter 11 D / A converter 12 Feedback gain 13 Feed forward gain 13 _{1 to} 13 _n-2 Feed forward gain 14 Feed forward gain 15 Delay circuit 16 Delay circuit 17 Gain 18 Gain 19 Gain 20 Gain 21 ₁ through 21 _n integrators 54 delta-sigma modulator 55 integrator 56 integrator 57 integrator 58 quantizer 59 to 61 subtractor 62 and 63 D / A converter 64 feed forward gain 65 to 67 gain 68 feedback gain 69 delta Sigma modulators 70 to 72 Integrator 73 Quantizers 74 and 75 Subtractor 76 Adder 77 D A converters 78 and 79 Feed forward gain 80 Gain 81 Feedback gain 100 First-order delta-sigma modulator 101 Feedback DA converter 102 Integrator 103 Comparator SW1 to SW12 Switch C1 to C5 Capacitance element Cs Capacitance element DAC D / A converter ap amplifier SW50 _{1 to} SW50 _{n + 1} switch SW51, SW53, SW54 switch SW52 _{1 to} SW52 _{n + 1} switch C50 _{1 to} C50 _{n + 1} capacitance element C0 capacitance element OP50 operational amplifier VR voltage generation part CP ₁ ~ CP _M comparator ENC encoder

Claims (7)

A semiconductor integrated circuit including a delta-sigma type A / D converter having first to nth (n ≧ 2) integrators and a quantizer that converts an input signal into a digital signal and quantizes it A circuit device,
The A / D converter is
A feedforward path for feeding forward an input signal input to the A / D converter to an input of the nth integrator which is the final stage;
A feedback path for feeding back an output signal of the A / D converter to an input of the nth integrator;
The feedforward path is
A signal obtained by multiplying the input signal multiplied by the first coefficient and the input signal delayed by an arbitrary clock period and the signal multiplied by the second coefficient,
The feedback path is
Output a signal obtained by multiplying the output signal delayed by an arbitrary period by the third coefficient,
The nth integrator is
A semiconductor integrated circuit device characterized in that an input signal is not delayed. The semiconductor integrated circuit device according to claim 1.
The feedforward path is
A first delay circuit for arbitrarily delaying and outputting an input signal;
A first gain output by multiplying a signal delayed by the delay circuit by a first coefficient;
A second gain that is output by multiplying the input signal by a second coefficient;
A semiconductor integrated circuit device comprising an adder for adding signals output from the first and second gains. The semiconductor integrated circuit device according to claim 1 or 2,
The feedback path is
A second delay circuit for arbitrarily delaying and outputting the output signal;
A third gain output by multiplying the signal delayed by the second delay circuit by a third coefficient;
A semiconductor integrated circuit device comprising: a D / A converter that converts a digital signal output from the third gain into an analog signal. The semiconductor integrated circuit device according to claim 2 or 3,
The first delay circuit includes:
A semiconductor integrated circuit device, wherein an input signal is delayed by one cycle of a clock signal. The semiconductor integrated circuit device according to claim 2 or 3,
The first delay circuit includes:
A semiconductor integrated circuit device, wherein an input signal is delayed by a half period of a clock signal. In the semiconductor integrated circuit device according to claim 1,
The first to (n-1) -th integrators delay an input signal at an arbitrary period. The semiconductor integrated circuit device according to any one of claims 1 to 6,
An output signal from the first to (n-1) -th integrators is input to an input of the n-th integrator.

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