KR101887808B1 - Analog to digital converter - Google Patents

Abstract

An analog-to-digital conversion apparatus according to the present invention includes an analog-to-digital converter; a digital-to-analog converter for converting the output of the analog-to-digital converter into an analog signal; a first calculation part for calculating an input signal and the output of the digital-to-analog converter; a loop filter for filtering the output of the first calculation part; a switching circuit for providing an input signal as an input of an analog to digital converter in a first mode and providing the output of the loop filter as the input of the analog to digital converter in a second mode; and a digital filter for filtering the output of the analog-to-digital converter. It is possible to change an operating mode selectively.

Description

ANALOG TO DIGITAL CONVERTER [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog-to-digital converter, and more particularly, to an analog-to-digital converter that performs analog-to-digital conversion in different modes according to modes.

1 is a block diagram showing an analog-to-digital converter (ADC) of a sigma-delta (SD) modulation method.

A sigma-delta analog-to-digital converter includes a sigma delta modulator (SDM) 10 and a decimator 20 for performing oversampling and noise shaping and can obtain a relatively high-resolution digital signal.

The sigma delta modulator 10 receives the analog input signal A and outputs a digital modulated signal DM.

At this time, the frequency component corresponding to the noise is shaped outside the signal band.

The decimator 20 removes a noise component outside the signal band in the digital modulated signal DM through filtering to output a digital signal D.

Figure 2 is a block diagram illustrating the sigma delta modulator of Figure 1;

The sigma delta modulator 10 includes an operation unit 11, a loop filter 12, an analog-to-digital converter 13, and a digital to analog converter (DAC) 14.

The operation unit 11 subtracts the output of the digital-to-analog converter 14 from the analog signal A and outputs the subtracted result.

The loop filter 12 filters the output of the arithmetic unit 11 and outputs the filtered result.

The analog-to-digital converter 13 converts the output of the loop filter 12 into a digital signal and outputs the digital modulated signal DM.

The digital-to-analog converter 14 converts the digital modulated signal DM output from the analog-to-digital converter 13 into an analog signal and outputs it.

The sigma-delta analog-to-digital converter of this structure is advantageous in that it can perform high-resolution digital conversion, but has a disadvantage of relatively high power consumption.

Accordingly, when high-resolution digital conversion is not required, it is preferable to use an analog-to-digital converter using a different method instead of the sigma delta method.

Conventionally, there is a problem that the area of the system is increased and the cost is increased because different analog digital converters must be separately used according to the required performance.

US 6970118 B2 US 9419642 B1 US 20040004994 A1 US 20160182074 A1

 Yun-Shiang Shu, Liang-Ting Kuo, and Tien-Yu Lo, "An Oversampling SAR ADC with DAC Mismatch Error Shaping Achieving 105dB SFDR and 101dB SNDR over 1kHz BW in 55nm CMOS," ISSCC Dig. Tech Papers, pp. 458-460, Feb 2016.

The present invention provides a general-purpose analog-to-digital converter capable of selectively changing an operation mode.

A digital-to-analog conversion apparatus according to an embodiment of the present invention includes an analog-to-digital converter; A digital-to-analog converter for converting an output of the analog-to-digital converter into an analog signal; A first calculator for calculating an input signal and an output of the digital-to-analog converter; A loop filter for filtering the output of the first calculation unit; A switching circuit providing an input signal to an input of an analog to digital converter in a first mode and providing an output of the loop filter to an input of an analog to digital converter in a second mode; And a digital filter for filtering the output of the analog to digital converter.

The analog-to-digital conversion apparatus according to the present invention provides a general-purpose analog-to-digital conversion apparatus capable of selectively changing an operation mode.

Accordingly, it is not necessary to mount a separate chip according to the operation method, thereby reducing the area of the system and reducing the manufacturing cost of the system.

The analog-to-digital conversion apparatus according to the present invention operates as a delta-sigma analog-to-digital conversion apparatus when a high-resolution signal is required and operates as a low-resolution analog-digital conversion apparatus in a case where a high- .

1 is a block diagram showing a conventional analog-to-digital converter of sigma-delta modulation method;
2 is a block diagram showing the structure of a delta sigma modulator;
3 is a block diagram of an analog-to-digital converter according to an embodiment of the present invention;
4 is a circuit diagram of a temperature sensor providing a temperature signal;
5 is a detailed block diagram of an analog-to-digital converter receiving the temperature signal of FIG.
6 is a block diagram illustrating an analog-to-digital converter for performing noise shaping;
FIG. 7 is a graph showing characteristics of the analog-to-digital converter of FIG. 6;
8 is a graph illustrating the characteristics of the sigma delta modulator of FIG. 3;

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing an analog-to-digital converter according to an embodiment of the present invention.

The analog-to-digital converter according to an exemplary embodiment of the present invention includes a sigma delta modulator 100 and a digital filter 200.

The sigma delta modulator 100 includes an analog digital converter 110, a loop filter 120, a first calculator 130, a switching circuit 140, a second calculator 150, a digital-to-analog converter 160, (170), and a control unit (180).

In this embodiment, the sigma delta modulator 100 performs an analog-to-digital conversion operation according to the first mode or the second mode.

The first mode is an operation suitable for obtaining a relatively low-resolution digital signal and consumes a relatively small amount of energy.

In the first mode, the input signal A or the temperature signal T is converted into a digital signal by the analog-to-digital converter 110 without the loop filter 120 being operated.

The temperature signal T may be referred to as a second input signal as an example of a sufficient signal even if it is converted into a digital signal of a relatively low resolution.

In the illustrated embodiment, it is assumed that the temperature signal T and the input signal A are input to the switching circuit 140 through separate input ports. However, the temperature signal T is input to the input port A Lt; / RTI >

The second mode is an operation suitable for obtaining a relatively high-resolution digital signal and consumes a relatively large amount of energy.

In the second mode, the entire configuration of the sigma delta modulator 100 including the loop filter 120 is used to convert the input signal A into a digital signal.

The sigma delta modulator 100 converts the input signal A or the temperature signal T to digital in the analog-to-digital converter 110 under the control of the control unit 180 in the first mode, DM can be output.

At this time, the controller 180 controls the switching circuit 140 so that the input signal A or the temperature signal T is directly input to the analog-to-digital converter 110.

The control unit 180 deactivates the loop filter 120, the code conversion unit 170, the digital-to-analog converter 160 and the like except for the analog-digital conversion unit 110, the switching circuit 140 and the second calculation unit 150 can do.

At this time, the digital filter 200 may filter or bypass the digital modulated signal DM under the control of the controller 180 to output the digital signal D.

In this embodiment, the sigma delta modulator 110 provides the input signal A to the first calculation unit 130 under the control of the control unit 160 in the second mode.

The first calculator 130 provides the difference between the input signal A and the output signal of the digital-to-analog converter 160 to the loop filter 120.

The loop filter 120 filters and outputs the output of the first calculator 130.

The switching circuit 140 provides the output of the loop filter 120 to the second arithmetic section 150.

The switching circuit 140 may further provide the input signal A to the second arithmetic operation unit 150. [

The second calculation unit 150 calculates and outputs the signals input to the second calculation unit 150.

If the input signal A is not further provided to the second arithmetic section 150 via the switching circuit 140, the second arithmetic section 150 may be omitted and the signal provided by the loop filter 120 may be supplied to the switching circuit 140 To the analog-to-digital converter 110 via the analog to digital converter.

The analog-to-digital converter 110 converts the input analog signal X into a digital signal to output a digital modulated signal DM.

In the second mode, the digital modulated signal DM is provided to the digital filter 200 as a noise-shaped over-sampling signal.

The digital filter 200 outputs a digital signal D from which a noise component is removed through a decimation operation.

The digital modulated signal DM may be provided to the direct digital to analog converter 160 or may be input to the digital to analog converter 160 via the code conversion unit 170. [

The code conversion unit 170 may encode and output the digital modulation signal DM.

In this embodiment, the analog-to-digital converter 110 outputs a multi-bit signal in binary code form.

In this embodiment, the digital-to-analog converter 160 converts the multi-bit digital value in the form of a thermometer code into an analog value.

For example, when a 4-bit binary code is output from the analog-to-digital converter 110, the digital-to-analog converter 160 receives a 15-bit thermometer code.

The number of 1s in the thermometer code is the same as the value obtained by converting a 4-bit binary code to a decimal number.

In the present embodiment, the digital-to-analog converter 160 includes fifteen units, and each unit receives a corresponding bit in the thermometer code of 15 bits.

Each unit outputs an analog voltage in accordance with the value of the corresponding bit and the digital-to-analog converter 160 adds the output voltage of the whole unit to output the final analog voltage.

In this embodiment, the code conversion unit 170 may convert the binary code type digital signal into a thermometer code.

In this embodiment, the code conversion unit 170 includes a first code conversion unit 171 and a second code conversion unit 172 connected in series.

In the present embodiment, the first code conversion unit 171 converts the digital modulation signal DM of the binary code type output from the analog-digital converter 110 into the thermometer code form.

In this embodiment, the second code conversion unit 172 converts the thermometer code input from the first code conversion unit 171 into a digital signal, which is input from the first code conversion unit 171, in order to reduce a mismatch between a plurality of digital- 1 and 0 are arbitrarily changed and output.

Accordingly, even if the same binary code is input to the code conversion unit 170, the form of the thermometer code output according to the input time point can be changed.

In this manner, the control unit 180 controls each configuration of the sigma delta modulator 100 so that the operation corresponding to the first mode or the second mode is selected.

The controller 180 may control the operation of the digital filter 200 according to the mode.

The digital filter 200 performs the function of the decimation filter in the second mode.

The digital filter 200 outputs the digital modulated signal DM as it is or the digital modulated signal DM to the digital signal D according to the type of the A / D converter 110 in the first mode, Can be output.

When the analog-to-digital converter 110 is an analog-to-digital converter of the SAR (Successive Approximation Register) type for performing noise shaping, the digital filter 200 can perform the operation of the decimation filter to output the digital signal D.

When the analog-to-digital converter 110 is a general SAR type analog-to-digital converter, the digital filter 200 can bypass the input digital modulated signal DM and output it as a digital signal D.

4 is a circuit diagram showing an example of a temperature sensor for outputting a temperature signal.

In this embodiment, the temperature sensor has a ratio of the channel width of 1: K (K is a real number) and the gate width of the first PMOS transistor P1 and the third PMOS transistor, 2 PMOS transistor P2, a fourth PMOS transistor P4 and a first PNP transistor Q0 and a second PNP transistor Q1 whose base is commonly grounded.

The power source voltage VDD is applied to the sources of the first PMOS transistor P1 and the third PMOS transistor P3.

The drain of the first PMOS transistor P1 is connected to the source of the second PMOS transistor P2 and the drain of the third PMOS transistor P3 is connected to the source of the fourth PMOS transistor P4.

The emitter of the first PNP transistor Q0 is connected to the drain of the second PMOS transistor P2 and the emitter of the second PNP transistor Q1 is connected to the drain of the fourth PMOS transistor P4, And the collector of the second PNP transistor Q1 are commonly grounded.

In this embodiment, the sizes of the first PNP transistor Q0 and the second PNP transistor Q1 are designed to be the same, and the ratio of the currents flowing to the respective collectors is 1: K.

Accordingly, a difference occurs between the base-emitter voltage VBE0 of the first PNP transistor Q0 and the base-emitter voltage VBE1 of the second PNP transistor Q1.

In this embodiment, the temperature signal T is a first temperature signal VBE0 outputted from the emitter of the first PNP transistor Q0 and a second temperature signal VBE1 outputted from the emitter of the second PNP transistor Q1 ).

The first temperature signal VBE0 and the second temperature signal VBE1 have a differential signal form oscillating around a common voltage in accordance with a temperature change.

5 is a block diagram showing an analog-to-digital converter 110 for converting the temperature signal of Fig. 4 into a digital signal.

In this embodiment, the analog-to-digital converter 110 includes a SAR ADC 111, an SAR control unit 112, a first switching unit 113, a second switching unit 114, and an offset unit 115.

The offset unit 115 is a virtual circuit element that reflects the offset voltage VOS inherent in the circuit.

In this embodiment, the controller 180 of FIG. 3 outputs the path control signal CHOP during the temperature sensing operation in the first mode.

The path control signal (CHOP) is alternately output between "0" and "1" when temperature sensing is performed.

When the path control signal CHOP is outputted as "1 ", the first switching unit 113 and the second switching unit 114 output the input signal without changing the path of the input signal.

At this time, the digital modulated signal DM1 output from the SAR controller 112 can be expressed by Equation (1). At this time, the function f represents the function of the analog-to-digital converter 110.

When the path control signal CHOP is output as "0 ", the first switching unit 113 and the second switching unit 114 change the input signal and output it.

Accordingly, the digital modulated signal DM0 output from the SAR control unit 112 can be expressed by Equation (2).

The digital filter 200 outputs a digital signal corresponding to the temperature signal through an average value of the signals obtained from Equations (1) and (2) under the control of the controller 180. [

Accordingly, the digital signal from which the influence of the offset VOS is removed can be output.

The SAR ADC 111 and the SAR controller 112 of FIG. 5 can be realized by a conventionally known circuit technology as an analog-to-digital converter receiving a differential signal.

Accordingly, detailed description of the SAR ADC 111 and SAR control unit 112 will be omitted.

In FIG. 3, the analog-to-digital converter 110 may be implemented as an analog-to-digital converter that performs a noise shaping function.

6 is a block diagram of an analog-to-digital converter 110 that performs a noise shaping function.

The analog-to-digital converter 110 includes a quantization unit 1101, a third calculation unit 1102, a delay unit 1103, a fourth calculation unit 1104, and an amplification unit 1105.

The third arithmetic operation unit 1102 outputs a quantization error from the input / output signal of the quantization unit 1101.

The delay unit 1103 stores the quantization error generated in the process of converting the previous analog signal.

The fourth arithmetic operation unit 1104 adds a quantization error of the current input analog signal and the previous signal output from the delay unit 1103, and outputs the result. The noise shaping operation is performed by the operation of the fourth operation unit 1104.

The amplifying unit 1105 can amplify the output of the fourth calculating unit 1104. At this time, the amplification ratio can be variously adjusted according to the embodiment.

The quantization unit 1101 quantizes the output of the amplification unit 1105 and outputs it as a digital modulation signal DM.

The digital modulated signal DM output from the analog-to-digital converter 110 of FIG. 6 includes a noise component shaped to the outside of the signal band.

Accordingly, the digital filter 200 operating in the first mode can perform a decimation function.

7 is a PSD (Power Spectral Density) graph of the analog-to-digital converter 110. FIG.

This can be seen in the PSD graph of the sigma delta modulator 100 operating in the first mode.

In the graph of FIG. 7, the analog-to-digital converter 110 performs a noise shaping function.

In the noise region above 1 KHz, the noise increases by 20dB every time the frequency increases by 10 times.

That is, the analog-to-digital converter 110 performs primary noise shaping.

8 is a PSD graph of a sigma delta modulator 100 operating in a second mode.

In the noise region above 100Hz, the noise increases by 60dB every time the frequency increases by 10 times.

In this case, the loop filter 120 performs the secondary noise shaping and the digital converter 110 performs the primary noise shaping so that the sigma delta modulator 100 performs the tertiary analog shaping as a whole.

As in the experiment of FIG. 7, the effective number of bits (ENOB) is 10.75 bits in the first mode and the number of valid bits is 20.5 bits in the second mode as in the experiment of FIG.

If a relatively low-resolution digital signal is required, the analog-to-digital converter according to an embodiment of the present invention can operate in the first mode. If a relatively high-resolution digital signal is required, Can be operated in the second mode.

The embodiments of the present invention have been described with reference to the drawings. The scope of the present invention is defined not by the above disclosure but by the scope of the claims and equivalents thereof.

10, 100: sigma delta modulator
20: decimator
110: analog-to-digital converter
111: SAR ADC
112: SAR controller
113: first switching unit
114:
115: Offset
1101: Quantization unit
1102:
1103:
1104: fourth calculation section
1105:
120: Loop filter
130:
140: switching circuit
150: second arithmetic section
160: Digital-to-Analog Converter
170: code conversion section
171:
172: second code conversion section
180:
200: Digital filter
300: Temperature sensor

Claims (12)

Analog-to-digital converters;
A digital-analog converter for converting an output of the analog-to-digital converter into an analog signal;
A first calculator for calculating an input signal and an output of the digital-to-analog converter;
A loop filter for filtering the output of the first calculation unit;
A switching circuit for selecting either the input signal or the output of the loop filter to provide an input to the analog-to-digital converter, the input signal being selected in a first mode and the output of the loop filter being selected in a second mode; And
A digital filter for filtering an output of the analog-to-
, ≪ / RTI &
Wherein in the first mode, at least one of the digital-to-analog converter, the loop filter, and the first calculation unit is controlled so as not to consume power. The analog-to-digital converter of claim 1, wherein the switching circuit provides the input signal or the second input signal as an input to the analog-to-digital converter in the first mode. The analog-to-digital converter according to claim 1, wherein the analog-to-digital converter further comprises a second calculating unit, wherein the switching circuit outputs the output of the loop filter and the input signal in the second mode, Wherein the input signal and the output of the loop filter are outputted through the switching circuit and the output of the loop filter is supplied to the analog-to-digital converter. The analog-to-digital converter according to claim 1, wherein the analog-to-digital converter further comprises a code converter for converting an output digital value of the analog-to-digital converter and providing the converted digital value as an input to the digital-to-analog converter. The analog-to-digital conversion apparatus according to claim 4, wherein the code conversion unit includes a first code conversion unit that converts a digital value in a binary code form into a digital value in a thermometer code form. 6. The digital-analog converter according to claim 5, wherein the code conversion unit further includes a second code conversion unit for arbitrarily changing positions of 0 and 1 in the digital value of the thermometer code type output from the first code conversion unit, Comprising an analog-to-digital converter. The analog to digital converter of claim 1, wherein the analog to digital converter performs noise shaping and the digital filter performs decimation filtering in the first mode. The analog-digital converter according to claim 1, wherein the analog-to-digital converter does not perform noise shaping and the digital filter outputs the same signal as the signal input in the first mode. The analog-to-digital converter of claim 1, wherein the loop filter performs noise shaping and the digital filter performs decimation filtering in the second mode. delete The analog-to-digital conversion apparatus according to claim 1, further comprising a control section for controlling the switching circuit, the loop filter, and the digital-analog converter in the first mode and the second mode. The analog-to-digital converter according to claim 2, wherein the temperature signal is provided as the input signal or the second input signal in the first mode.

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