JP2017147712A - AD converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-resolution successive comparison type A/D converter having higher order noise shaping characteristics.SOLUTION: An AD converter (100) includes a common node to which an analog input voltage is input, a capacitance DAC (2) having a plurality of capacitive elements (201 to 205), a comparator (3) for comparing the voltage of the common node with a comparison reference voltage, a successive comparison control circuit (4) for determining a successive comparison control signal of a next bit from a comparison result of the comparator (3), and an integrator (8) for integrating a residual voltage and setting the integral value as a comparison reference voltage for a next sampling. The integrator (8) comprises a plurality of cascade-connected integrator circuits (12, 14, 16), and at least one feedforward path (FF1, FF2) for sampling the residual voltage and inputting the sampled residual voltage to any one of the second or subsequent integration circuits out of the plural integration circuits.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to an AD converter.

  A noise shaping type successive approximation AD converter has been proposed as a technique for achieving high resolution like a ΔΣ type AD converter while maintaining the low power consumption performance of the successive approximation type AD converter (for example, non-patented). Reference 1). The noise shaping type successive approximation AD converter has a configuration in which an integration circuit is added to a normal successive approximation AD converter. The noise shaping characteristic can be obtained by integrating the residual voltage of the capacitor DAC after performing the successive approximation operation up to LSB and feeding it back to the next sampling.

J. et al. A. Fredenburg, M.M. P. Flynn, “A 90-MS / s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC,” IEEE J. et al. Solid-State Circuits, vol. 47, no. 12, pp. 2898-2904, Dec, 2012.

  The present disclosure provides an AD converter that can achieve high resolution.

The AD converter in one aspect of the present disclosure is:
A common node to which the analog input voltage is input;
A capacitive DAC including a plurality of capacitive elements, one end of each capacitive element being connected to the common node, and the other end being selectively connected to one of the first and second voltages according to a successive approximation control signal; ,
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The integrator is
A plurality of cascaded integrator circuits;
The residual voltage is sampled and provided with at least one feed forward path that is input to any one of the plurality of integration circuits in the second and subsequent stages.

  The AD converter according to the present disclosure can achieve high resolution.

It is a figure showing an example of composition of an AD converter concerning a comparative example of this indication. It is a wave form diagram which shows an example of the change of the output voltage of capacity | capacitance DAC in a successive approximation operation. It is a signal flow figure which shows the operation | movement of AD converter shown in FIG. It is a figure which shows an example of a structure of the AD converter in Embodiment 1 of this indication. It is a figure which shows an example of the timing diagram of the integrator shown in FIG. FIG. 5 is a signal flow diagram illustrating an operation of the AD converter illustrated in FIG. 4. It is a signal flow diagram of the AD converter when the integrator is configured by an integrator having a second-order noise shaping characteristic. It is a graph which shows the AD conversion output spectrum when not performing noise shaping, but performing 1st, 2nd, 3rd order noise shaping. It is a graph which shows the frequency characteristic of NTF (noise transfer function) at the time of performing 1st, 2nd, 3rd order noise shaping. It is a figure which shows an example of a structure of the integrator which performs a 3rd-order integration with one operational amplifier. It is a figure which shows an example of a structure of the AD converter in Embodiment 2 of this indication. It is explanatory drawing of operation | movement of split type capacity | capacitance DAC. It is a wave form diagram showing transition of the output voltage from split type capacity DAC. It is a graph which shows an example of the power spectrum at the time of not employ | adopting DEM. It is a graph which shows an example of the power spectrum of the AD converter in Embodiment 2 of this indication, and is a graph at the time of employ | adopting DEM.

(Background to inventing one aspect of the present disclosure)
In the analog front end of a sensor system that handles weak signals such as biological signals, the high resolution of the AD converter reduces the amplification factor of the analog amplifier provided in the previous stage of the AD converter and does not require the analog amplifier itself. The advantages as described above can be obtained. However, increasing the resolution of the AD converter generally requires a reduction in noise, so an increase in power consumption is inevitable. Since it is expected that the sensor system will be further reduced in size and power consumption in the future, a high-resolution AD converter is also required to operate at a low power.

  There are various architectures for AD converters, and they are properly used according to the required specifications. The successive approximation AD converter sequentially repeats a comparison operation between an analog input voltage and a voltage generated by a digital-analog converter (hereinafter referred to as a DAC) from the most significant bit, thereby converting a multi-bit digital signal. obtain. Therefore, it is an architecture that can be configured only by a comparator, a DAC, and a simple digital circuit, and is the most compact and low power consumption. However, the successive approximation AD converter is subject to thermal noise during comparison because the voltage to be compared decreases as the resolution increases. Therefore, the successive approximation type AD converter is not suitable for a sensor system that requires high resolution.

  On the other hand, there is a ΔΣ type AD converter as one of AD converter architectures. The ΔΣ AD converter has an architecture that enables high resolution by combining noise shaping technology and oversampling technology. The noise shaping technique is a technique for providing a frequency characteristic in which the low frequency side attenuates against quantization noise by ΔΣ modulation. The ΔΣ AD converter can increase the signal-to-noise ratio by sampling the analog input voltage at a frequency sufficiently higher than the signal band (oversampling) and blocking high-frequency noise with a low-pass filter (LPF). It becomes. However, in order to achieve higher resolution, it is necessary to increase the order of ΔΣ modulation and further increase the oversampling ratio. An increase in the order causes an increase in the number of integration circuits in the ΔΣ modulator, and an improvement in the oversampling ratio requires a higher speed operation. Usually, since an operational amplifier is used for the integration circuit, an increase in the number of integrators and a high-speed operation cause a significant increase in power.

  Therefore, as described above, the noise shaping type successive approximation AD converter described in Non-Patent Document 1 has been proposed. The noise shaping type successive approximation AD converter can obtain a noise shaping characteristic by integrating the residual voltage of the capacitor DAC after performing the successive approximation operation up to LSB and feeding it back to the next sampling.

  However, in the noise shaping type successive approximation AD converter described in Non-Patent Document 1, since the order of noise shaping is first order, a significant improvement in resolution cannot be expected. Further, although an operational amplifier is used for the integrator, it is necessary to always operate it, which causes an increase in power consumption.

  In addition, improvement in resolution of the successive approximation AD converter is not only a thermal noise but also a capacitance mismatch of the DAC. Conventionally, mismatch is improved by using a method of trimming the capacitance. However, since many of the trimming methods have discrete resolutions, the trimming accuracy deteriorates as the resolution increases.

  In view of the above problems, the present disclosure is directed to a successive approximation type that suppresses noise such as quantization noise and thermal noise to increase resolution, or suppresses spurious generated due to DAC capacity mismatch to increase resolution. An AD converter is provided. In addition, the present disclosure provides a successive approximation AD converter that can reduce power consumption.

The AD converter in one aspect of the present disclosure is:
A common node to which an analog input voltage is input;
A capacitive DAC including a plurality of capacitive elements, one end of each capacitive element being connected to the common node, and the other end being selectively connected to one of the first and second voltages according to a successive approximation control signal; ,
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The integrator is
A plurality of cascaded integrator circuits;
The residual voltage is sampled and provided with at least one feed forward path that is input to any one of the plurality of integration circuits in the second and subsequent stages.

  According to this configuration, the residual voltage of the capacitor DAC after the successive approximation operation is performed up to LSB (least significant bit) is integrated by the integrator, and the integrated value is fed back as a comparison reference voltage for the next sampling.

  Here, since the integrator is composed of a plurality of cascaded integration circuits, it is possible to perform second-order or higher integration on the residual voltage. Further, since the residual voltage is supplied to the at least one integrating circuit after the second stage via the feedforward path, this integrating circuit can integrate the integrated value and the residual voltage of the preceding integrating circuit. it can.

  As a result, the residual voltage is given a high-order noise shaping characteristic and added to the analog input voltage to be sampled next. As a result, high-order noise shaping characteristics can be given to the analog input voltage. Therefore, a high-resolution successive approximation AD converter can be provided by oversampling the analog input voltage.

  In the AD converter, the integrator may include at least one feedback path that feeds back an integration value of the subsequent-stage integration circuit to the previous-stage integration circuit.

  According to this configuration, the integration value of the subsequent-stage integration circuit is fed back to the previous-stage integration circuit by the feedback path, so that the noise reduction region in the noise shaping characteristics can be expanded to the high frequency side, and the analog input that can be input The frequency band of the voltage can be extended to the high frequency side.

  In the AD converter, each integrating circuit may include an operational amplifier that is activated only when performing an integrating operation.

  According to this configuration, since the operational amplifiers constituting each integrating circuit are activated only when performing an integrating operation, power consumption can be reduced.

Further, the AD converter in another aspect of the present disclosure is:
A common node to which an analog input voltage is input;
A capacitive DAC including a plurality of capacitive elements, one end of each capacitive element being connected to the common node, and the other end being selectively connected to one of the first and second voltages according to a successive approximation control signal; ,
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The integrator is
An integration circuit that includes an operational amplifier, and that sequentially performs a plurality of stages of integration operation by sharing the operational amplifier;
At least one feedforward path that samples the residual voltage and inputs the sampled residual voltage to the integrating circuit when the integrating circuit performs at least one of the integrating operations in the second and subsequent stages. With.

  According to this configuration, the residual voltage of the capacitor DAC after the successive approximation operation is performed up to LSB (least significant bit) is integrated by the integrator, and the integrated value is fed back as a comparison reference voltage for the next sampling.

  Here, the integrator is composed of an integration circuit that sequentially performs a plurality of stages of integration operation by sharing an operational amplifier, and therefore, it is possible to perform second-order or higher integration on the residual voltage. Further, when the integration circuit performs at least one integration operation of the second and subsequent integration operations, the residual voltage is supplied to the integration circuit through the feedforward path. The integral value and the residual voltage can be integrated.

  As a result, the residual voltage is given a high-order noise shaping characteristic and added to the analog input voltage to be sampled next. As a result, high-order noise shaping characteristics can be given to the analog input voltage. Therefore, a high-resolution successive approximation AD converter can be provided by oversampling the analog input voltage.

  Furthermore, in this aspect, since the integrating circuit performs the integration operation in a plurality of stages by sharing the operational amplifier, the integrating circuit can be realized by one operational amplifier.

  In the other AD converter, the integrator feeds back an integration value of the first integration operation to the integration circuit when the integration circuit performs an integration operation following the integration operation of the first integration operation. May be provided.

  According to this configuration, when the integration circuit performs the integration operation next to the one integration operation, the integration value of the one integration operation is fed back by the feedback path, so that the noise reduction region in the noise shaping characteristic is shifted to the high frequency side. The frequency range of the analog input voltage that can be input can be extended to the high frequency side.

  In the AD converter according to another aspect, the operational amplifier may be activated only when performing an integration operation.

  According to this configuration, since the operational amplifier is activated only when performing an integration operation, power consumption can be reduced.

In addition, an AD converter according to still another aspect of the present disclosure includes:
A common node to which an analog input voltage is input;
A plurality of capacitive elements are provided, one end of each capacitive element is connected to the common node, and the other end is selected from the first voltage and the second voltage lower than the first voltage according to the successive approximation control signal Capacitively connected capacitor DAC;
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The capacitor DAC is composed of a split capacitor DAC including a plurality of first capacitor elements that increase the output voltage of the capacitor DAC and a plurality of second capacitor elements that decrease the output voltage.
The successive approximation control circuit includes:
In the initial state of successive approximation, all the first capacitive elements are connected to the second voltage, and all the second capacitive elements are connected to the first voltage,
When increasing the output voltage of the capacitor DAC in the successive comparison of the next bit, the first pointer is virtually moved along the arrangement direction of the plurality of first capacitor elements, and the second voltage is changed to the first voltage. Determining the first capacitive element to switch connection;
When lowering the output voltage of the capacitor DAC in the successive approximation of the next bit, the second pointer is virtually moved along the arrangement direction of the plurality of second capacitor elements, and the first voltage is changed to the second voltage. Determine the second capacitive element to be switched,
When the sequential comparison of the least significant bit is completed, all the first capacitive elements are connected to the second voltage while maintaining the positions of the first and second pointers, and all the second capacitive elements are Connect to the first voltage.

  According to this configuration, when the successive comparison of the least significant bit is completed, the capacitance DAC is reset while maintaining the positions of the first and second pointers. The movement of the two pointers is started. Therefore, even if a plurality of first and second capacitive elements are used without deviation and a capacitive mismatch occurs in the capacitive element of the split type capacitive DAC, spurious can be suppressed without generating fixed pattern noise. As a result, a high-resolution AD converter can be provided.

  In the AD converter according to another aspect, the successive approximation control circuit may determine whether or not it is necessary to increase the output voltage of the capacitor DAC from the comparison result of the comparator.

  In the AD converter according to another aspect, the successive approximation control circuit may move the first pointer and the second pointer in opposite directions.

  According to this configuration, since the first pointer and the second pointer are moved in the opposite directions, the spurious suppression effect can be further enhanced even if there is a capacitance mismatch between the first and second capacitive elements.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same code | symbol may be attached | subjected to the same structure and the overlapping description may be abbreviate | omitted.

(Comparative example)
FIG. 1 is a diagram illustrating an example of a configuration of an AD converter 1000 according to a comparative example of the present disclosure. The AD converter 1000 is a noise shaping type successive approximation AD converter. The AD converter 1000 is based on a successive approximation type AD converter composed of a switch 1, a capacitor DAC 2, a comparator 3, a successive approximation controller 4, and a serial-parallel converter (SP) 5. The AD converter 1000 further includes a low-pass filter (LPF) 6, an integrator 7, and a control unit 900 in addition to this basic configuration.

  The switch 1 is a switch used when sampling the analog input voltage Vin. When the switch 1 becomes conductive, the analog input voltage Vin is input to the capacitor DAC2 through the common node N10.

  The capacitor DAC2 includes a plurality of capacitor elements 201 to 205 whose capacitance values are weighted by a binary ratio (ratio of powers of 2). Hereinafter, the capacitive elements 201 to 205 are represented as capacitive elements 200 unless otherwise distinguished. One end of the capacitive element 200 is connected to the common node N10, and the other end is connected to the reference voltage VH or the reference voltage VL. Here, it is assumed that the capacitance values of the capacitive elements 201 to 205 are, for example, 16C, 8C, 4C, 2C, and C, respectively. In FIG. 1, the number of capacitive elements 200 is five, but this is an example, and N (N is an integer of 2 or more) may be used.

  Further, the capacitor DAC2 includes switches 211 to 215 corresponding to the capacitor elements 201 to 205. Hereinafter, the switches 211 to 215 are represented as switches 210 unless otherwise distinguished. When the number of capacitive elements 200 is N, the number of switches 210 is N.

  The switch 210 applies a reference voltage VH (an example of a first voltage) or a reference voltage VL (an example of a second voltage) to the capacitive element 200 according to a digital input signal (an example of a successive approximation control signal) output from the successive approximation control unit 4. Connect one example). For example, when a digital input signal “1” is input, the switch 210 connects the reference voltage VH to the corresponding capacitive element 200, and when a digital input signal “0” is input, the switch 210 The reference voltage VL may be connected to the capacitor element 200 to be connected. Here, “connecting the reference voltage VH to the capacitor 200” means connecting the signal line to which the reference voltage VH is applied to the capacitor 200. Further, “connecting the reference voltage VL to the capacitor 200” means connecting a signal line to which the reference voltage VL is applied to the capacitor 200. It is assumed that the reference voltage VH is larger than the reference voltage VL.

  The comparator 3 compares the output voltage from the capacitor DAC2 with the comparison reference voltage Vfb output from the integrator 7.

  The successive approximation control unit 4 determines a digital input signal for causing the capacitor DAC2 to generate a comparison target voltage of the next bit of the target bit based on the comparison result of the target bit by the comparator 3.

  The serial-parallel converter 5 converts the comparison result from the comparator 3 into a multi-bit signal. The low-pass filter (LPF) 6 transmits the low-frequency component of the multi-bit signal output from the serial-parallel converter 5 and causes the AD converter 1000 to function as an oversampling AD converter.

  The integrator 7 receives the voltage output from the capacitor DAC 2, integrates the input voltage, and outputs an integrated value to the comparator 3.

  The control unit 900 causes the switches 1, 71, 72, and the like other than the switch 210 included in the capacitor DAC2 among the switches constituting the AD converter 1000 to be in a conductive state (ON) or an open state (OFF).

  Hereinafter, the operation of the AD converter 1000 will be described. First, the control unit 900 puts the switch 1 into a conductive state and opens the switch 1 after a predetermined time. As a result, the analog input voltage Vin is sampled by the capacitor DAC2. At this time, an intermediate value of the digital output code is given to the digital input signal of the capacitor DAC2 as an initial value.

  In the example of FIG. 1, since the capacitor DAC2 is a 5-bit capacitor DAC, the intermediate value of the digital output code is “1, 0, 0, 0, 0”. Thereby, the comparator 3 first compares the analog input voltage Vin with the comparison target voltage of (VH−VL) / 2, and determines the magnitude relationship between the two voltages. If Vin ≧ (VH−VL) / 2, the comparator 3 sets the MSB to “1”, and if Vin <(VH−VL) / 2, the comparator 3 sets the MSB to “0”. . Thereafter, based on the comparison result by the comparator 3, the successive approximation control unit 4 supplies the analog input voltage Vin and the comparison target voltage to the comparator 3 from MSB to LSB while operating the capacitor DAC2 by binary search. Let them compare.

  For example, if the MSB is “1”, the successive approximation control unit 4 maintains the digital input signal of the MSB at “1”, and converts the digital input signal of “1, 1, 0, 0, 0” to the capacitor DAC2. Output to. As a result, the analog input voltage Vin is compared with the comparison target voltage of 3 (VH−VL) / 4. If Vin ≧ 3 (VH−VL) / 4, the MSB-1 bit is set to “1”, and Vin If <3 (VH−VL) / 4, the MSB−1 bit is set to “0”.

  On the other hand, if the MSB is “0”, the successive approximation control unit 4 sets the MSB to “0” and outputs a digital input signal of “0, 1, 0, 0, 0” to the capacitor DAC2. Thereby, the analog input voltage Vin is compared with the comparison target voltage of (VH−VL) / 4, and if Vin ≧ (VH−VL) / 4, the next bit is set to “1”, and Vin <(VH− If (VL) / 4, the next bit is set to "0". Such an operation is repeated from the MSB to the LSB, and the value of each bit is determined. The comparison result of each bit is output as a multi-bit AD conversion value by the serial-parallel converter 5.

  FIG. 2 is a waveform diagram showing an example of a change in the output voltage of the capacitor DAC2 in the successive approximation operation. The successive approximation control unit 4 determines the comparison target voltage of the next bit by controlling the digital input signal of the capacitor DAC 2 based on the comparison result by the comparator 3. Since the binary search is performed by using the capacitor DAC2 weighted by the binary ratio, the difference between the output signal from the capacitor DAC2 and the comparison reference voltage Vfb becomes smaller toward the LSB from the MSB. Here, since the normal successive approximation AD converter does not compare the next bit after the LSB comparison process, it does not control the capacitor DAC2.

  However, after completing the LSB successive approximation, the AD converter 1000 performs the capacity control again based on the comparison result. The residual voltage Vres at this time corresponds to an error when quantized (that is, quantization noise). Further, the residual voltage Vres includes noise (that is, comparator noise) that is generated when the comparator 3 operates. These noise components are sampled and integrated by the integrator 7 and then input to the comparison reference voltage terminal of the comparator 3 as the comparison reference voltage Vfb. Thereby, the residual voltage Vres is added to the sampling value of the next analog input voltage Vin. Thus, by integrating the noise component generated at the time of quantization and feeding back to the next analog input voltage Vin, the AD converter 1000 can be given a noise shaping characteristic.

  FIG. 3 is a signal flow diagram showing the operation of the AD converter 1000 shown in FIG. Hereinafter, the principle of the AD converter 1000 will be described with reference to FIG. The residual voltage Vres is equal to the difference between the digital output Dout obtained by AD conversion and the analog input voltage Vin. This residual voltage Vres is sampled and integrated, and then fed back to the analog input voltage Vin of the next sample.

  Here, noise (that is, quantization noise and comparator noise) generated during the above-described quantization is defined as a noise component Q (z). At this time, the transfer function of the analog input voltage Vin (z) and the digital output Dout (z) is expressed as follows.

Dout (z) = Vin (z) + (1−Z ⁻¹ ) Q (z) Formula (1)
Here, the transfer function (noise transfer function: NTF) focusing on the noise component Q (z) is represented by (1-Z ⁻¹ ). This NTF has a high-pass filter characteristic that lowers the gain in the low frequency region. Therefore, the equation (1) shows the characteristic of moving the quantization noise and the comparator noise (that is, the noise component Q (z)) to the high frequency region side while maintaining the analog input voltage Vin (z) as it is. As a result, the AD converter 1000 realizes noise shaping characteristics. The noise component Q (z) moved to the high frequency region side is later removed by the low pass filter (LPF) 6. That is, the AD converter 1000 samples the analog input voltage Vin at a frequency sufficiently higher than the frequency of the analog input voltage Vin (that is, oversamples), thereby improving SNR (Signal to Noise ratio). And high resolution can be realized. Here, the frequency sufficiently higher than the analog input voltage Vin corresponds to a frequency larger than twice the maximum frequency included in the analog input voltage Vin. Therefore, oversampling is realized by the control unit 900 switching the switch 1 at a frequency sufficiently higher than the analog input voltage Vin. The oversampling frequency is not particularly limited as long as it is at least twice the maximum frequency of the analog input voltage Vin.

  However, the noise shaping characteristic in the AD converter 1000 shown in FIG. 1 is a first-order NTF, and a higher-order noise shaping characteristic is required in order to further increase the resolution. Moreover, since the operational amplifier used for the integrator 7 flows a steady current, an increase in power is inevitable. Therefore, the present inventors propose an AD converter according to the first embodiment.

(Embodiment 1)
FIG. 4 is a diagram illustrating an exemplary configuration of the AD converter 100 according to the first embodiment of the present disclosure. Similar to the AD converter 1000, the AD converter 100 is a noise shaping type successive approximation AD converter. Hereinafter, in the AD converter 100, the same components as those of the AD converter 1000 are denoted by the same reference numerals and description thereof is omitted.

  The AD converter 100 includes an integrator 8 instead of the integrator 7 in the AD converter 1000.

  The integrator 8 includes cascade-connected plural stages of integrating circuits 12, 14, and 16, two feedforward paths FF1 and FF2, and a feedback path FB1.

  The integrating circuit 12 is a first-stage integrating circuit, and includes an operational amplifier OP1 and a capacitive element C12. The integration circuit 14 is a second-stage integration circuit, and includes an operational amplifier OP2 and a capacitive element C14. The integration circuit 16 is a third-stage integration circuit, and includes an operational amplifier OP3 and a capacitive element C16.

  In the integrating circuit 12, the capacitive element C12 is connected between the input node N1 and the output node of the operational amplifier OP1. The other input node of the operational amplifier OP1 is grounded. Since the integrating circuits 14 and 16 have the same configuration as the integrating circuit 12, the description thereof is omitted.

  The input node N1 of the integrating circuit 12 is connected to the common node N10 via the switch φ1_1. Further, the integrating circuit 12 is connected to the integrating circuit 14 via the switch φ1_2 and the switch φ2_3. One end of the capacitive element 13 is connected to the connection point K1 of the switches φ1_2 and φ2_3, and the other end is grounded.

  The integration circuit 14 is connected to the integration circuit 16 via the switch φ2_4 and the switch φ3_3. One end of the capacitive element 15 is connected to the connection point K3 of the switches φ2_4 and φ3_3, and the other end is grounded.

  The feedforward path FF1 is provided between the common node N10 and the input node N2 of the second-stage integrating circuit 14, and samples the residual voltage Vres input from the common node N10 by the capacitive element 9, The difference voltage Vres is input to the second-stage integrating circuit 14.

  Specifically, the feedforward path FF1 includes a switch φs_2, a switch φ2_1, and a capacitive element 9. One end of the capacitive element 9 is connected to the common node N10 via the switch φs_2 and to the input node N2 via the switch φ2_1.

  The feedforward path FF2 is provided between the common node N10 and the input node N3 of the third-stage integrating circuit 16, and the residual voltage Vres input from the common node N10 is sampled by the capacitive element 10 and the sampled residual is obtained. The difference voltage Vres is input to the integration circuit 16 at the third stage.

  Specifically, the feedforward path FF2 includes a switch φs_1, a switch φ3_1, and a capacitive element 10. One end of the capacitive element 10 is connected to the common node N10 via the switch φs_1 and to the input node N3 via the switch φ3_1.

  The feedback path FB1 is provided between the output node N4 of the third-stage integrating circuit 16 and the input node N2 of the second-stage integrating circuit 14, and samples the output voltage from the integrating circuit 16 with the capacitive element 11, Feedback is provided to the integration circuit 14 at the second stage.

  Specifically, the feedback path FB1 includes a switch φ2_2, a switch φ3_2, and a capacitive element 11. One end of the capacitive element 11 is connected to the input node N2 through the switch φ2_2 and is connected to the output node N4 through the switch φ3_2. The other end of the capacitive element 11 is grounded.

  In the example of FIG. 4, the integrator 8 includes three integrator circuits 12, 14, and 16 connected in cascade, but this is only an example, and there are M (an integer of 2 or more) integrator circuits connected in cascade. It may be configured. In this case, a feed-forward path connected to the integration circuits from the second stage to the M stage may be provided.

  FIG. 5 is a diagram showing an example of a timing diagram of the integrator 8 shown in FIG. Hereinafter, the high-order noise shaping operation performed by the integrator 8 will be described with reference to FIGS. 4 and 5. Here, in the timing diagram, “ADC state” described in the first line indicates an operation state of the AD converter 100. In the “ADC state”, four operation states of a sampling state ST1, an AD conversion state ST2, an error feedback state ST3, and a reset state ST4 are cyclically repeated.

  The control signals Sφs, Sφ1, Sφ2, and Sφ3 are switch control signals, and when the switch is Hi, the switch is turned on (ON), and when the switch is Low, the switch is opened (OFF).

  The control signal Sφs is a control signal of switches φs_1 and φs_2 whose head is represented by a symbol “φs”, and the control signal Sφ1 is a control signal of switches φ1_1 and φ1_2 whose head is represented by a symbol “φ1”. The control signal Sφ2 is a control signal of the switches φ2_1 to φ2_4 whose head is represented by “φ2”, and the control signal Sφ3 is a control signal of the switches φ3_1 to φ3_4 whose head is represented by “φ3”. The control signals Sφs and Sφ1 to Sφ3 are output from the control unit 900.

  Hereinafter, a switch controlled by the control signal Sφs is represented as a switch φs unless otherwise distinguished, and a switch controlled by the control signal Sφ1 is represented as a switch φ1 unless otherwise distinguished, and is controlled by the control signal Sφ2. Unless otherwise distinguished, the switch controlled by the control signal Sφ3 is represented as switch φ3.

  First, in the sampling state ST1, the switch 1 is turned on and the analog input voltage Vin is charged in the capacitor DAC2. When the switch 1 is turned off, the AD conversion state ST2 is started. In the AD conversion state ST2, the value of each bit from the MSB to the LSB is determined by the successive approximation control unit 4, the capacitor DAC2, and the comparator 3, and the analog input voltage Vin is AD converted.

  When the value of LSB is determined, the error feedback state ST3 is started. The switch φs is in a conductive state until the error feedback state ST3 is started from the sampling state ST1. Therefore, at the start of the error feedback state ST3, the capacitive elements 9 and 10 are charged with the residual voltage Vres of the DAC 2 after completion of the successive comparison up to the LSB.

  In the error feedback state ST3, after the switch φs is turned off, the switch φ1 is turned on, and the residual voltage Vres stored in the capacitor DAC2 is integrated by the integration circuit 12 in the first stage, and the integrated value is the capacitance. Accumulated in the element 13. Next, the switch φ1 is turned off and the integrated value is sampled and held by the capacitive element 13, the switch φ2 is turned on, and the integrated value sampled and held by the capacitive element 13 is integrated by the second-stage integrating circuit. At this time, the residual voltage Vres sampled and held in the capacitive element 9 is also input to the second-stage integrating circuit 14 at the same time. Thereby, the feedforward path FF1 is realized.

  Similarly, after the switch φ2 is turned off, the switch φ3 is turned on, and the integrated value of the second-stage integrating circuit 14 sampled and held by the capacitor 15 and the residual voltage Vres sampled and held by the capacitor 10 are obtained. It is input to the integration circuit 16 at the third stage.

  Finally, the switch φ3 is turned OFF, and the integrated value of the third-stage integrating circuit 16 is sampled and held in the capacitive element 17. As described above, third-order integration is realized. The integration value of the third-order integration sampled by the capacitive element 17 is fed back to the comparator 3 as a comparison reference voltage Vfb when the analog input voltage Vin of the next sample is converted from MSB to LSB. In this way, a successive approximation AD converter having a third-order noise shaping characteristic is realized.

  Further, when the switch φ3 is ON, the feedback path FB1 causes the capacitive element 11 to sample the integration value of the integration circuit 16 at the third stage. Then, when the switch φ2 is turned on in the next sample, the feedback path FB1 feeds back the integrated value sampled by the capacitive element 11 to the input node N2 of the second-stage integrating circuit. Thereby, noise shaping in which noise in the low frequency region is further reduced can be realized.

  In the reset state ST4, for example, the capacitor elements 201 to 205 of the capacitor DAC2 are reset in preparation for AD conversion in the next sample.

  FIG. 6 is a signal flow diagram showing the operation of the AD converter 100 shown in FIG. In the AD converter 100, three integrating circuits 12, 14, and 16 are connected in cascade. In the AD converter 100, the input of the second-stage integrating circuit 14 is multiplied by the coefficient a1 by the feedforward path FF1, and the input of the third-stage integrating circuit 16 is multiplied by the coefficient a2 by the feedforward path FF2. It is done. In the present embodiment, the coefficients a1 and a2 are each 1. At this time, the transfer function of the AD converter 100 is expressed as follows.

Dout (z) = Vin (z) + (1-Z ⁻¹ ) ³ × Q (z) Formula (2)
As shown in Expression (2), the noise transfer function focused on the noise component Q (z) is represented by (1-Z ⁻¹ ) ³ , and a third-order noise shaping characteristic is realized.

  Further, in the AD converter 100, the feedback value FB1 multiplies the integral value output from the third stage integration circuit 16 by the coefficient g and inputs the result to the second stage integration circuit 14. Thereby, the NTF (noise transfer function) can have a zero point, and a notch can be made at a specific frequency position by the coefficient g. By creating the notch, the noise reduction region can be expanded to the high frequency side, so that the frequency band of the input analog input voltage Vin can be extended to the high frequency side.

  FIG. 7 is a signal flow diagram of the AD converter 100 when the integrator 8 is configured by an integrator 8 having a secondary noise shaping characteristic. When the secondary noise shaping characteristic is provided, the integrator 8 is composed of two integrating circuits 12 and 14 connected in cascade. Further, the input of the second-stage integrating circuit 14 is multiplied by a coefficient a1 by the feedforward path FF1. In addition, the feedback path FB1 multiplies the integral value of the second stage integration circuit 14 by the coefficient g, and returns the result to the first stage integration circuit 12.

  FIG. 8 is a graph showing an AD conversion output spectrum when noise shaping is not performed and when first-order, second-order, and third-order noise shaping is performed. In FIG. 8, the vertical axis represents power spectral density (PSD) in decibels, and the horizontal axis represents normalized frequency. Graphs 801, 802, 803, and 804 indicate AD conversion output spectra when noise shaping is not performed and when first-order, second-order, and third-order noise shaping are performed. A dotted line 805 parallel to the vertical axis indicates the upper limit of the signal band.

  As the noise shaping order increases to the first, second, and third orders, the PSD on the low frequency side decreases as a whole, and it can be seen that the noise suppression effect on the low frequency side is high. Therefore, it can be seen that the higher the order of noise shaping, the higher the SNR can be realized.

  FIG. 9 is a graph showing the frequency characteristics of NTF (noise transfer function) when first-order, second-order, and third-order noise shaping is performed. In FIG. 9, the vertical axis indicates the gain in dB, and the horizontal axis indicates the normalized frequency. The AD converter 100 can widen the low frequency side band with less noise by moving the zero point by the feedback path FB1.

  As described above, the AD converter 100 according to the first embodiment integrates the residual voltage Vres of the capacitor DAC2 after performing the successive approximation operation up to the LSB with the integrator 8, and feeds back as the comparison reference voltage Vfb of the next sampling. I am letting.

  Here, the integrator 8 first integrates the residual voltage Vres by the first-stage integrating circuit 12 and samples it by the feedforward paths FF1 and FF2. Next, the second-stage integration circuit 14 integrates the integration result of the first stage and the residual voltage Vres sampled by the feedforward path FF1. Next, the integration circuit 16 at the third stage integrates the integration result at the second stage and the residual voltage Vres sampled by the feedforward path FF2. As a result, the residual voltage Vres is given a high-order noise shaping characteristic and added to the next sampled analog input voltage Vin, and the analog input voltage Vin is given a high-order noise shaping characteristic. Therefore, a high-resolution successive approximation AD converter can be provided by oversampling the analog input voltage Vin.

  In the first embodiment, the operational amplifiers OP1, OP2, and OP3 constituting the integrating circuits 12, 14, and 16 do not need to be operated at all times. The operational amplifiers OP1, OP2, and OP3 need only operate during the integration operation. Accordingly, the operational amplifiers OP1, OP2, and OP3 used in the first-stage, second-stage, and third-stage integration circuits 12, 14, and 15 are periods in which the control signals Sφ1, Sφ2, and Sφ3 are ON, respectively. Need only work. In the case of a 10-bit successive approximation operation, the integration period is about 1/20 of the entire AD conversion period, so that significant power reduction can be achieved.

  Specifically, the control signal Sφ1 is input to the operational amplifier OP1 of the integration circuit 12, the control signal Sφ2 is input to the operational amplifier OP2 of the integration circuit 14, and the control signal Sφ3 is input to the operational amplifier OP3 of the integration circuit 16. Then, the operational amplifier OP1 is operated when the control signal Sφ1 is Hi, the operational amplifier OP2 is operated when the control signal Sφ2 is Hi, and the operational amplifier OP3 is operated when the control signal Sφ3 is Hi.

  Further, it is possible to realize the third-order integrator 8 with only one operational amplifier. As described above, since the operational amplifiers only need to be operated during each integration period, the first stage, the second stage, and the third stage integration can be realized by using one operational amplifier. By applying such an operational amplifier sharing technique, the AD converter 100 can be further reduced in size.

  FIG. 10 is a diagram illustrating an example of the configuration of an integrator 8A that performs third-order integration with one operational amplifier. In the integrator 8A shown in FIG. 10, the same components as those of the integrator 8 shown in FIG. The integrator 8A includes an operational amplifier OP1, and includes an integration circuit that sequentially performs a plurality of stages (three stages in the example of FIG. 10) of integration by using the operational amplifier OP1.

  In the example of FIG. 10, the integration circuit includes capacitive elements C12 and 13 and switches φ1_1, φ1_2 and φ1_3 corresponding to the first stage integration operation, and capacitive elements C14 and 15 and switch φ2_2 corresponding to the second stage integration operation. , Φ2_3, φ2_4, and capacitive elements C16, 17 and switches φ3_2, φ3_3, φ3_4 corresponding to the integration operation of the third stage.

  The integrator 8A includes a feed forward path FF1 corresponding to the second stage integration operation and a feed forward path FF2 corresponding to the third stage integration operation. The feedforward paths FF1 and FF2 respectively sample the residual voltage Vres, and input the residual voltage Vres sampled when the integration circuit performs the second-stage and third-stage integration operations to the operational amplifier OP1 of the integration circuit. .

  Between the input node N20 and the output node N30 of the operational amplifier OP1, there are a capacitive element C12 and a switch φ1_2 connected in series, a capacitive element C14 and a switch φ2_4 connected in series, and a capacitive element C16 and a switch φ3_4 connected in series. Connected in parallel.

  The input node N20 is connected to the common node N10 via the feedforward path FF1, and is connected to the common node N10 via the feedforward path FF2. Further, the input node N20 is connected to the common node N10 via the switch φ1_1.

  Output node N30 is connected to capacitive element 13 via switch φ1_3, connected to capacitive element 15 via switch φ2_3, and connected to capacitive element 17 via switch φ3_3.

  Capacitance element 13 is connected to input node N20 via switch φ2_2, and capacitance element 15 is connected to input node N20 via switch φ3_2.

  Next, the operation of the integrator 8A will be described with reference to the timing diagram of FIG. In the sampling state ST1 and the AD conversion state ST2, the switch φs is turned on. Therefore, when the switch φs is turned off and the error feedback state ST3 is started, the residual voltage Vres is sampled by the capacitive elements 9 and 10.

  When the switch φ1 is turned on in the error feedback state ST3, the capacitive element C12 is connected between the input node N20 and the output node N30 of the operational amplifier OP1. As a result, the operational amplifier OP1 forms a first-stage integration circuit and executes the first-stage integration operation. When the switch φ1 is turned on, the input node N20 of the operational amplifier OP1 is connected to the common node N10 via the switch φ1_1, and the output node N30 is connected to the capacitive element 13 via the switch φ1_3. As a result, the residual voltage Vres is integrated by the first-stage integration circuit, and the integrated value of the first-stage integration operation is stored in the capacitive element 13.

  Next, when the switch φ1 is turned off and the switch φ2 is turned on, the capacitive element C14 is connected between the input node N20 and the output node N30 of the operational amplifier OP1. As a result, the operational amplifier OP1 forms a second-stage integration circuit and executes the second-stage integration operation. At this time, input node N20 is connected to capacitive element 9 via feedforward path FF1, input node N20 is connected to capacitive element 13 via switch φ2_2, and output node N30 is connected to capacitive element 15 via switch φ2_3. Connected. Therefore, the integrated value of the first stage integration operation sampled by the capacitive element 13 and the residual voltage Vres sampled by the capacitive element 9 are integrated by the second stage integration operation, and the integrated value is supplied to the capacitive element 15. Stored.

  Next, when the switch φ2 is turned off and the switch φ3 is turned on, the capacitive element C16 is connected between the input node N20 and the output node N30 of the operational amplifier OP1. As a result, the operational amplifier OP1 forms a third-stage integration circuit and executes the third-stage integration operation. At this time, input node N20 is connected to capacitive element 10 via feedforward path FF2, input node N20 is connected to capacitive element 15 via switch φ3_2, and output node N30 is connected to capacitive element 17 via switch φ3_3. Connected. Therefore, the integrated value of the second stage integration operation sampled by the capacitive element 15 and the residual voltage Vres sampled by the capacitive element 10 are integrated by the third stage integration operation, and the integrated value is supplied to the capacitive element 17. Stored.

  The integrated value stored in the capacitive element 17 is input to the comparator 3 as the comparison reference voltage Vfb in the next sampling.

  As described above, when the integrator 8A is employed, the number of operational amplifiers OP1 is only one, so that the circuit scale can be reduced.

(Embodiment 2)
FIG. 11 is a diagram illustrating an example of a configuration of the AD converter 100A according to the second embodiment of the present disclosure. Similar to the AD converter 100, the AD converter 100 </ b> A is a noise shaping type successive approximation AD converter. Hereinafter, in the AD converter 100A, the same components as those of the AD converter 100 are denoted by the same reference numerals and description thereof is omitted.

  The AD converter 100A employs a split capacitor DAC 18 as the capacitor DAC2 in the AD converter 1000 shown in FIG. The integrator 7 is shown on the right side of the split capacitor DAC 18, but is electrically the same as the integrator 7 of the AD converter 1000 because the input terminal is connected to the common node N 10.

  The split capacitor DAC 18 includes capacitor elements 301 to 305 for increasing the output voltage of the split capacitor DAC 18 and capacitor elements 401 to 405 for decreasing the output voltage.

  One end of the capacitive elements 301 to 305 and one end of the capacitive elements 401 to 405 are connected to each other via a common node N10. The other ends of the capacitive elements 301 to 305 are connected to the reference voltage VH or the reference voltage VL, and the other ends of the capacitive elements 401 to 405 are connected to the reference voltage VH or the reference voltage VL.

  Further, a DEM (Dynamic Element Matching) unit 19 is used to control the split capacitor DAC 18. The DEM unit 19 suppresses the spurious of the output signal by randomly using the capacitive element according to the analog input voltage Vin when the capacitive element constituting the split-type capacitive DAC 18 varies. It is. The DEM unit 19 is an example of a successive approximation control unit.

  Hereinafter, the capacitive elements 301 to 305 are represented as a capacitive element 300 unless particularly distinguished. Further, the capacitor elements 401 to 405 are represented as a capacitor element 400 unless particularly distinguished. Here, it is assumed that the capacitive elements 301 to 305 and 401 to 405 have the same capacitance value. Here, five capacitive elements 300 and five capacitive elements 400 are provided, but this is an example. N (an integer greater than or equal to 2) capacitor elements 300 may be provided, and N capacitor elements 400 may be provided. The capacitive element 300 is an example of a second capacitive element, and the capacitive element 400 is an example of a first capacitive element.

  The switches 501 to 505 correspond to the capacitive elements 301 to 305, and the switches 601 to 605 correspond to the capacitive elements 401 to 405. Hereinafter, the switches 501 to 505 are represented as a switch 500 unless otherwise distinguished, and the switches 601 to 605 are represented as a switch 600 unless otherwise distinguished.

  FIG. 12 is an explanatory diagram of the operation of the split capacitor DAC 18. FIG. 13 is a waveform diagram showing the transition of the output voltage (that is, the analog input voltage Vin) from the split capacitor DAC 18. Hereinafter, the operation of the split capacitor DAC 18 will be described with reference to FIGS. 12 and 13. Here, in the example of FIG. 12, the operation of the split capacitor DAC 18 in the case where there are 32 capacitors is shown.

  The capacitance map 1200 conceptually shows the arrangement of the capacitive elements 300 and 400. Sixteen capacitive elements 300 are mapped in the first row, and sixteen capacitive elements 400 are mapped in the second row. In the capacitance map 1200, for example, the cell in the first row and the first column indicates the capacitive element 300 arranged first from the left, and the cell in the first row and the second column shows the capacitive element 300 arranged second from the left. Thus, the capacitive element 300 is mapped.

  In the capacitance map 1200, for example, the square in the second row and the first column indicates the capacitive element 400 arranged first from the left, and the square in the second row and the second column shows the capacitive element 400 arranged second from the left. As shown, the capacitive element 400 is mapped.

  A pointer P1 (an example of a first pointer) designates a position in the capacitive element 400, and a pointer P2 (an example of a second pointer) designates a position in the capacitive element 300. In the initial state of the successive approximation, the pointer P1 is located at the left end, and the pointer P2 is located at the right end.

  In the capacitance map 1200, the reference voltage VH is connected to the capacitance element corresponding to the gray cell among the capacitance elements 300 and 400. The reference voltage VL is connected to the capacitive element corresponding to the white cell among the capacitive elements 300 and 400.

  As described above, the initial value of the capacitor DAC2 when sampling the analog input voltage Vin is an intermediate value of the digital output code.

  Accordingly, in step S1, which is an initial state of successive approximation, the DEM unit 19 connects the reference voltage VH to one end (terminal opposite to the common node N10) of the upper half 16 capacitive elements 300, and the lower half 16 A reference voltage VL is connected to one end of each capacitor element 400 (a terminal opposite to the common node N10).

  After opening the switch 1, the DEM unit 19 transitions the output voltage of the split capacitor DAC 18 according to the comparison result of the comparator 3. In this case, when changing the output voltage (Vin) in the plus direction, the DEM unit 19 moves the pointer P1 in the right direction to switch the connection of the capacitive element 400 from the reference voltage VL to the reference voltage VH. On the other hand, when changing the output voltage (Vin) in the minus direction, the DEM unit 19 moves the pointer P2 to the left and switches the connection of the capacitive element 300 from the reference voltage VH to the reference voltage VL.

  In the example of FIG. 13, since the output voltage (Vin) is equal to or higher than the comparison reference voltage Vfb in step S1, the DEM unit 19 sets “1” to the MSB, and the output voltage (Vin) is set in the MSB-1 bit successive comparison. Judge to lower. Therefore, as shown in step S2 of FIG. 12, the DEM unit 19 moves the pointer P2 by eight squares in the left direction and positions the ninth capacitive element 300 from the right. Then, the DEM unit 19 switches the connection of the eight capacitive elements 300 through which the pointer P2 has passed from the reference voltage VH to the reference voltage VL.

  As a result, the output voltage (Vin) transitions by − (VH−VL) / 4. In step S2, as shown in FIG. 13, since the output voltage (Vin) is smaller than the comparison reference voltage Vfb, the DEM unit 19 sets the MSB-1 bit to “0”, and in the MSB-2 bit sequential comparison, It is determined that the output voltage (Vin) is increased. Therefore, as shown in step S3 of FIG. 12, the DEM unit 19 moves the pointer P1 to the right by 4 squares and positions the fifth capacitive element 400 from the left. Then, the DEM unit 19 switches the connection of the four capacitive elements 400 through which the pointer P1 has passed from the reference voltage VL to the reference voltage VH. As a result, the output voltage (Vin) transitions by + (VH−VL) / 8.

  In subsequent S4 and S5, the DEM unit 19 repeats the transition of the output voltage (Vin) until the LSB sequential comparison is completed while moving the pointers P1 and P2 by the same operation. When the LSB successive approximation is completed, the DEM unit 19 resets the initial value of the split capacitor DAC 18 in preparation for the next sampling of the analog input voltage Vin. At this time, the DEM unit 19 connects all the capacitor elements 300 in the upper half to the reference voltage VH, connects all the capacitor elements 400 in the lower half to the reference voltage VL, and resets the split capacitor DAC 18. The positions of P1 and P2 are not reset.

  If step S5 in FIG. 12 indicates the end of the LSB successive approximation, the movement of the pointers P1 and P2 starts from this position at the next sampling.

  Therefore, after the switch 1 is opened, the operations of the pointers P1 and P2 with respect to the capacitive elements 300 and 400 are started from the final positions of the previous sampling pointers P1 and P2. Thereby, even if a capacitance mismatch occurs in the capacitive elements 300 and 400 of the split capacitive DAC 18, it is possible to suppress spuriousness without generating fixed pattern noise. Furthermore, the first order noise shaping characteristic can be given to the noise due to the capacitance mismatch by the pointer operation depending on the analog input voltage Vin.

  In the capacitance map 1200, the leftmost capacitive element 300 and the rightmost capacitive element 300 are continuous, and the leftmost capacitive element 400 and the rightmost capacitive element 400 are continuous. Therefore, when the pointer P1 reaches the rightmost capacitive element 400, the pointer P1 is continuously moved rightward from the leftmost capacitive element 400. When the pointer P2 reaches the leftmost capacitive element 300, the pointer P2 continues to move leftward from the rightmost capacitive element 300.

  FIG. 14 is a graph 1401 showing an example of a power spectrum when the DEM is not employed. FIG. 15 is a graph 1501 illustrating an example of a power spectrum of the AD converter 100A according to the second embodiment of the present disclosure, and is a graph 1501 when a DEM is employed. In FIGS. 14 and 15, the vertical axis indicates power spectral density (PSD) in decibels, and the horizontal axis indicates frequency.

  In this simulation, the capacity mismatch is given by 1σ = 1%, and the spectrum of the output signal of the capacity DAC is obtained. From a comparison between the graph 1401 and the graph 1501, it can be seen that a plurality of spurious generated due to the capacity mismatch is suppressed by using the DEM.

(Modification)
(1) Although two feedforward paths FF1 and FF2 are provided in FIG. 4, if there is at least one feedforward path, higher-order noise shaping characteristics can be obtained, so one feedforward path is omitted. You may be. When the integrator 8 is composed of N (integers greater than or equal to 2) integrator circuits, the feedforward path is connected to at least one of the N-1 integrator circuits in the second and subsequent stages. The

  (2) Although the feedback path FB1 is provided in FIG. 4, the feedback path FB1 may be omitted. In FIG. 10, the feedback path FB1 is not provided, but the feedback path FB1 may be provided. In this case, the feedback path FB1 only needs to have one end connected to the output node N30 and the other end connected to the input node N20.

  (3) Although the primary integrator 7 is used in FIG. 11, the integrators 8 and 8A may be employed.

  (4) In FIG. 10, the integrator 8A is configured using one operational amplifier OP1, but the integrator may be configured using a plurality of operational amplifiers.

  In the present disclosure, all or part of the functional blocks in the block diagrams shown in FIGS. 4 and 11 are one or more electronic circuits including a semiconductor device, a semiconductor integrated circuit (IC), or an LSI (large scale integration). May be executed by The LSI or IC may be integrated on a single chip, or may be configured by combining a plurality of chips. For example, the functional blocks other than the memory element may be integrated on one chip. Here, it is called LSI or IC, but the name changes depending on the degree of integration, and may be called system LSI, VLSI (very large scale integration), or ULSI (ultra large scale integration). A Field Programmable Gate Array (FPGA) programmed after manufacturing the LSI, or a reconfigurable logic device capable of reconfiguring the junction relationship inside the LSI or setting up a circuit partition inside the LSI can be used for the same purpose.

  Furthermore, all or some of the functions or operations of the functional blocks in the block diagrams shown in FIGS. 4 and 11 can be executed by software processing. In this case, the software is recorded on a non-transitory recording medium such as one or more ROMs, optical disks, hard disk drives, etc., and when the software is executed by a processor, A specific function in the software is executed by a processor and peripheral devices. The system or apparatus may comprise one or more non-transitory recording media in which software is recorded, a processor, and required hardware devices such as interfaces.

  Since the AD converter according to the present disclosure can perform high-resolution AD conversion while maintaining low power consumption, it is useful as an AD converter used for an analog front end of a sensor for mobile use.

1 Switch 2 Capacitance DAC
3 Comparator 4 Successive Comparison Control Unit 5 Serial-Parallel Conversion Circuit 6 Digital Filter 7, 8 Integrator 9, 10, 11, 13, 15, 17 Capacitance Element 12, 14, 16 Integration Circuit 18 Split Type Capacitance DAC
19 DEM part FF1, FF2 Feed forward path FB Feedback path Sφs, Sφ1, Sφ2, Sφ3 Control signal

Claims (9)

A common node to which an analog input voltage is input;
A capacitive DAC including a plurality of capacitive elements, one end of each capacitive element being connected to the common node, and the other end being selectively connected to one of the first and second voltages according to a successive approximation control signal; ,
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The integrator is
A plurality of cascaded integrator circuits;
An AD converter including at least one feedforward path that samples the residual voltage and inputs the residual voltage to any one of the second and subsequent integration circuits.   2. The AD converter according to claim 1, wherein the integrator includes at least one feedback path that feeds back an integrated value of an integrating circuit in a subsequent stage to an integrating circuit in the preceding stage.   3. The AD converter according to claim 1, wherein each integrating circuit includes an operational amplifier that is activated only when the integrating operation is performed. A common node to which an analog input voltage is input;
A capacitive DAC including a plurality of capacitive elements, one end of each capacitive element being connected to the common node, and the other end being selectively connected to one of the first and second voltages according to a successive approximation control signal; ,
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The integrator is
An integration circuit that includes an operational amplifier, and that sequentially performs a plurality of stages of integration operation by sharing the operational amplifier;
At least one feedforward path that samples the residual voltage and inputs the sampled residual voltage to the integrating circuit when the integrating circuit performs at least one of the integrating operations in the second and subsequent stages. An AD converter comprising:   5. The AD conversion according to claim 4, wherein the integrator includes a feedback path that feeds back an integration value of the first integration operation to the integration circuit when the integration circuit performs an integration operation next to the integration operation of the first integration operation. vessel.   The AD converter according to claim 4, wherein the operational amplifier is activated only when performing an integration operation. A common node to which an analog input voltage is input;
A plurality of capacitive elements are provided, one end of each capacitive element is connected to the common node, and the other end is selected from the first voltage and the second voltage lower than the first voltage according to the successive approximation control signal Capacitively connected capacitor DAC;
A comparator for comparing the voltage of the common node with a comparison reference voltage;
A successive approximation control circuit for determining a successive approximation control signal of the next bit from the comparison result of the comparator;
The residual voltage of the capacitor DAC after the successive approximation operation is performed up to the least significant bit is input via the common node, the input residual voltage is integrated, and the integrated value is used as a comparison reference voltage for the next sampling. And an integrator
The capacitor DAC is composed of a split capacitor DAC including a plurality of first capacitor elements for increasing the output voltage of the capacitor DAC and a plurality of second capacitor elements for decreasing the output voltage,
The successive approximation control circuit includes:
In the initial state of successive approximation, all the first capacitive elements are connected to the second voltage, and all the second capacitive elements are connected to the first voltage,
When increasing the output voltage of the capacitor DAC in the successive comparison of the next bit, the first pointer is virtually moved along the arrangement direction of the plurality of first capacitor elements, and the second voltage is changed to the first voltage. Determining the first capacitive element to switch connection;
When lowering the output voltage of the capacitor DAC in the successive approximation of the next bit, the second pointer is virtually moved along the arrangement direction of the plurality of second capacitor elements, and the first voltage is changed to the second voltage. Determine the second capacitive element to be switched,
When the sequential comparison of the least significant bit is completed, all the first capacitive elements are connected to the second voltage while maintaining the positions of the first and second pointers, and all the second capacitive elements are AD converter connected to the first voltage.   The AD converter according to claim 7, wherein the successive approximation control circuit determines whether or not it is necessary to increase an output voltage of the capacitor DAC from a comparison result of the comparator.   The AD converter according to claim 8, wherein the successive approximation control circuit moves the first pointer and the second pointer in opposite directions.

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