JP2000338148A - Electronic watthour meter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a watthour meter of high accuracy and simple circuit structure by low-pass filtering ab AC current and AC voltage quantized by a sigma delta modulating circuit, thinning them with a predetermined ratio by a thinning means, and then determining an electric power value by multiplying the same. SOLUTION: An AC current (i) and an AC voltage (v) are respectively integrated by an integrator, and the digital values are output through a comparator. Sigma delta modulating circuits 10, 11 delay the outputs, convert digital values into analogue values, and feedback the same to an input side of the integrator to quantize the AC current and the AC voltage. Then the AC current and the AC voltage as input signals are low-pass filtered by digitals LPF 12, 13, and a quantized sampling value array of the AC current and the AC voltage is thinned by a ratio of 1/m (m: arbitrary positive :integer) by thinning means 141, 151, 161, 171. The thinned AC current I and AC voltage V are multiplied by a multiplier 20 to determine an electric power value, and the power source value determined by a counter is integrated. Whereby a circuit can be simplified and a monolithic circuit can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic watt-hour meter for converting a voltage and a current of an analog input signal into a digital value for processing.

[0002]

2. Description of the Related Art FIG. 34 is a block diagram of a circuit for calculating the power of a conventional electronic watt-hour meter. In FIG. 34,
Reference numeral 71 denotes a first successive approximation type A / D converter which receives an analog current signal, 72 denotes a second successive approximation type A / D converter which receives an analog voltage signal, and 73 denotes each successive approximation type. This is a multiplier that receives digital data corresponding to the voltage value and the current value from the A / D converters 71 and 72 as inputs.

A conventional electronic watt-hour meter employs a first and second successive approximation type A / D as shown in FIG. 34 as means for converting analog amounts of voltage and current into digital values.
It has converters 71 and 72, and a digital output is calculated by a multiplier 73 to obtain power W. Generally, the successive approximation type A / D converters 71 and 72 quantize the output of an analog input signal to a digital value that discretely increases with the same resolution. A high-resolution successive approximation A / D converter is required to obtain high accuracy.

For example, the current signal is 1/12 of the maximum input.
Assuming that the precision of the quantized current value at this time is 0.
To keep it below 5% Need to be The S / N of the successive approximation type A / D converter is S / N = 6m + 1.8 (dB) (2) (m is the successive approximation type A when the sampling frequency fs = 2 × signal frequency) / Number of output bits of the D / D converter), and in order to maintain the above accuracy of 0.5% or less, a successive approximation A / D converter having a resolution of m = 15 bits is required.

On the other hand, as a method of increasing the accuracy, there is a method of increasing the sampling frequency (fs) of the successive approximation A / D converter, a method called oversampling. For example, if the sampling frequency (fs) is increased to 128 times the sampling frequency (fs = twice the signal frequency) determined by the Nyquist theorem, the quantization noise is dispersed over a wide band, and the level of each frequency component spectrum decreases. I do. If the signal frequency is 60 Hz and the sampling frequency (fs) is 15.36 kHz, oversampling is performed 128 times, the noise level of the signal frequency component is improved by about 21 dB, and the resolution of the successive approximation A / D converter is 3 to This is equivalent to increasing by 4 bits. In order to maintain the accuracy of the quantized current value at 0.5% or less, a successive approximation A / D converter having a resolution of 11 to 12 bits is required in this case.

[0006]

Therefore, conventionally, to obtain a high-precision electronic ammeter, a high-resolution successive approximation type A / A
A D converter and a multiplier having multiple bits as inputs are required, which complicates the circuit configuration and increases the cost.
This is extremely disadvantageous especially when mass production is to be performed by making a monolithic IC.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to obtain a highly accurate electronic watt-hour meter with a simple circuit configuration. It is an object of the present invention to obtain an electronic watt-hour meter that can be easily converted to a monolithic IC by using a particularly simple circuit configuration.

[0008]

(1) In the invention according to claim 1 of the present application, an AC current and an AC voltage are respectively integrated by an integrator, a digital value is output through a comparator, and the output is delayed. First and second sigma-delta modulation circuits for D / A converting and feeding back to the input side of the integrator to quantize the AC current and the AC voltage, respectively; and the quantized AC current and the AC voltage. And a second digital low-pass filter that respectively passes low-pass signals as input signals, and 1 / m (m is an arbitrary positive integer) from a sampled value sequence of the quantized AC current and AC voltage after low-pass. ), First multiplying means for multiplying the AC current and AC voltage from the thinning means to obtain a power value, and integrating means for multiplying the obtained power value. Those were.

(2) The invention according to claim 2 of the present application is:
The first and second digital low-pass filters connect a predetermined number of delay means to the input signal in a cascade, multiply the input signal and the output of each delay means by predetermined coefficients, and multiply these multiplication results. And a filter for low-passing each of the quantized AC current and AC voltage as an input signal, and the thinning-out means reduces the quantized AC current and AC voltage after the low-pass. A means for thinning out the sampling value sequence at a rate of 1 / m (m is an arbitrary positive integer equal to or greater than the number of the delay means of the first and second digital low-pass filters).

(3) The invention according to claim 3 of the present application:
First and second integrating means for integrating each of the quantized AC current and AC voltage for one cycle, second multiplying means for multiplying the output from each of the integrating means, output of the first multiplying means And a subtraction means for subtracting the output of the second multiplication means from the output signal, and the output from the subtraction means is input to the accumulation means.

(4) The invention according to claim 4 of the present application is:
Zero-crossing detection means for detecting one cycle of the quantized AC current and AC voltage by zero-crossing of the AC voltage, and each of the quantized AC current and AC voltage for one cycle based on the output of the zero-crossing detection means. First and second integration means for integrating, second multiplication means for multiplying the output from each of the integration means, and subtraction means for subtracting the output of the second multiplication means from the output of the first multiplication means It is provided.

(5) The invention according to claim 5 of the present application:
Switching means for sequentially taking out the alternating current and the alternating voltage of the input multi-element at a predetermined cycle, integrating the alternating current and the alternating voltage of each element from the switching means with an integrator and outputting a digital value through a comparator, A first sigma-delta modulation circuit converting means for delaying the output, performing D / A conversion and feeding it back to the input side of the integrator, and sequentially quantizing the AC current and AC voltage of each element from the switching means; And second sigma-delta modulation circuit, first and second digital low-pass filters for sequentially passing low-pass AC current and AC voltage of each of the quantized elements as input signals, quantization after low-pass Thinning-out means for thinning out the sampled sequence of AC current and AC voltage of each element at a rate of 1 / m (m is an arbitrary positive integer). First multiplying means for multiplying the alternating current and the alternating voltage, respectively, adding means for obtaining the sum of the multiplication results as the power value is obtained with an integration means for integrating the power values obtained.

(6) The invention according to claim 6 of the present application is:
The first and second digital low-pass filters connect a predetermined number of delay means to the input signal in a cascade, multiply the input signal and the output of each delay means by predetermined coefficients, and multiply these multiplication results. And a filter for low-passing each of the quantized AC current and AC voltage as an input signal, and the thinning-out means reduces the quantized AC current and AC voltage after the low-pass. A means for thinning out the sampling value sequence at a rate of 1 / m (m is an arbitrary positive integer equal to or greater than the number of the delay means of the first and second digital low-pass filters).

(7) The invention according to claim 7 of this application is as follows:
Offset adjusting means for subtracting the offset power value from the quantized power value is provided, and the offset power is calculated from the quantized offset current and offset voltage obtained by inputting the reference current and the reference voltage. This is set as the offset power value.

(8) The invention according to claim 8 of this application is as follows:
Providing offset adjustment means for subtracting the offset power value from the quantized power value, calculating the offset power from the quantized offset current and offset voltage obtained by inputting the reference current and the reference voltage at a predetermined cycle, This calculation result is set as the offset power value for each of the predetermined cycles.

(9) According to claim 9 of the present application,
A delay means for obtaining a desired delay time is provided between at least one of the second sigma-delta modulation circuit and the second digital filter, and at least one between the first sigma-delta modulation circuit and the first digital filter, This delay operation adjusts the current phase angle or the voltage phase angle.

(10) In the invention according to claim 10 of the present application, the delay means is a shift register capable of shifting a desired number of shifts, and the phase angle is adjusted by this shift operation.

(11) The invention according to claim 11 of the present application relates to a multi-element input in which an AC current and an AC voltage of an n element are inputted, and the second, third,. .., And Bn are respectively provided with balance adjustment means for multiplying the quantized power values by B2, B3,.
, N, and a reference current and a reference voltage are respectively applied to the inputs of the elements, and the quantized power value is measured by w
1, w2, w3,... Wn, and B2 = w1 / w2,
The balance adjustment values of B3 = w1 / w3,... Bn = w1 / wn are set as the balance adjustment values.

(12) The invention according to claim 12 of the present application is to reset and repeat integration each time the integrated value of the quantized power value exceeds a preset rated reference value.
It measures the time until the integrated value of the power value exceeds the rated reference value. If the time is equal to or longer than a predetermined time, a dive prevention means for preventing the power amount within the measured time from being measured is provided. It is provided.

(13) The invention according to claim 13 of the present application is to provide a third digital low-pass filter for passing the quantized power value in a low-pass range, and to lay out the output passed through the third digital low-pass filter. This is input to the motion prevention means.

(14) The invention according to claim 14 of this application is provided with a light load adjusting means for adding a predetermined light load adjustment value to the quantized power value at least when the load is light.

(15) The invention according to claim 15 of the present application is a third digital low-pass filter which operates at a predetermined operation clock frequency f and passes a quantized power value in a low-pass range. A first register that stores the output value that has passed through the low-pass filter, a second register that operates at an operating clock frequency of n times the frequency f and adds and stores the value of the first register n times, A comparison means for comparing the value of the second register with a preset rated reference value at an operating clock frequency of n times the frequency f, and sending out an output for measuring the amount of electric power every time the rated reference value is exceeded. Things.

(16) The invention according to claim 16 of the present application is provided with rating adjusting means for outputting the input electric energy as the electric energy corrected based on the rated reference value, and inputting the reference current and the reference voltage. Correct the rated reference value previously set according to the ratio of the actually measured reference power value obtained by multiplying the reference current and the reference voltage by the calculated reference power value. The rated reference value thus set is set as the above-mentioned rated reference value.

(17) The invention according to claim 17 of this application is a switching means for sequentially switching and outputting each of the first phase, second phase, and third phase input currents and input voltages at a predetermined cycle, and this switching means. First and second analog-to-digital conversion means for quantizing the AC current and AC voltage of each phase from the first and second, respectively, for passing the quantized AC current and AC voltage of each phase in low-pass, respectively. Two digital low-pass filters, one of which is obtained from a sequence of sampling values of AC current and AC voltage of each phase quantized after low-pass.
/ M, a multiplying means for multiplying the AC current and the AC voltage of each phase from the thinning means, an adding means for obtaining the sum of outputs from the multiplying means, and A third digital low-pass filter for passing the signal, an integrating means for integrating the output from the third digital low-pass filter, and a second phase and a third phase obtained from an ordinary AC current and AC voltage of the object to be measured. And first and second balance adjustment registers for multiplying the quantized power values by the balance adjustment values B1 and B2, respectively, and input a predetermined analog value in the same phase as the first phase current / voltage input. The output of the third digital low-pass filter at the time is
The analog value is input as the current / voltage input of the phase, the output of the third digital low-pass filter at this time is w02, and the analog value is input as the current / voltage input of the first phase. Balance adjustment means for setting the output of the third digital low-pass filter to w03, setting the value of B2 = w01 / w02 in the first balance adjustment register, and setting the value of B3 = w01 / w03 in the second balance adjustment register . A register for integrating the output of the third digital low-pass filter and an F value setting register for setting a value of F = (w01 / reference power) × rated reference value are provided, where reference power = reference voltage. The product calculated by multiplying the reference current, the rated reference value = the calculated value (constant) that determines the number of pulses per power amount) The quantized power amount is integrated by the register, and the integrated value is calculated by the F value. Rating adjusting means for sending an output for measuring the amount of electric power each time the power exceeds the limit and resetting the register. A light load adjustment register for adding the set light load adjustment value to the output value of the third digital low-pass filter is provided, and 1 / n (n ≧ n) of the current analog value input above.
The value of 1) is input as a current input of the first phase, and 1 / m (m ≧ 1) of the voltage analog value input as described above is input as a current input of the second phase. The output of the low-pass filter is defined as w0n, and L = (w01
(/ Nm) -Light load adjustment means for setting the value of -w0n as the light load adjustment value in the light load adjustment register. A shift register capable of shifting a desired number of shifts between the second analog / digital conversion means and the second digital low-pass filter and P1, P2, and P3 registers for designating the number of shifts of the shift register are provided. As an input of the first phase, an analog value having the same effective value as the above-mentioned input analog value and a power factor = 0.5 is input, and the output of the third digital low-pass filter at that time is W0P1, and P1 = K ( w01 × 0.5) −w0P1 (where K is a constant) is set in the P1 shift register, and the second
As the phase input, an analog value having the same effective value as the above input analog value and a power factor = 0.5 is input, and the output of the third digital low-pass filter at that time is w0P2,
The value of P2 = K (w01 × 0.5) -W0P2 is set in the shift register of P1, and the analog value of power factor = 0.5 having the same effective value as the input analog value as the input of the third phase as the input analog value is input. , And the output of the third digital low-pass filter at that time is defined as w0P3, and P1 = K (w01 × 0.
5) Phase adjusting means for setting the value of -w0P3 in the shift register of P1 and sequentially shifting the phase of each phase to the values of P1, P2 and P3 in the shift register in synchronization with the switching means to adjust the phase. It has at least one adjusting means among the above adjusting means.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In FIG. 1, 1
Reference numeral 0 denotes a first sigma-delta modulation circuit that receives an analog current signal i, and reference numeral 11 denotes a second sigma-delta modulation circuit that receives an analog voltage signal v. 12 is the first one
The output of the first sigma-delta modulation circuit 10 is converted to 16 points (hereinafter, 16 points) by a 6-tap moving average digital filter.
Called tap. ) To perform a moving average. Reference numeral 14 denotes a second 16-tap moving average digital filter connected to the first moving average digital filter 12, and reference numeral 13 denotes a third 16-moving average of the output of the second sigma-delta modulation circuit 11 using 16 taps. The 16-tap moving average digital filter 15 is a fourth 16-tap moving average digital filter connected to the third 16-tap moving average digital filter 13. The first and second 16
Tap moving average digital filters 12 and 14 constitute first moving average processing means, and third and fourth 16 tap moving average digital filters 13 and 15 constitute second moving average processing means.

Reference numeral 16 denotes a first one-cycle moving average digital filter, which is connected in parallel with the first 16-tap moving average digital filter 12. Reference numeral 17 denotes a second one-period moving average digital filter connected in parallel with the third 16-tap moving average digital filter 13. The first and second one-cycle moving average digital filters 16,
17 constitutes first and second integration means. Reference numeral 18 denotes a first multiplier which outputs the outputs of the second and fourth 16-tap moving average digital filters 14 and 15 to 1
Only one of the eight data is thinned out and input by the / 8 thinning means 141 and 151. Reference numeral 19 denotes a second multiplier, which outputs the outputs of the first and second one-period moving average digital filters 16 and 17 to 1/8 decimation means 1
According to 61 and 171, only one of the eight data is thinned out and input. Reference numeral 20 denotes a subtracter which calculates a difference between the output of the first multiplier 18 and the output of the second multiplier 19 to calculate power data w. Reference numeral 30 denotes a counter for integrating the power data w.

FIG. 2 shows an internal configuration when the first and second sigma-delta modulation circuits 10 and 11 in FIG. 1 are constituted by primary sigma-delta modulation circuits. In FIG. 2, an input X (z) is taken into an adder 31 in a unit of a sampling frequency (fs). The output of the adder 31 is
The output of the integrator 32 is connected to the comparator 33.
To output 1-bit logical data Y (z).
This output data is supplied to a 1-bit D /
The signal is fed back to the adder 31 by the A converter 34. The above configuration is called a first-order sigma-delta modulation circuit.

The input / output relational expression of the first-order sigma-delta modulation circuit shown in FIG. 2 is expressed by equation (3). Y (z) = X (z) + (1−Z ⁻¹ ) Q (z) (3) (Q (z) is noise generated by quantization) As shown in equation (3), sigma .Input signal X of delta modulation
(Z) appears as it is in the output Y (z), and the output data is information to which noise Q (z) is further added.

The above is an example of the first-order sigma-delta modulation circuit. The first and second sigma-delta modulation circuits 10 and 11 in FIG. 1 are constituted by the second-order sigma-delta modulation circuit shown in FIG. You can also. In the case of the second-order sigma-delta modulation circuit shown in FIG. 3, adders 41 and 46 and integrators 42 and
47 each have a two-stage configuration, and the other components are the same as those of the primary sigma-delta modulation circuit shown in FIG. The input / output relational expression of the secondary sigma-delta modulation circuit shown in FIG. Y (z) = X (z) + (1−z ⁻¹ ) ² Q (z) (4) (Q (z) is noise generated by quantization) Equation (4) is also a first-order sigma. As with the delta modulation circuit,
The input signal X (z) appears on the output Y (z) as it is,
The output data is information to which noise Q (z) is further added. Here, the difference between Expressions (3) and (4) is only the difference in the quantization noise distribution caused by the noise (Q (z)) which is the second term in each expression.

FIG. 4 shows a distribution spectrum of quantization noise generated by the modulation operation of the second-order sigma-delta modulation circuit. As shown in FIG. 4, the quantization noise in the low frequency range is small and the quantization noise in the high frequency range is large. The same distribution of quantization noise is shown in the case of the first-order sigma-delta modulation circuit shown in FIG. 2, but the second-order sigma-delta modulation circuit of FIG. It has the characteristic of becoming smaller.

Therefore, in the first embodiment of the present invention shown in FIG.
Sampling frequency fS = 122.88 kHz, first and second sigma-delta modulation circuits 10 and 11 using the secondary sigma-delta modulation circuit shown in FIG.
The operation will be described. As mentioned above, the first and second sigma
The outputs of the delta modulation circuits 10 and 11 are 1-bit serial logic data obtained by adding quantization noise to an input signal and having a sampling rate of 122.88 kHz. Therefore, the first and third 16-tap moving average digital filters 12 and 13 shown in FIG. 1 serve as low-pass filters for attenuating quantization noise in a high frequency range. Normal,
As shown in FIG.
1, 52, 53, multipliers 54, 55, 56, 57 and adders 58, 59, 60. The elements which determine the shape of the low-pass filter in the digital filter shown in FIG. 5 include coefficients a0, a1, a2,..., A15.
a1 = a2 =... = a15 = 1. Therefore, in the case of the moving average digital filter, the multipliers 54, 55, 56, and 57 shown in FIG. 5 are not required and can be realized with a very simple configuration.

The digital filter shown in FIG. 5 (the coefficient an is not only 1) can be realized by combining the first and second 16-tap moving average digital filters 12 and 14 of the configuration shown in FIG. In this case, the first and second 16-tap moving average digital filters 12, 14 are:
H (z) = (1 + Z ^-1 +... + Z ^-15 ) (1 + Z ^-1 +
.. + Z ^-15 ) and expanding the equation, H (z) =
(1 + 2Z ^-1 + 3Z ^-2 , ... + 3Z ^-28 + 2Z ^-29 +
Z- ³⁰ ). That is, when the coefficient an is (1, 2, 3,.
., 3, 2, 1), and the digital filter shown in FIG. 5 having 31 taps is equivalent to a two-stage moving average digital filter. Third and fourth 1 shown in FIG.
The same applies to the case of the 6-tap moving average digital filters 13 and 15.

Therefore, the signals are passed through first and third 16-tap moving average digital filters 12 and 13 and further to second and fourth 16-tap moving average digital filters 14 and 15.
FIG. 6 shows the distribution spectrum of the output quantization noise after passing through FIG.
Shown in The 8-bit width output data of the second 16-tap moving average digital filter 14 corresponding to the analog current signal i and the 8-bit width output data of the fourth 16-tap moving average digital filter 15 corresponding to the analog voltage signal v are: Each of them is 8 by the 1/8 thinning-out means 141 and 151.
After performing a thinning-out operation of extracting one output data from the pieces of output data, the first multiplier 18 calculates the power.

Considering the accuracy of the power, the voltage data V and the current data I input to the first multiplier 18 are expressed by equations (5) and (6). V = VS + ΣVN
(VS is the input signal, VN is the quantization noise for each frequency)
(5) I = IS + ΣIN (IS is an input signal, IN is quantization noise for each frequency) (6) Power W and power error ε
Is expressed by equations (7) and (8). W = VI = VS ・ IS + VS ・ NS + VNS ・ IS + Σ (VN ・ IN) (7) (where VNS is quantization noise of a voltage signal frequency component, INS
Is the quantization noise of the current signal frequency component) Here, in the case of the first embodiment, VS = 0 dB, IS = -42
As dB (1/120 of the maximum input), from the quantization noise level shown in FIG. 6, INS = -110 dB, VNS = -110 dB, and the quantization noise level for each frequency is, on average, IN.
= −80 dB, VN = −80 dB or less. Therefore,
From the equation (8), power accuracy of ε 電力 0.16% can be secured.

If a sigma-delta modulation circuit is used, it is possible to perform A / D conversion with a smaller bit width and higher precision than the conventional multi-bit successive approximation A / D conversion.

In the case of the successive approximation type A / D conversion, the precision of the quantized current value is set to 0.5 as described in the background art.
%, An A / D converter with a resolution of 11 to 12 bits is required. The successive approximation type A / D converter includes a D / A converter that generates an analog voltage corresponding to an output value, and a comparator that compares an output voltage with a signal input voltage.
In the A / D conversion, it is general to search for a value having the smallest difference between the instantaneous value of the input voltage and the output of the D / A converter into two parts. Therefore, a D / A converter that is equal to the resolution at which the A / D conversion is performed is finally required. However, in order to achieve an accuracy exceeding 10 bits at a high conversion speed, laser trimming or the like is required in production. It is necessary to make corrections to increase accuracy. In the case where the MOS is realized with a high integration rate of the LSI, a capacitor is usually used as an element element of the D / A converter. The LSI has a property that a relative error with respect to the same shape is small. In a D / A converter which needs to have an integer ratio, elements of the same shape are arranged. However, 16 when fabricating the D / A converter of the bit, if made of 2 ¹⁶ capacitors, it is necessary to below 0.2% of the variation in the capacitance value by the standard deviation. (When one capacitor has a size of 5 μm square, the dimensional variation must be 4.9 nm or less.) Even if the variation is achieved as required, the area of only the capacitor excluding the isolation region and the wiring region is about 1.3 mm. This is a corner, and requires a very large area as an LSI. Therefore, it is difficult to ensure accuracy unless laser trimming or the like is used.

When this successive approximation type A / D converter is a monolithic IC (LSI), 11-12 resistors having the same resistance value are required for each bit. It must be formed on a semiconductor. in this case,
As described above, it is difficult to realize an accurate resistance value due to an error caused by the semiconductor mask or the manufacturing apparatus. On the other hand, the sigma-delta modulation circuit does not require a capacitor for each bit, so that it is easy to implement an LSI, does not require laser trimming or the like, requires only a small capacitor area, and increases conversion accuracy.

Next, considering the components of the quantization noise,
The accuracy of the sigma-delta modulation circuit varies greatly depending on the "oversampling frequency" and the "digital filter" because of its circuit configuration, and the dependence on the analog circuit is lower than that of the successive approximation type A / D converter. Therefore, the following method can be used to reduce the quantization noise. (1) Increase the "oversampling frequency" to increase the attenuation of the "digital filter". (2) The cut-off frequency is brought closer to the vicinity of the frequency of the required signal component.

In addition, even for DC input, which is a feature of the sigma-delta modulation circuit, ± bits for several bits are generated, so that an average value (moving average) is obtained. (A value that falls between one bit).

From the above, even if the number of bits is 8 bits or less in a sigma-delta modulation circuit, quantization noise is hardly contained in one bit for the above-described reason, so that the circuit has sufficient accuracy. And for reasons of 8
Even when the number of bits is less than the number of bits, an intermediate bit can be expressed, and the accuracy can be improved even if the resolution (the number of bits) is low, so that it can be applied to a watt hour meter.

Next, considering the digital filter, the digital filter is a low-pass filter,
If the output of the 6-tap moving average low-pass filter is 8 bits or less, sufficient accuracy can be ensured. This means that when the moving average of 16 taps is one stage, there is an attenuation of -20 dB or more,
When the moving average of 16 taps is two stages, there is an attenuation of -40 dB or more. Therefore, in order to keep the power error within 0.5% within a required range, sufficient attenuation can be obtained by connecting the 16-tap moving average low-pass filter in two stages in series. Therefore, accuracy can be ensured even with 8 bits or less. (Refer to the precision of equation (8) above)

By combining the sigma-delta modulation circuit and the moving average digital filter as described above,
A / D conversion, moving average calculation, and removal of high-frequency noise can be performed with a small circuit scale. In addition, highly accurate power calculation becomes possible.

Next, the means for removing the DC components of the AC current and the AC voltage will be described. The first and second sigma
In order to remove the DC component generated by the offset of the delta modulation circuits 10 and 11, etc., the first and second sigma.
The 1-bit logic outputs of the delta modulation circuits 10 and 11 are converted into first and second one-cycle moving average digital filters 16 and
17, a moving average of one cycle (2048 TAP) is obtained. That is, the DC components VDC and IDC of the voltage and the current are extracted by taking an average value for one cycle. First and second one-cycle moving average digital filters 16, 1
7 output data from 1/8 thinning means 161 and 17 respectively.
After performing a thinning operation for extracting one output data from among the eight output data according to 1, the second multiplier 19 calculates the product VDC · IDC of the DC component of the current and the voltage.

Here, assuming that V = VS + VDC (VDC is a DC component error) and I = IS + IDC (IDC is a DC component error), the current W obtained by the first multiplier 18 is expressed by equation (9). . W = VS · IS + VDC · IDC (9) Therefore, in the first embodiment, the DC component product of the second multiplier 19 is obtained from the power calculation data of the first multiplier 18 according to the equation (9). By subtracting VDC · IDC by the subtracter 20, a power error due to the DC component VDC · IDC is removed, and highly accurate data w is output.
To obtain the electric energy.

The main effect of the first embodiment is as follows.
The A / D conversion by the combination of the delta modulation circuit and the moving average digital filter enables multiplication with less bit width data than the conventional multi-bit successive approximation type A / D conversion. High-precision power calculation becomes possible. Furthermore, the analog section is only a sigma-delta modulation circuit, and the other circuits are digital circuits,
Digital circuits with a small analog scale are mainly used. Therefore, the configuration is suitable for a monolithic IC, and an extremely large effect can be expected when mass production is to be performed.
Further, since a moving average digital filter is used as the low-pass filter, a multiplier in the digital filter is not required, and the low-pass filter can be realized with a simple configuration.

As a secondary effect of the first embodiment, since the thinning-out means thins out at a rate of 1 / n (n ≧ 1), the number of times of multiplication can be reduced, and the power consumption of the circuit is reduced. In addition, since the influence of the DC component is removed by the one-cycle moving average digital filter, the power calculation error can be reduced. As described above, in the first embodiment, the quantization noise in the low frequency range can be significantly reduced, the power error can be reduced, and a highly accurate electronic watt-hour meter can be obtained with a simple circuit configuration. Further, it is easy to make a monolithic IC.

Embodiment 2 FIG. 7 shows another embodiment of the present invention. In FIG. 7, reference numerals 22 and 24 denote first and second up-down counters, which are connected to the output sides of the first and second sigma-delta modulation circuits 10 and 11, respectively. The first and second up-down counters 22, 24
Is a counter that counts up when the logic is "1" and counts down when the logic is "0" for the 1-bit logic output of the first and second sigma-delta modulation circuits 10 and 11. The up / down count value at the time of one cycle means that the DC components of the current and voltage signals are extracted.

The present embodiment has the advantage that it operates effectively even when the frequency of the input voltage signal fluctuates. A periodic signal is generated, and the first and second up / down counters 22 and 24 are generated for each one periodic signal.
Are stored and held in the latch registers 23 and 25. Therefore, the first and second latch registers 23, 25
Is always the value of the DC component of the current and the voltage. Other configurations are the same as those of the first embodiment of FIG. 1. Even if the frequency of the input voltage signal fluctuates, it is possible to perform a power calculation operation in which a power error due to a DC component of current and voltage is reduced.

Embodiment 3 FIG. 8 shows still another embodiment. This embodiment is different from the embodiment of FIG. 1 in that first and second one-period moving average digital filters 16, 1
7 and 1/8 thinning means 141, 151, 161, 17
The first and second multipliers 19 and the subtractor 20 are omitted, and the first multiplier 18a obtains the data of the power w shown in the above-mentioned equation (7). To obtain the quantity WH.

Embodiment 4 FIG. 9 shows another embodiment. This embodiment is different from the embodiment shown in FIG. 8 in that 1/8 thinning means 141 and 15 similar to those shown in the embodiment shown in FIG.
By adding 1, the number of times of multiplication is reduced by a thinning operation to reduce the power consumption of the circuit.

Embodiment 5 FIG. FIG. 10 shows still another embodiment. In this embodiment, only one sigma-delta modulation circuit is used, and its input is multiplexed (time division).
It was done. Other configurations are the same as those in the embodiment of FIG. FIG. 11 shows the internal configuration of the sigma-delta modulation circuit 10 used in this embodiment. This sigma-delta modulation circuit 10 is a modification of the above-described first-order sigma-delta modulation circuit shown in FIG. 2, and has a configuration in which capacitors C1 and C2 are selectively connected to an integrator 32 by switches SW3 and SW4. ing.

10 and 11, in the sigma-delta modulation circuit 10, a current signal i and a voltage signal v are alternately input by a switch SW1. When the current signal i is taken as an input, the switches SW3 and SW4 are connected to the capacitor C1 to hold the value in the capacitor C1, and the switch SW2 is connected to the first and second 16-tap moving average digital filters 12 and 14. To the side. Voltage signal v
When the switch SW3, SW4 is connected to the capacitor C2 in order to hold the value in the capacitor C2,
And the switch SW2 is connected to the third and fourth 16-tap moving average digital filters 13 and 15. The switches SW1, SW2, SW3 and SW4 are switched in synchronization with the sampling clock fS. According to this embodiment, the use of one sigma-delta modulation circuit 10 in a time-sharing manner has the effect of simplifying the circuit configuration.

When the second-order sigma-delta modulation circuit shown in FIG. 3 is used, the capacitor C1 is connected to the integrator 32 shown in FIG.
, C2 and switches may be provided with capacitors and switches for holding the integrated values for the integrators 42 and 47, respectively, as if SW3 and SW4 were inserted. That is, in the case of a two-element input, the integrator 42 is provided with two capacitors and one switch for switching the capacitors, and the integrator 43 is provided with two capacitors and one switch for switching the capacitors. By forming the integrated value holding means by the combination of the capacitor and the switch in this manner, two inputs of the input current and the input voltage can be processed by one sigma-delta modulation circuit. In addition, a multi-element input such as a single-phase three-wire, three-phase three-wire, and three-phase four-wire may be processed by providing a sigma-delta modulation circuit for current and voltage. That is, one sigma-delta modulation circuit can handle a plurality of inputs. The means for holding the integrated value is not limited to a capacitor, but may be any means for holding the integrated value. For example, a register with A / D conversion and D / A conversion may be used.

Embodiment 6 FIG. FIG. 12 shows an embodiment in the case of a two-element watt-hour meter for measuring the electric energy of a single-phase three-wire or three-phase three-wire. In FIG. 12, first and second sigma-delta modulation circuits 10a and 10b are respectively shown in FIG.
1. A first-order sigma-delta modulation circuit having the same configuration as that shown in FIG.
The switch SW1a alternately captures the current signal i1 on the first line and the current signal i2 on the third line in a time-sharing manner, and stores the respective values alternately in the capacitors C1 and C2 shown in FIG.

When the current signal i1 is taken in, the switch SW2a is connected to the first and second 16-tap moving average digital filters 12a and 14a. When the current signal i2 is taken in, the switch SW2a is connected to the fifth and fifth switches. It is connected to the sixth 16-tap moving average digital filters 12b and 14b. The second sigma-delta moving average digital filter 10b alternately captures the one-line voltage signal v1 and the three-line voltage signal v2 in a time-sharing manner by the switch SW1b, and stores the respective values with the capacitor C1 shown in FIG. C2
Is stored alternately.

When taking in the voltage signal v1, the switch SW2b is connected to the third and fourth 16-tap moving average digital filters 13a and 15a, and when taking in the voltage signal v2, the switch SW2b is connected to the seventh, It is connected to the eighth 16-tap moving average digital filters 13b and 15b. 18a1 multiplies current data I1 and voltage data V1 based on current signal i1 and voltage signal v1 to obtain power W
1, a multiplier 18b1 for multiplying the current data I2 and the voltage data V2 based on the current signal i2 and the voltage signal v2 to calculate the power W2, and a multiplier 50 for the multiplier 1
This is an adder that adds the outputs of 8a1 and 18b1 to obtain power data w. Naturally, when the first sigma-delta modulation circuit 10a is taking in the current data i1, the second sigma-delta modulation circuit 10b is taking in the voltage data v1. When i2 is fetched, voltage data v2 is fetched. According to this embodiment, the multipliers 18a1, 18b1
Are added by the adder 50 to obtain power data w of a single-phase three-wire system or a three-phase three-wire system, and this is integrated by the counter 30 to obtain the power amount WH.

Embodiment 7 FIG. FIG. 13 shows another embodiment. In this embodiment, the moving average filter connected to each of the first and second sigma-delta modulation circuits 10 and 11 has only one stage, and the moving average filter has a moving average tap number of 256 taps. First and second 256 tap moving average digital filter 1
21 and 131. 1st and 2nd above
56 tap moving average digital filters 121 and 131
Is an 8-bit output. The outputs of the first and second moving average digital filters 121 and 131 are 1/32 decimation means 141a and 151 at a ratio of one for every 32 filters.
The signal is decimated by a and guided to the multiplier 18a to obtain a signal w corresponding to the power and a power amount WH obtained by integrating the signal w by the counter 30.

According to the above-described first to seventh embodiments, the A / D conversion by the combination of the sigma-delta modulation circuit and the moving average digital filter is more effective than the conventional multi-bit successive approximation A / D conversion. Multiplication can be performed with small bit width data, and highly accurate power calculation can be performed with a multiplier having a small circuit scale. Further, the analog section is only a sigma-delta modulation circuit, and the other circuits are digital circuits, and mainly digital circuits having a small analog scale. Therefore, the configuration is suitable for a monolithic IC, and an extremely large effect can be expected when mass production is to be performed. Further, since a moving average digital filter is used as the low-pass filter, a multiplier in the digital filter is not required, and the low-pass filter can be realized with a simple configuration.

Embodiment 8 FIG. This embodiment provides an electronic watt-hour meter slightly different from the configuration of the first embodiment. FIG. 14 shows this embodiment, and shows a case of a two-element power amount for measuring the power amount of a single-phase three-wire or three-phase three-wire. FIG. 15 is an operation explanatory diagram, and FIG.
6 is an operation explanatory diagram in which the time axis of FIG. 15 is enlarged. In the figure, first and second sigma-delta modulation circuits are sigma-delta modulation circuits shown in FIG. 2 or FIG. The first digital low-pass filter 80 and the second digital low-pass filter are the digital low-pass filters shown in FIG. 5, and have n delay means. The thinning means 181 and 182 perform 1 / m thinning. The value of m is equal to or larger than n.

Then, the switch SW5 takes in i1, and at that time, the switch SW6 takes in v1. on the other hand,
The switch SW7 is connected to the i1 register, and the switch SW7
8 connects to the v1 register. A first digital low-pass filter 8 via a first sigma-delta modulation circuit 10
The sample value sequence of the alternating current is output by 0, but the thinning means 181 operates to take in the m-th sample value sequence into the i1 register 191 after the switches SW5 and SW6 are selected. Second sigma-delta modulation circuit 11
The sample value of the AC voltage is output by the second digital low-pass filter 81 via the switch. However, in the thinning means 182, after the switches SW6 and SW8 are selected, the operation of taking in the m-th sample value sequence into the v1 register is performed. do.

This operation is performed as shown in FIG.
, V1, i10 and v10 are i1 registers 191, v1
The data is taken into the register 201, respectively. FIG. 16 shows the details, in which the value of m is 8, and the eighth i17 of the sample value sequence of i10 to i17 is thinned out for the input i1 and stored in the i1 register 191 as i1b. v
The eighth v17 in the sample value sequence of v10 to v17 for 1
Is thinned out and stored in the v1 register 201 as v1b. In this manner, i1a, i1b, i1c,.
1a, v1b, v1c,...

The obtained i 1, i 2, v 0, v 1,
The quantized data (i1a, i1b, v1a, v1b) of v2 is calculated by the multipliers 18c and 18d and the adder 50 as w = (i1 ×
v1) + (i2.times.v2) are processed and integrated by the counter 30 to obtain the electric energy. Thereafter, the same operation is repeated. As the first and second digital low-pass filters 10 and 11 use the digital low-pass filters shown in FIG. 5, as described in the first embodiment,
Sufficient precision can be maintained even with an output of less than bits.

The effect of the eighth embodiment is that a single-phase three-wire, three-phase three-wire,
In the case of a multi-element input such as a phase 4 wire, the sigma-delta modulation circuit and the data low-pass filter can be shared, and the circuit scale is reduced and the configuration is inexpensive. In the case of single-phase two-wire instead of multi-element input, the present invention can be applied to a circuit that does not require switch switching.

Embodiment 9 This embodiment provides an electronic watt-hour meter provided with an offset adjusting means capable of adjusting an offset.
FIG. First and second sigma-delta modulation circuits 1
The configurations of 0, 11, the first and second digital low-pass filters 80, 81, and the thinning means 181 and 182 are the same as those of the eighth embodiment.
Offset register 203, subtractors 21a, 21b, 2
1c and 21d are provided.

In the present embodiment, the input SW 9 and the input S
In selecting W10, first, the reference potential GND
Signals, respectively, and the i-offset register 19
The data is fetched and stored in the 3 and v offset registers 203. Thereafter, as shown in the operation explanatory diagram of FIG. 18, i1 and i2 are alternately fetched on the current side, and v1 on the voltage side.
, V2 are alternately fetched. At that time, i1 register 19
1. Data is taken into the i2 register 192, the v1 register 201, and the v2 register 202 by the same operation as in the eighth embodiment. The quantized data fetched into each register is output to the subtracters 21a, 21b, 21c, 21d, the multiplier 1
8c, 18d, w = (i1−i offset) × (v1−v offset) + (i2−i offset) × (v
2-v offset) is calculated and integrated by a counter to obtain the electric energy. That is, the offset power is corrected by subtracting the offset power from the power before the offset adjustment.

The advantage of the ninth embodiment is that the DC offset which is present in the analog circuit and causes an error in the measurement of the amount of power can be accurately corrected with a small circuit configuration without increasing the number of sigma-delta modulation circuits and digital low-pass filters. A watt-hour meter can be realized.

Embodiment 10 FIG. This embodiment is a modification of the ninth embodiment and is shown in FIG. i1 register 19
1, i2 register 192, i offset register 19
3. The configuration and operation of the v1 register 201, v2 register 202, and v offset register 203 are the same as in the ninth embodiment. The subsequent arithmetic circuit is different, and w =
(I1 x v1)-(i offset x v offset) + (i2 x v
2) The arithmetic processing of-(i offset × v offset) is performed, and integrated by the counter 30 to obtain the electric energy. The result is the same as that of the ninth embodiment, and correction is performed by subtracting the offset power from the power before the offset adjustment. Therefore, the same effect as that of the ninth embodiment can be obtained.

Embodiment 11 FIG. This embodiment is a modification of the ninth embodiment and the tenth embodiment.
9, the switch SW9 is connected to GND, i1,
i2 and the switch SW10 are set to GN
D, v1, and v2 are sequentially and repeatedly fetched. In response to this operation, the switches SW11 and SW12 are sequentially switched including the i offset register 193 and the v offset register 203. FIG. 20 is a diagram for explaining the operation, in which the offset current and the offset voltage are sequentially measured at that time and used for adjustment.

The effect of this embodiment is that i offset,
Since the v-offset is always taken in, it is hard to be affected by fluctuations of the DC offset in the analog circuit due to temperature, aging, and the like, and a highly accurate electronic watt-hour meter can be realized.

Embodiment 12 FIG. This embodiment provides an electronic watt-hour meter provided with a delay means capable of adjusting a voltage phase angle. FIG. 21 is a block diagram. This configuration is different from the configuration of the eighth embodiment in that a P-stage shift register 211 is provided between the second sigma-delta modulation circuit 11 and the second digital low-pass filter, and P1 that determines the number of P-stage shifts is provided. Register 212
And a P2 register 213. And the thinning means 181 and the thinning means 182 are 1 / (m +
P) Perform thinning. The value of m is equal to or greater than n (n is the number of stages of the digital low-pass filter in FIG. 5).

When the AC voltage signal v1 is taken in,
The P-stage shift register 211 is connected to the second digital low-pass filter 81 from the output of the number of shift stages corresponding to the P1 value stored in the P1 register 212.
Therefore, the AC voltage signal v1 is delayed in phase by the time corresponding to the number of shift register stages of the P-stage shift register 211 as compared with the AC current signal i1. Similarly, when the AC voltage signal v2 is taken in, the P-stage shift register 211 is connected to the second digital low-pass filter 81 from the output of the number of shift stages corresponding to the P2 value stored in the P2 register 213. . Therefore, P is smaller than AC current signal i1.
The AC voltage signal v2 is delayed in phase by the time corresponding to the number of shift register stages of the stage shift register 211.

The effect of this embodiment is that the AC current signal is generally detected by CT, and the AC voltage signal is generally detected by VT. At this time, a phase angle error occurs between the primary side and the secondary side due to the detection elements of CT and VT. A VT phase angle error can be eliminated, and a highly accurate electronic watt-hour meter with a small circuit scale can be obtained.

Embodiment 13 This embodiment provides an electronic watt-hour meter provided with a delay means capable of adjusting the current phase angle. FIG. 22 shows a block diagram of the electronic watt-hour meter. This configuration is different from that of the eighth embodiment in that the P-stage shift register 214 and the P1 register 2
15 and a P2 register 216 are provided on the current side. Therefore, compared with the AC signals v1 and v2, the AC signals i1 and i2 can be delayed in phase by the number of shift register stages of the P-stage shift register. Further, when this embodiment and the twelfth embodiment are combined, the voltage / current co-phase angle can be freely adjusted.

Embodiment 14 This embodiment relates to an electronic power supply provided with balance adjusting means capable of performing balance adjustment in the case of multi-element measurement such as single-phase three-wire, three-phase three-wire, three-phase four-wire, or the like. FIG. 23 shows a block diagram of a three-element watt-hour meter which provides a watt-hour meter for measuring the power amount of three-phase four-wire.

In the figure, i1 register 191, i2 register 192, i3 register 194, v1 register 20
The configuration up to a 1, v2 register 202 and a v3 register 203 is the same as that of the eighth embodiment except that the three-phase four-wire configuration is used. Therefore, balance adjustment registers 221 and 222 are provided, and SW13 is first used before the operation of the watt hour meter.
And SW14 are connected to the i1 and v1 sides, and a reference current and a reference voltage are inputted.
1 and the value of the v1 register 201, w1 = i1 × v
Calculate and store 1.

Next, SW13 and SW14 are connected to the i2 and v2 sides, a reference current and a reference voltage are inputted, and based on the values of the i2 register 192 and the v2 register 202 obtained at that time, w2 = i2.times.v2 Is calculated, and a value of B2 = w1 / w2 is set in the balance adjustment register 221. Next, SW13 and SW14 are connected to the i3 and v3 sides, a reference current and a reference voltage are input, and based on the i3 register 194 and the v3 register 204 obtained at that time, w
3 = i3 × v3, and the balance adjustment register 222
Is set to B3 = w1 / w3. The preparation is completed as described above, and thereafter SW13 and SW14 are sequentially switched in the same manner as in the eighth embodiment, w = (i1 × v1) + (i2 × v2 × B2) +
(I3.times.v3.times.B3) is processed and integrated by the counter 30 to obtain the electric energy. In the case of a single-phase three-wire system and a three-phase three-wire system, the balance of i1, i3, v1, and v3 can be checked.

The effect of this embodiment is that in the case of multi-element measurement, each element has an error generating factor such as VT and CT.
Therefore, the balance adjustment register 221 and the balance adjustment register 222 are used to adjust the measurement accuracy between the elements.
And adjusting the value in the register, a highly accurate watt-hour meter can be obtained.

Fifteenth Embodiment A fifteenth embodiment provides an electronic watt-hour meter provided with balance adjusting means capable of performing a balance adjustment, as in the fourteenth embodiment. FIG. . In the structure of the fourteenth embodiment, w = (i1 × v1
) + (I2 × v2) × B2 + (i3 × v3) × B3
The operation is the same as that of the fourteenth embodiment except that the positions of the multipliers 18g and 18h for calculating B2 and B3 are different among the arithmetic circuits for calculating B2 and B3. The effects of this embodiment are the same as those of the fourteenth embodiment.

Embodiment 16 This embodiment provides an electronic watt-hour meter provided with anti-movement means for preventing start-up when there is no input. FIG. FIG. 2 is a block diagram showing a case of a one-element watt-hour meter. FIG. 27a shows the operation waveform. In the figure, first and second sigma-delta modulation circuits 10 and 11 are the same as the sigma-delta modulation circuits shown in FIG. 2 or FIG. 3, and first and second digital low-pass filters 80 and 81. Is the same as the digital low-pass filter shown in FIG.

The AC current signal i and the current voltage signal v are A / D-converted by sigma-delta modulation circuits 10 and 11 and first and second digital low-pass filters 80 and 81.
Is converted. The A / D converted current data and voltage data are multiplied by a multiplier 50 to calculate instantaneous power data.
The instantaneous power data is output from the output (w0) and the accumulator 231 and the register 232 to obtain wn = w0 + wn-.
1 (wn is the output value of the register 232 at the time tn, wn-1 is the output value of the register 232 at the time tn-1) (FIG. 27a).

In the waveform of FIG. 27A, the output of the register 232 is on the negative side only when the power factor is 1, but when the power factor is other than 1, a negative component is generated as instantaneous power. Is a waveform as shown in the figure.

The output value wn of the register is compared with the rated reference value set in the rated reference value setting unit 234. If wn-rated reference value ≧ 0, the magnitude comparator 233 is output.
Is output (FIG. 27a), and (wn-rated reference value) is set in the register 232. On the other hand, the pulse output from the magnitude comparator 233 is compared with the starting reference value (S) of the starting reference value setting unit 236 in the pulse period detection circuit 235, and if the pulse output period (T) <S, a signal to open the AND gate is output. If the pulse output period (T) ≧ S, a signal to close the AND gate is output (FIG. 27A). Accordingly, the output of the AND gate 237 has a pulse output when the pulse period is smaller than the starting reference value, and does not output a pulse when the pulse period is longer than the starting reference value (FIG. 27A). This pulse is output to counter 3
At 0, the electric energy is obtained by cumulative addition. That is,
If the amount of power per hour is small, the amount of power is not counted.

The effect of this embodiment is that the accumulator 231, the register 232, and the magnitude comparator 233 output a pulse, and the pulse period is detected to detect the starting current. It has a function to prevent unintentional movement to prevent useless measurement by components.

Embodiment 17 This embodiment provides an electronic watt-hour meter provided with anti-movement means for preventing start-up when there is no input, as in Embodiment 16. FIG. Measuring the amount of power in a line 1
FIG. 3 shows a block diagram for an element watt hour meter. FIG.
The operation waveform is shown in FIG.

The configuration is the same as that of the sixteenth embodiment except that a third digital low-pass filter 82 is provided. After passing through a third digital low-pass filter 82, wn = w0 + wn-
1 (wn is the output value of the register at time tn, wn-
1 performs an arithmetic operation on the output value of the register 232 at the time tn-1 (FIG. 27B). The subsequent operation is the same as in the sixteenth embodiment. Here, when the signal passes through the third digital low-pass filter 82, the output of the register 232 becomes as shown in FIG.
The result is averaged as shown in FIG.

The effect of this embodiment is that the addition of the third digital low-pass filter 82 makes it possible to detect the starting current with higher accuracy.

Embodiment 18 This embodiment provides an electronic watt-hour meter provided with a light-load adjusting means for adjusting at light load, and a block diagram is shown in FIG. The configuration is such that a light load adjustment setting device (register) 241 and an adder 50 for adding the light load adjustment value are provided in FIG. 25 of the sixteenth embodiment.

The light load adjustment value L in the light load adjustment setting unit 241 is added to the quantized power value output from the multiplier 18j.
Is added to perform light load adjustment. The reason for this light load adjustment is that when using the CT, which is an AC current detection element,
As shown in FIG. 29, since a small current region tends to have a minus error, the CT error is corrected by adding a constant value L in the light load adjustment register 241. In the expression, wn = (w0 + L) + wn-1 (wn is the time tn
, And wn-1 is the output value of the register 232 at time tn-1). The operation after the addition of the light load adjustment value is the same as in the sixteenth embodiment. This light load adjustment value is added as a constant value not only in the light load but also in other regions other than the light load, but since this value is small, the ratio of the error in other regions can be ignored.

The effect of the present invention is to correct a CT error at a light load and to obtain a highly accurate watt hour meter.

Nineteenth Embodiment In the eighteenth embodiment, the light load adjustment value is added in a region other than the light load condition. In this embodiment, the light load adjustment value is added only at the light load condition. FIG. 30 shows this embodiment, in which 242 is a comparator, 243 is a reference current setter (register) for setting a reference current value, and SW 17 is a switch opened and closed by the comparator 242.

When the light load adjustment value L is added, the current value from the first digital low-pass filter 80 causes the comparator 242 not to operate when the current value is equal to or less than the reference current value at a light load, and the switch SW17 is turned on. The light load adjustment value is connected to the light load adjustment setting device, and the light load adjustment value is added. When the current value is other than the light load and is equal to or larger than the reference current value, the comparator 242 is activated, and the switch SW17 is not connected to the light load adjustment setting device. Adjustment value is not added. The operation after the addition of the light load adjustment value is the same as in the sixteenth embodiment. The effect of this embodiment is the same as that of the eighteenth embodiment, but the light load adjustment value is added only at the time of light load, so that a more accurate electronic watt-hour meter can be provided.

Embodiment 20 This embodiment provides an electronic watt-hour meter capable of measuring the measuring accuracy in a minute current range in a short time. FIG. 31 is a block diagram. In the configuration of the eighteenth embodiment, a third digital low-pass filter 82 is provided between the multiplier 18j and the adder 50, and a first register 2 for storing the value of w0 + L between the adder 50 and the accumulator 231.
51, and a register on the output side of the accumulator 231 is a second register 252.

Next, the operation will be described. The addition of the third digital low-pass filter 82 and the light load is performed in synchronization with the operation clock (CLK) frequency f and the first register 251.
To memorize. On the other hand, in the circuits subsequent to the accumulator 231, the operation clock (CLK) frequency is executed in synchronization with the speed of n times f. That is, the value (w0 + L) stored in the first register 251 is cumulatively added n times,
It is stored in the second register 252. Thereafter, the magnitude comparator 233 performs the same operation as that of the eighteenth embodiment, and accumulates the pulses by the counter 30 to obtain the electric energy.

The effect of this embodiment is that the pulse output interval time from the magnitude comparator 233 is shortened, so that the measurement accuracy can be measured in a short time especially in a minute current range. In this embodiment, the light load adjustment value is added, but the light load adjustment setting device is omitted in the sixteenth embodiment.
Also, the present invention can be applied to the circuit of the seventeenth embodiment, and a similar effect is obtained.

Embodiment 21 This embodiment is a summary of a typical three-phase four-wire electronic watt-hour meter, in which necessary adjustment means for measuring the amount of power are incorporated to perform necessary adjustment. It is like that. FIG. 32 is a block diagram, and FIG. 33 is a flowchart of the adjustment. In this configuration, the same reference numerals as those in the above-described embodiment represent the same functions. Where 26
Reference numeral 1 denotes a display for displaying the integrated electric energy, 260 denotes an arithmetic control circuit for controlling the entire arithmetic operation, 270 denotes the entire electronic watt-hour meter, and 301 denotes an analog reference generator for inputting a reference input value. Here, L is a light load adjustment value setting device 241 for setting the light load adjustment value L, and F is a rated reference value setting device 234 for setting the rated reference value F.

The operation will be described. First, before starting the continuous measurement of the electric energy, the arithmetic and control circuit 260 has the adjustment mode and performs the next operation.

The same analog value (for example, both current and voltage are set to 1) from the analog reference generator 301 to CT1 and VT1.
00%). Note that CT2, CT3, VT2,
VT3 = 0 The entire circuit is operated in that state, and the output (w0) of the third digital low-pass filter 82 at that time is stored. [This is w01. ]

The same analog value is input to CT2 and VT2. Note that CT1, CT3, VT1, VT3 =
0, the entire circuit is operated in that state, and the output (w0) of the third digital low-pass filter 82 at this time [w
02. ] Is set and the value of B2 = w01 / w02 is set in the balance adjustment register 221.

The same analog value is input to CT3 and VT3. Note that CT1, CT2, VT1, VT2 =
0, the entire circuit is operated in that state, and the output (w0) of the third digital low-pass filter 82 at this time [w
03. ] Is set in the balance adjustment register 222 such that B3 = w01 / w03.

The same analog value is input from the analog reference generator 301 to CT1 and VT1, and a value of F = (w01 / reference power) × rated reference value is set in the rated reference value setting unit 234. Here, the reference power is a calculated value obtained by multiplying the voltage and current from the analog reference generator 301,
The rating reference value is a calculated value (constant) that determines the number of pulses per power amount. F is a corrected rating reference value, which is set as a new rating reference value. That is, the input electric energy (the value of the register 232) becomes the electric energy corrected based on F (the output of the magnitude comparator), and the accurate electric energy (the value of the counter 30) is measured.

The value input in VT1 is changed to CT1
The value of 1 / n of the input analog value is input to, and CT2, CT3, VT2, and VT3 = 0. The output of the third digital low-pass filter 82 at that time (w
0) [This is w0n. ], L = (w01 / n)-
The value w0n is set as a light load adjustment value in the light load adjustment value setting device.

An analog signal having the same effective value and a power factor = 0.5 is input to CT1 and VT1. Note that CT
2, CT3, VT2, VT3 = 0. The output (w0) of the third digital low-pass filter 82 at this time [this is defined as w0p1. ], P1 = K · (w01 / 2−W
0p1) The value w01 / 2 is set in the P1 register 212. (K is a constant)

An analog signal having the same effective value and a power factor = 0.5 is input to CT2 and VT2. Note that CT
1, CT3, VT1, and VT3 = 0. The output (w0) of the third digital low-pass filter 82 at this time [this is defined as w0p2. ], P2 = K · (w01 / 2−w
0p2) The value w01 / 2 is set in the P2 register 213. (K is a constant)

An analog signal having the same effective value and a power factor = 0.5 is input to CT3 and VT3. Note that CT1, C
It is assumed that T2, VT1, and VT2 = 0. The output (w0) of the third digital low-pass filter 82 at that time [w0
Set to 0p3. ], P3 = K · (w01 / 2−w0p3)
The value w01 / 2 is set in the P3 register 217. (K
Is a constant). Each set value is set in the following order, and then the electric energy is measured based on the set value determined.

FIG. 33 shows a flowchart of this adjustment operation. The adjustment work can be automatically performed according to such a flow. If the characteristics (ratio error) of VT and CT can be manufactured within a predetermined range, the balance adjustment becomes unnecessary. When a CT having a good light load characteristic is used, light load adjustment is not required. VT,
If the phase angle characteristic of the CT can be manufactured within a predetermined range, the phase angle adjustment of (1) becomes unnecessary. on the other hand,,
Is a constant determined by the sampling frequency fs and the commercial frequency f0, and K = 100 on the assumption that the phase error is 1 minute and the power error is about 0.05%.
/360×60×0.05×(f0/fs).

The effect of this embodiment is that, since the means for adjusting the error is provided, a high-precision electronic watt-hour meter can be obtained, and each adjustment value is set and stored as a digital numerical value. It can be manufactured on an automated line that eliminates the need for an inexpensive electronic watt-hour meter.

[0107]

According to the first and second aspects of the present invention, the quantization noise in the low frequency range can be greatly reduced, the power error is reduced, and a high-precision electronic watt-hour meter has a simple circuit configuration. Has the effect that can be obtained. Especially monolithic IC (LS
In the case of I), the circuit is simplified and the effect is large.

According to the third aspect of the present invention, the moving average of one cycle of the AC current and the AC voltage is performed, and the power calculation error due to the influence of the DC component can be reduced.

According to the fourth aspect of the present invention, the zero crossing of the AC voltage is detected by the zero crossing detecting means, and the quantized AC current and one cycle of the AC voltage are detected based on the zero crossing. In addition, there is an effect that the influence of the direct current components of the current and the voltage can always be removed even if the frequency fluctuates.

According to the fifth and sixth aspects of the present invention, two sigma-delta modulation circuits can cope with the input of multiple elements, and the use of time division makes it possible to simplify the circuit configuration.

According to the seventh aspect of the present invention, since the offset adjusting means is provided, there is an effect that the offset power value can be corrected and the measurement accuracy can be improved.

According to the eighth aspect of the present invention, the calculation of the offset power is performed at a predetermined cycle, and the offset value is always corrected, so that there is an effect that the measurement accuracy can be further improved.

According to the ninth aspect of the present invention, since the phase angle error is corrected by adjusting the voltage phase angle and / or the current phase angle by the delay means, the effect of improving the measurement accuracy can be obtained. is there.

According to the tenth aspect of the present invention, the phase angle is adjusted by the shift register capable of shifting the desired number of shifts to correct the phase angle error, so that the measurement accuracy can be improved. effective.

According to the eleventh aspect of the present invention, in the measurement of the electric energy of the multi-element, since the balance is corrected by providing the balance adjusting means, there is an effect that the measurement accuracy can be improved.

According to the twelfth aspect of the present invention, since the anti-movement means is provided to reduce the weighing error when there is no input power, the weighing accuracy can be improved.

According to the thirteenth aspect of the present invention, since the latent output of the output having passed through the third low-pass filter is prevented, the weighing error when there is no input power is reduced.

According to the fourteenth aspect of the present invention, the light load adjusting means is provided so that a predetermined light load adjustment value is added at least when the load is light, so that there is an effect of reducing the measurement error at the light load.

According to the fifteenth aspect of the present invention, the power amount is measured at an operating clock frequency of n times the frequency f, so that the measurement accuracy can be measured in a short time, and in particular, the minuteness can be measured. There is an effect that measurement of measurement accuracy in a current range can be performed in a short time.

According to the sixteenth aspect of the present invention, since the rating value adjusting means is provided so as to output the power value corrected by the rating reference value, it is possible to measure the power amount with high accuracy.

According to the seventeenth aspect of the present invention, by providing a means for setting and storing each adjustment value as a digital numerical value, the accuracy is improved, and automatic setting without manual setting becomes possible. Since it can be produced on a line, there is an effect that an inexpensive and highly accurate electronic watt-hour meter can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram of an example of a first-order sigma-delta modulation circuit.

FIG. 3 is a block diagram of an example of a second-order sigma-delta modulation circuit.

FIG. 4 is a graph showing an example of a quantization noise spectrum distribution of a second-order sigma-delta modulation circuit.

FIG. 5 is a block diagram of an example of a digital filter constituting a low-pass filter.

FIG. 6 is a graph showing an example of a quantization noise spectrum distribution after a moving average digital filter.

FIG. 7 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 2 of the present invention.

FIG. 8 is a block diagram of a power calculator of an electronic watt-hour meter according to Embodiment 3 of the present invention.

FIG. 9 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 4 of the present invention.

FIG. 10 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a fifth embodiment of the present invention.

FIG. 11 is a block diagram of an example of a first-order sigma-delta modulation circuit used in Embodiments 5 and 6 of the present invention.

FIG. 12 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 6 of the present invention.

FIG. 13 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a seventh embodiment of the present invention.

FIG. 14 is a block diagram of a power calculation unit of an electronic watt-hour meter according to an eighth embodiment of the present invention.

FIG. 15 is a diagram illustrating the operation of FIG.

16 is an operation explanatory diagram of FIG.

FIG. 17 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a ninth embodiment of the present invention.

FIG. 18 is an operation explanatory diagram of FIGS. 17 and 19;

FIG. 19 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a tenth embodiment of the present invention.

FIG. 20 is an operation explanatory diagram of the eleventh embodiment of the present invention.

FIG. 21 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a twelfth embodiment of the present invention.

FIG. 22 is a block diagram of a power calculator of an electronic watt-hour meter according to a thirteenth embodiment of the present invention.

FIG. 23 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a fourteenth embodiment of the present invention.

FIG. 24 is a block diagram of a power calculator of an electronic watt-hour meter according to a fifteenth embodiment of the present invention.

FIG. 25 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a sixteenth embodiment of the present invention.

FIG. 26 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a seventeenth embodiment of the present invention.

FIG. 27 is an operation explanatory diagram of FIGS. 25 and 26.

FIG. 28 is a block diagram of a power calculation unit of an electronic watt-hour meter according to Embodiment 18 of the present invention.

FIG. 29 is a diagram showing output characteristics of CT according to the embodiment 08 of the present invention.

FIG. 30 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a nineteenth embodiment of the present invention.

FIG. 31 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a twentieth embodiment of the present invention.

FIG. 32 is a block diagram of a power calculation unit of an electronic watt-hour meter according to a twenty-first embodiment of the present invention.

FIG. 33 is a flowchart showing the adjustment operation of FIG. 32;

FIG. 34 is a block diagram of a power calculator of a conventional electronic watt-hour meter.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 1st sigma-delta modulation circuit 10a 1st sigma-delta modulation circuit 10b 2nd sigma-delta modulation circuit 11 2nd sigma-delta modulation circuit 12 1st 16-tap moving average digital filter 12a 1st 16 tap moving average digital filter 12b Fifth 16 tap moving average digital filter 13 Third 16 tap moving average digital filter 13a Third 16 tap moving average digital filter 13b Seventh 16 tap moving average digital filter 14 Second 16 tap moving average digital filter 14a second 16 tap moving average digital filter 14b sixth 16 tap moving average digital filter 15 fourth 16 tap moving average digital filter 15a fourth 16 tap moving average digital filter 15b Eighth 16-tap moving average digital filter 16 First one-period moving average digital filter 17 Second one-period moving average digital filter 18 First multipliers 18a, 18a1, 18b1, 18c, 18d, multipliers 18e, 18f, 18g, 18h, 18j Multiplier 19 Second multiplier 20 Subtractors 21a, 21b, 21c, 21d, 21e, 21f Subtractor 22 First up / down counter 23 First latch register 24 Second up / down counter 25 Second latch register 26 Zero-cross detection 27 1/2 frequency division 30 Counter 31 Adder 32 Integrator 33, 43 Comparator 34 1-bit D / A converter 35, 45 Delay means 41, 46, 50, 50a Adder 42 , 47 Integrator 44 1-bit D / A converter 51, 52, 53
Delay means 54, 55, 56, 57, 73 Multipliers 58, 59, 60 Adders 71 First successive approximation type A / D converter 72 Second successive approximation type A / D converter 80 First digital low-pass Filter 81 second digital low-pass filter 82 third digital low-pass filter 121 first 256-tap moving average digital filter 131 second 256-tap moving average digital filter 141, 151, 161, 171 1/8 decimation means 141a, 151a, 141b, 151b 1/8 thinning means 141a1, 151a1 1/32 thinning means 181 182 thinning means 191 i1 register 192 i2 register 193 i register 194 i3 register 201 v1 register 202 v2 register 203 v register 204 v3 211, 214 P
Stage shift register 212,215 P1 register 213,216 P2
Register 217 P3 register 221, 222 Balance adjustment register 231 Accumulator 232 Register 233 Magnitude comparator 234 Rated reference value setting device 235 Pulse period detection circuit 236 Start reference value setting device 237 AND circuit 241 Light load adjustment value setting device 242 Comparator 243 Reference current setting Instrument 251 First register 252 Second register 260 Operation control circuit 261 Display 270 Watt hour meter 301 Analog reference generator

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 3/00 H03M 3/00

Claims (17)

[Claims] An AC current and an AC voltage are respectively integrated by an integrator, and a digital value is output through a comparator.
First and second sigma-delta modulation circuits for delaying the output, performing D / A conversion and feeding back to the input side of the integrator to quantize the AC current and the AC voltage, respectively; First and second digital low-pass filters for passing low-pass AC current and AC voltage as input signals, respectively, from the sampled sequence of the quantized AC current and AC voltage after low-pass
/ M (m is an arbitrary positive integer) thinning means,
An electronic watt-hour meter comprising first multiplying means for obtaining a power value by multiplying the AC current and AC voltage from the thinning means, and integrating means for integrating the obtained power value. 2. The first and second digital low-pass filters connect a predetermined number of delay means to an input signal in a cascade and multiply the input signal and the output of each delay means by predetermined coefficients. , A circuit for adding these multiplication results, and a filter for low-passing the quantized AC current and AC voltage as input signals, respectively, 1 / m from the sequence of sampling values of current and AC voltage
2. An electronic watt-hour meter according to claim 1, wherein said thinning means is a means for thinning out at a ratio of (m is an arbitrary positive integer equal to or greater than the number of said delay means of the first and second digital low-pass filters). 3. A first and second integrating means for integrating each of the quantized AC current and AC voltage for one cycle, a second multiplying means for multiplying an output from each of the integrating means, 3. The apparatus according to claim 1, further comprising subtraction means for subtracting the output of said second multiplication means from the output of said multiplication means, and wherein the output from said subtraction means is input to the accumulation means. Electronic watt-hour meter as described. 4. A zero-cross detecting means for detecting one cycle of the quantized AC current and AC voltage by a zero-cross of the AC voltage, and the quantized AC current and AC voltage based on an output of the zero-cross detecting means. The first and second integration means each integrating for one cycle, the second multiplication means multiplying the output from each of the integration means, the output of the second multiplication means from the output of the first multiplication means The electronic watt-hour meter according to claim 1 or 2, further comprising a subtraction means for performing subtraction. 5. Switching means for sequentially taking out an alternating current and an alternating voltage of the input multi-element at a predetermined period, integrating the alternating current and the alternating voltage of each element from the switching means by an integrator, and obtaining a digital value through a comparator. And a D / A converter that delays the output, feeds it back to the input side of the integrator, and sequentially quantizes the AC current and AC voltage of each element from the switching means. Delta modulation circuit conversion means and second sigma-delta modulation circuit, first and second digital low-pass filters for sequentially passing low-pass AC current and AC voltage of each quantized element as input signals, low-pass From the sampled sequence of AC current and AC voltage of each quantized element after
thinning means for thinning out at a rate of m (m is an arbitrary positive integer), first multiplying means for multiplying an AC current and an AC voltage corresponding to a multi-element input from the thinning means, and a sum of the multiplication results An electronic watt-hour meter comprising an adding means for obtaining a power value and an integrating means for integrating the obtained power value. 6. The first and second digital low-pass filters connect a predetermined number of delay means to the input signal in a cascade, and multiply the input signal and the output of each delay means by predetermined coefficients. , A circuit for adding these multiplication results, and a filter for low-passing the quantized AC current and AC voltage as input signals, respectively, 1 / m from the sequence of sampling values of current and AC voltage
6. The electronic watt-hour meter according to claim 5, wherein the thinning means is a means for thinning out at a ratio of (m is an arbitrary positive integer greater than or equal to the number of the delay means of the first and second digital low-pass filters). 7. An offset adjusting means for subtracting an offset power value from a quantized power value, and calculates offset power from the quantized offset current and offset voltage obtained by inputting a reference current and a reference voltage. ,
7. The electronic watt-hour meter according to claim 1, wherein the calculation result is set as the offset power value. 8. An offset adjusting means for subtracting an offset power value from a quantized power value, wherein the offset adjusting means subtracts an offset power value from a quantized power value, and inputs a reference current and a reference voltage at a predetermined period to obtain an offset from the quantized offset current and offset voltage. 7. The electronic watt-hour meter according to claim 6, wherein the power is calculated, and the calculation result is set as the offset power value at each of the predetermined cycles. 9. A desired delay time can be obtained between at least one of the second sigma-delta modulation circuit and the second digital filter and / or between the first sigma-delta modulation circuit and the first digital filter. Providing delay means,
9. The electronic watt-hour meter according to claim 1, wherein the current phase angle or the voltage phase angle is adjusted by the delay operation. 10. The delay means is a shift register capable of shifting a desired number of shifts, and the shift operation adjusts a phase angle.
Electronic watt-hour meter as described. 11. A multi-element input in which an AC current and an AC voltage of an n element are input, and each of the second, third,.
Balance adjustment means are provided for multiplying the quantized power values of the elements by the balance adjustment values of B2, B3,... Bn, respectively, and a reference current is supplied to the input of each of the first, second, third,. , W2, w3,..., And wn, B2 = w
1 / w2, B3 = w1 / w3,... Bn = w1 / wn
The electronic watt-hour meter according to any one of claims 1 to 10, wherein each of the balance adjustment values is set as the balance adjustment value. 12. Each time the integrated value of the quantized power value exceeds a preset rated reference value, resetting and repeating the integration are performed, and the time until the integrated value of the power value exceeds the rated reference value is set. Measuring, and if the time is equal to or longer than a predetermined time, there is provided anti-movement means for preventing the power amount within the measured time from being measured.
An electronic watt-hour meter according to any one of claims 11 to 13. 13. A digital low-pass filter for passing a quantized power value in a low-pass range, and an output having passed through the third digital low-pass filter is inputted to a dive prevention means. Claim 12
Electronic watt-hour meter as described. 14. A light load adjusting means for applying a predetermined light load adjustment value to a quantized power value at least at light load. Electronic watt-hour meter. 15. A third digital low-pass filter that operates at a predetermined operating clock frequency f and passes a quantized power value in a low band, and a first digital low-pass filter that stores an output value passed through the third digital low-pass filter. Registers,
A second register that operates at an operating clock frequency of n times the frequency f and adds and stores the value of the first register n times, and compares the value of the second register with a preset rated reference value And a comparing means for performing an operation clock frequency n times the frequency of f and outputting an output for measuring the amount of electric power every time the rated reference value is exceeded.
An electronic watt-hour meter according to any one of claims 4 to 7. 16. A rating adjusting means for outputting an input electric energy as an electric energy corrected based on a rated reference value, wherein an actually measured reference electric power value obtained by inputting a reference current and a reference voltage is provided. Correct the rating reference value previously set according to the ratio of the calculated reference power value calculated by multiplying the reference current and the reference voltage, and set the corrected rating reference value as the rating reference value. The electronic watt-hour meter according to any one of claims 1 to 15, wherein the electronic watt-hour meter is provided. 17. Switching means for sequentially switching and outputting each input current and input voltage of a first phase, a second phase, and a third phase at a predetermined cycle, and outputting AC current and AC voltage of each phase from the switching means, respectively. First and second sigma-delta modulation circuits to be quantized, first and second digital low-pass filters that respectively pass the quantized AC current and AC voltage of each phase in the low pass, after the low pass Thinning-out means for thinning out the quantized AC current and AC voltage sampling value sequence at a rate of 1 / m, multiplying means for multiplying each phase AC current and AC voltage from the thinning-out means, respectively, Adding means for obtaining the sum of the outputs from the means, a third digital low-pass filter for low-passing the added output, and an output from the third digital low-pass filter. A first and a second multiplying means for multiplying the quantized power values of the second phase and the third phase obtained from the AC current and the AC voltage of the normal object to be measured by balance adjustment values B1 and B2, respectively; A second balance adjustment register is provided, a predetermined analog value is input in the same phase as the first phase current / voltage input, and the output of the third digital low-pass filter at this time is set to w01,
The analog value is input as the current / voltage input of the phase, the output of the third digital low-pass filter at this time is w02, and the analog value is input as the current / voltage input of the first phase. Balance adjustment means for setting the output of the third digital low-pass filter to w03, setting the value of B2 = w01 / w02 in the first balance adjustment register, and setting the value of B3 = w01 / w03 in the second balance adjustment register . A register for integrating the output of the third digital low-pass filter and an F value setting register for setting a value of F = (w01 / reference power) × rated reference value are provided, where reference power = reference voltage. The product calculated by multiplying the reference current, the rated reference value = the calculated value (constant) that determines the number of pulses per power amount) The quantized power amount is integrated by the register, and the integrated value is calculated by the F value. Rating adjusting means for sending an output for measuring the amount of electric power each time the power exceeds the limit and resetting the register. A light load adjustment register for adding the set light load adjustment value to the output value of the third digital low-pass filter is provided, and 1 / n (n ≧ n) of the current analog value input above.
The value of 1) is input as a current input of the first phase, and 1 / m (m ≧ 1) of the voltage analog value input as described above is input as a current input of the second phase. The output of the low-pass filter is defined as w0n, and L = (w01
(/ Nm) -Light load adjustment means for setting the value of -w0n as the light load adjustment value in the light load adjustment register. A shift register capable of shifting a desired number of shifts between the second analog / digital conversion means and the second digital low-pass filter and P1, P2, and P3 registers for designating the number of shifts of the shift register are provided. As an input of the first phase, an analog value having the same effective value as the above-mentioned input analog value and a power factor = 0.5 is input, and the output of the third digital low-pass filter at that time is W0P1, and P1 = K ( w01 × 0.5) −w0P1 (where K is a constant) is set in the P1 shift register, and the second
As the phase input, an analog value having the same effective value as the above input analog value and a power factor = 0.5 is input, and the output of the third digital low-pass filter at that time is w0P2,
The value of P2 = K (w01 × 0.5) -W0P2 is set in the shift register of P1, and the analog value of power factor = 0.5 having the same effective value as the input analog value as the input of the third phase as the input analog value is input. , And the output of the third digital low-pass filter at that time is defined as w0P3, and P1 = K (w01 × 0.
5) Phase adjusting means for setting the value of -w0P3 in the shift register of P1 and sequentially shifting the phase of each phase to the values of P1, P2 and P3 in the shift register in synchronization with the switching means to adjust the phase. An electronic watt-hour meter having at least one of the above adjusting means.