JP2005109599A - Analog / digital conversion apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analog / digital conversion apparatus for converting a converted analog signal into a digital signal with high precision even when a single signal level conversion means converts the level of the analog signal belonging to a range from a small level signal region to a large level signal region. <P>SOLUTION: In the case that a current sensor 10 converts an analog signal from a power system into the level of a small signal range suitable for control arithmetic operations or the level of a large signal range proper to protection arithmetic operations according to its input level and a ΔΣ A/D converter 18 adopting the ΔΣ modulation system converts the converted analog signal into digital data, the ΔΣ A/D converter 18 with a gradation of 20 bits or over is used and the current sensor 10 is shared with an input converter for the protection arithmetic operations and an input converter for the control arithmetic operations. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an analog / digital conversion apparatus, and more particularly to an analog / digital conversion apparatus suitable for converting an analog signal from a power system into a digital signal and using it as an input sensor of an intelligent digital protection control system.

  Conventionally, as this type of device, for example, a digital protection relay (second generation digital relay) is known (Non-Patent Document 1), and this device includes an analog input unit, a digital arithmetic processing unit, a settling unit, and an output. It is comprised with the part. The analog input unit includes an analog filter for preventing aliasing errors, a sample hold circuit, a multiplexer, an A / D converter, and a buffer. An A / D converter having a resolution of 16 bits is used, and a configuration in which various types of filter processing are applied to output data of the A / D converter is employed. Furthermore, the digital protection relay is configured with an input board for digital filter processing using high-speed sampling data and a control calculation board for protection control calculation. The input board is mainly an analog with an electrical angle of 3.75 degrees. The signal is sampled, the signal obtained by the sampling is passed through a digital filter for removing harmonics, and the signal that has passed through the digital filter is transferred as digital data to the control operation board once every 30 degrees. In the control calculation board, calculation for protecting and controlling the power system is executed based on digital data from the input board, and a control signal according to the calculation result is output to a circuit breaker or the like.

  On the other hand, in the digital protection relay, when an analog signal from the power system is taken into the input board, a protection device that performs a protection operation for protecting the power system and a control device that controls the configuration of the power system are fully handled. Since scale current values are different, transformers as input converters are individually connected to the protection device and the control device. The transformer for the protection device converts an analog signal from the power system into a signal range level suitable for protection calculation. For example, when a current of several hundred A is input, a voltage of several volts is output. When a current of several thousand A is input, a voltage of several tens of volts is output.

  On the other hand, a transformer for a control device converts an analog signal from a power system into a signal range level suitable for control calculation. For example, when a current of several tens A is input, a voltage of several volts is output, and when a current of several hundreds of A is input, a voltage of several tens of volts is output. An analog signal whose level is converted by each transformer is sequentially input to a 16-bit A / D converter via a multiplexer, and converted to a digital signal by the A / D converter.

  In addition, when converting a plurality of analog signals with different full-scale current values into digital signals in the protective device, the analog signals from the power system are taken into a plurality of electric quantity input circuits with different full scales, and each electric quantity input In the circuit, an analog signal is sampled and held, and the held signal is converted into digital data by an A / D converter via a multiplexer, and a plurality of protection relays corresponding to each electric quantity input circuit based on the digital data There has been proposed one in which a protection operation for protecting a system is performed by an operation unit (Patent Document 1).

Electric Cooperative Research Volume 50 No.1 JP-A-5-161245 (pages 3 to 4, FIGS. 1 and 2)

  In the prior art, when converting the level of an analog signal having different full-scale current values, a plurality of transformers (input converters) as signal level conversion means for converting the level of the analog signal must be provided. Cannot be shared by one transformer.

  An object of the present invention is to convert a converted analog signal into a highly accurate digital signal even if the level of the analog signal belonging to the large signal region is converted by a single signal level conversion means. .

  In order to solve the above problems, the present invention converts an analog signal from a power system into a small signal range level suitable for control computation or a large signal range level suitable for protection computation according to the input level. Signal level conversion means, and analog / digital conversion means for converting the analog signal converted by the signal level conversion means into a digital signal according to a sampling frequency, wherein the signal level conversion means is a small signal suitable for the control calculation. A range including a range and a large signal range suitable for the protection operation is configured as a full-scale range for the analog signal, and the analog / digital conversion unit has the resolution corresponding to the full-scale range of the signal level conversion unit, One of the small signal range and the large signal range is Greater resolution than the resolution at which the full scale range for the analog signal, for example, which is constituted of an analog-digital converter comprising a resolution of more than 20 bits.

  In configuring the analog-digital conversion device, the signal level conversion means may be configured such that an analog signal from an electric power system is output from the electric power system according to the input level when the analog signal level is in the small signal region. The signal is converted to a signal (voltage) of a level belonging to a small signal range suitable for a control calculation for controlling the configuration, and the input level when the level of the analog signal is in a large signal region higher than the small signal region Accordingly, the power system can be configured to have a function of converting to a signal (voltage) of a level belonging to a large signal range suitable for a protection operation for protecting the power system.

Further, when configuring the analog-digital conversion apparatus, the following elements can be added.
(1) Auxiliary analog / digital for converting the analog signal from the signal source into a digital signal in synchronization with the analog / digital conversion means and using the ground potential of the analog / digital conversion means as a signal source in accordance with the sampling frequency. Conversion means; and arithmetic means for calculating a difference between the digital signal converted by the analog / digital conversion means and the digital signal converted by the auxiliary analog / digital conversion means.
(2) The analog-to-digital conversion means and the auxiliary analog-to-digital conversion means include an integrator that integrates the analog signal as an element that converts the analog signal into the digital signal by a ΔΣ modulation method, A delta modulator for delta modulating the output signal.
(3) The analog / digital conversion means and the auxiliary analog / digital conversion means are formed on the same semiconductor chip.
(4) The arithmetic means includes a gain correction multiplier for multiplying a digital signal obtained by the conversion of the auxiliary analog / digital conversion means, a digital signal multiplied by the gain correction multiplier and the analog / digital conversion. And a noise canceling subtractor for calculating a difference from the digital signal by the conversion of the means.
(5) The calculation means includes an integrator that extracts a direct current component from the calculation result of the noise canceling subtractor, and an offset correction that calculates a difference between the calculation result of the noise canceling subtractor and the output of the integrator. And a gain error correction multiplier for multiplying the calculation result of the offset correction difference by a gain error correction coefficient and outputting the result.
(6) A photoelectric converter that converts an electrical signal output from the gain error correcting multiplier into an optical signal and transmits the optical signal is provided.

  In addition, an analog / digital conversion device that converts an analog signal from the power system into a digital signal, and an operation for protecting / controlling a protection / control target based on a digital signal output from the analog / digital conversion device, When configuring a digital protection control system including a protection / control arithmetic device that outputs a protection / control signal according to the arithmetic operation to the protection / control target, the analog / digital control device may be any one of the analog / digital control devices. -A digital conversion device can be used.

  According to the above-described means, in the process in which the analog signal changes from the small signal region to the large signal region, the analog signal is converted into a small signal range level suitable for control calculation according to the input level (to the small signal range). (Converted to a voltage signal of a level belonging to) or a level of a large signal range suitable for protection operation (a voltage signal of a level belonging to a large signal range), and the converted analog signal (voltage signal) is converted into a digital signal according to the sampling frequency The range including the small signal range and large signal range is the full scale range (all input voltage range) for analog signals, and the resolution of the analog / digital conversion means corresponding to this full scale range is the small signal range or large signal range. When setting one of the ranges to the full scale range for analog signals Since the resolution is larger than the resolution (16 bits), for example, a resolution of 20 bits or more, an analog signal converted by a single signal level conversion means can be converted into a digital signal with high accuracy, and signal level conversion can be performed. The means can be shared, contributing to simplification of hardware configuration and cost reduction.

  According to the present invention, an analog signal converted by a single signal level conversion means can be converted into a digital signal with high accuracy, and the signal level conversion means can be shared.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram when an analog / digital conversion apparatus showing an embodiment of the present invention is used as an input sensor of a digital protection control system.

  In FIG. 1, an analog / digital conversion device constituting an input sensor of a digital protection control system includes a current sensor 10, an integration circuit 12, a differential amplifier 14, and a folding error prevention low-pass filter 16 as signal level conversion means. As an analog / digital conversion means, a ΔΣ A / D converter 18, a timing control circuit 20, clock oscillation circuits 22 and 24, a microcomputer (CPU) 26 for executing various operations, and serial / parallel conversion for converting serial data into parallel data The circuit (S / P circuit) 28, a dual port memory 30 having bidirectional ports, a signal bus 32, and a work memory 34 of the microcomputer 26 are configured, and the signal bus 32 communicates with the outside. Communication circuit 36 is connected to the communication circuit 36. An electrical / optical converter (E / O converter) 38 that converts an electrical signal of the communication circuit 36 into an optical signal 101d is connected. The integrator 12 to the electrical / optical converter 38 are mounted on a single printed circuit board (semiconductor chip).

  The ΔΣ A / D converter 18 includes two sets of ΔΣ modulation A / D conversion circuits 18a and 18b, two sets of band limiting digital filters 18c and 18d, and output signals of the digital filters 18c and 18d as one output signal. An output interface circuit (IF circuit) 18e that combines and outputs to the serial / parallel conversion circuit 28 is provided. The ΔΣ modulation A / D conversion circuit 18a is connected to the low-pass filter 16 as a one-channel A / D conversion circuit to capture an analog signal from the power system, and the ΔΣ modulation A / D conversion circuit 18b is a two-channel A / D conversion circuit. As an A / D conversion circuit, it is connected to a ground potential at a location close to the ΔΣ A / D converter 18. That is, the ΔΣ modulation A / D conversion circuit 18b is provided to cancel the influence of clock noise. Each ΔΣ modulation A / D conversion circuit 18a, 18b is configured to perform the conversion operation in an independent state and at a synchronized timing.

  The timing control circuit 20 outputs a start signal to the microcomputer 26 in response to the clock from the clock oscillation circuit 22, and sends a conversion start command signal 101a to the ΔΣ modulation A / D conversion circuits 18a and 18b. The serial / parallel operation clock signal 101b is output to the serial / parallel conversion circuit 28.

  The current sensor 10 is connected to the power system in a state of being directly attached to the power equipment (breaker), and for example, a Rogowski coil is used as the current sensor 10. The current sensor 10 captures current as an analog signal from the power system, and when the level of the analog signal is in the small signal region, the current sensor 10 has a small signal range suitable for control computation for controlling the configuration of the power system according to the input level. Protection operation to convert power level (voltage signal of level belonging to small signal range) and protect power system according to its input level when analog signal level is in large signal area higher than small signal area Is converted to a level of a large signal range suitable for the voltage (a voltage signal of a level belonging to the large signal range), and the converted analog signal is output to the integrating circuit 12. When the Rogowski coil is applied to the current sensor 10, the integrating circuit 12 is provided to attenuate the high frequency region because the current is amplified to the high frequency region due to its frequency characteristics. In addition, when taking in a voltage as an analog signal from an electric power system instead of the current sensor 10, a voltage sensor is used instead of the current sensor. The voltage sensor is configured to divide the voltage from the power system by a plurality of capacitors connected in parallel and output the divided voltage to the differential amplifier 14.

  The differential amplifier 14 is provided for the purpose of amplifying the signal because the output voltage of the current sensor 10 is very small, for example, about ± 10 V, and reduces common mode noise superimposed on a minute signal. It is provided for.

  1, R 2, R 3, R 4, R 5, R 6, R 7 and operational amplifiers (op-amps) OP 1, OP 3, OP 2, OP 3, so that the signal from the integrating circuit 12 is input to the resistors RD 1, RD 2. It has become.

The output voltage of the differential amplifier 14 having the above configuration can be expressed by the following equation (1), and the differential voltage of the input voltages V _{+ in} and V _−in can be amplified.

Vout1 = (V _{+ in−} V− _in ) × (1 + 2 · R2 / R1) × (R6 / R
4) ... (1)
As apparent from the equation (1), since the differential amplifier 14 can handle only the differential voltage of the input voltage, it can remove common mode noise generated between the input terminal and the analog ground. .

  As shown in FIG. 2, the low-pass filter 16 includes a resistor R8, a capacitor C1, and an operational amplifier OP4. The low-pass filter 16 is configured as a first-order lag element filter, and its transfer function can be expressed by the following equation (2). .

T (jw) = 1 / (1 + jwC1 · R8) (2)
The low-pass filter 16 having the above configuration functions as a signal band limiter for preventing a folding error due to sampling. That is, an analog signal having a sampling frequency of 1/2 times or more in the ΔΣ A / D converter 18 is attenuated by the attenuation characteristic of the low-pass filter 16. Normally, when the sampling frequency of the ΔΣ A / D converter 18 is low, the aliasing error prevention filter needs to have a low cutoff frequency, so that it is necessary to increase the delay order and to increase the resistance / capacitor. However, in the present embodiment, since the sampling frequency in the ΔΣ A / D converter 18 is significantly higher than that in the prior art, for example, set to 1 MHz, the attenuation characteristic of the low-pass filter 16 can be made gentle. Downsizing can be achieved.

  The ΔΣ A / D converter 18 operates by receiving the basic clock CLK output from the clock oscillation circuit as shown in FIG. 3A, and divides the basic clock by half as shown in FIG. 3B. Data is output in synchronization with the clock BCLK that has been rotated. The 1-channel ΔΣ modulation A / D conversion circuit 18a then serially outputs data from the most significant bit MSB to the least significant bit LSB in order as shown in (c). Subsequently, as shown in (d), the 2-channel ΔΣ modulation A / D conversion circuit 18b serially outputs data from the most significant bit MSB to the least significant bit LSB in order. At this time, from the output port 101c of the output interface circuit 18e, 1-channel data and 2-channel data are switched and output in a time division manner. When serial data is sequentially output from the port 101c, each serial data is converted into parallel data (parallel data) in the serial / parallel conversion circuit 28, and the converted data is stored in the dual port memory 30, respectively.

  Here, the ΔΣ modulation A / D conversion circuits 18a and 18b and the digital filters 18c and 18d have the same characteristics, and the operation timings are also operated in parallel at the same time. The ΔΣ modulation A / D conversion circuits 18a and 18b include, for example, an integrator that integrates an analog signal and a Δ modulator that Δ-modulates the output signal of the integrator, and each ΔΣ modulation A The / D conversion circuits 18a and 18b can shift the random noise (N1) having no periodicity to the high-frequency region with respect to the signal (S), as shown in FIG. It is possible to compress noise in the signal frequency band. FIG. 4B shows a power spectrum diagram after the output of the ΔΣ modulation A / D conversion circuit 18a is passed through the digital filter 18c. As shown in FIG. 4B, due to the attenuation characteristic of the digital filter (low-pass filter) 18c, random noise (N1) that has shifted to the high-frequency region due to the integration characteristic of the ΔΣ modulation A / D conversion circuit 18a and the partial high-frequency region. The generated periodic noise (noise generated by a clock or the like) can be largely removed. However, noise that cannot be removed by the digital filter 18c and has periodicity (N2) is generated in the signal passband, and therefore remains as noise.

  Here, the random noise (N1) having no periodicity refers to noise associated with quantization error or thermal noise during A / D conversion, and noise having a relatively clear periodicity (N2). ) Refers to noise in which an A / D conversion error occurs due to the influence of induced noise of a clock signal (noise on the order of several MHz), induced noise from a switching power supply (noise of the order of 100 kHz to 200 kHz), and the like.

  In order to remove periodic noise (N2), in this embodiment, as shown in FIG. 5, a noise cancellation processing unit 26a, an offset error correction processing unit 26b, and a gain error correction processing unit are connected to the microcomputer 26. The function as 26c is added.

  The microcomputer 26 has a built-in program memory as calculation means for calculating the difference between the digital signal output from the digital filter 18c and the digital signal output from the digital filter 18d, and sequentially takes in the data stored in the dual port memory 30. Various operations are executed based on the fetched data. In this case, the microcomputer 26 operates using the clock oscillation circuit 24 as a clock source, and starts a predetermined program in response to the start signal output from the timing control circuit 20. In general, in the microcomputer 26, processing is started at regular intervals by applying an interrupt signal.

  The noise cancellation processing unit 26a includes a gain correction multiplier 5a and a noise canceling difference unit 5b, and a 1-channel digital signal output from the digital filter 18c is input to the difference unit 5b. An analog ground signal (a signal input using the ground potential of the ΔΣ modulation A / D conversion circuit 18d as a signal source), which is a two-channel digital signal output from the digital filter 18d and is periodic noise, is supplied to the multiplier 5a. 501b is input. The analog ground signal 501b is multiplied by the gain (K) by the multiplier 5a, and the gain-multiplied signal is input to the differentiator 5b. The difference unit 5b calculates a difference between the digital signal 501a obtained by A / D converting an analog signal from the power system and the analog ground signal output from the multiplier 5a, and calculates the calculation result as an offset error correction processing unit 26b. To output. When the processing by the noise cancellation processing unit 26a is performed, noise (N2) having a periodicity, which is a noise component superimposed on the digital data 501a, can be canceled. In other words, since the 1-channel and 2-channel ΔΣ modulation A / D conversion circuits 18a and 18b operate simultaneously and in parallel, the induced noise of the clock signal or the induced noise of the switching power supply is different from the digital data 501a and the analog ground signal 501b. Since the operation is the same, the noise (N2) can be canceled by subtracting the output signal of the multiplier 5a from the digital data 501a.

  Further, by mounting the ΔΣ A / D converter 18 in the same semiconductor chip, the 1-channel and 2-channel ΔΣ modulation A / D conversion circuits 18 a and 18 b are also considered to be affected by the same noise at the same time. be able to. In addition, the influence of noise is a parameter such as the distance from the noise source, the stray capacitance, and the voltage value of the noise source.

  The offset error correction processing unit 26b includes an integrator 5c that extracts a DC component from the output signal of the difference unit 5b, and an offset correction difference unit 5d that calculates a difference between the output signal of the difference unit 5b and the integrator 5c. It is configured. By subtracting the output signal of the difference unit 5b by the output signal of the integrator 5c, the offset of the differential amplifier 14 can be corrected.

  The gain error correction processing unit 26c includes a gain error correction multiplier 5e that multiplies the output signal of the difference unit 5d by a gain error correction coefficient Kg and outputs the result. The gain error correcting multiplier 5e can output the digital signal of the signal component with the gain error corrected by multiplying the calculation result of the difference unit 5d by the gain error correction coefficient Kg. The digital signal is output to the communication circuit 36 via the signal bus 32 as a digital signal indicating a difference between the digital signal output from the digital filter 18c and the digital signal output from the digital filter 18d.

  Here, the signal-to-noise power spectrum is shown in FIG. FIG. 6A shows a power spectrum of one channel data obtained by taking in a system voltage or system current and A / D converting the acquired voltage or current signal, and FIG. 6B shows an A / D conversion of an analog ground signal. (C) shows the corrected power spectrum obtained by the processing of the noise cancellation processing unit 26a, the offset error processing unit 26b, and the gain error correction processing unit 26c.

  In (a) and (b), there is (N2) having periodicity in the signal passband that cannot be removed by the digital filters 18c and 18d, whereas as shown in (c), the periodicity is changed. It can be seen that the noise (N2) is removed from the signal pass band, and only the signal (S) exists in the signal pass band.

  As described above, the microcomputer 26 can perform offset correction and gain correction as well as noise cancellation by performing the process of calculating the difference between the 1-channel data and the 2-channel data. Even with a minute voltage, it is possible to obtain highly accurate digital data (digital signal) that is not affected by noise.

  Furthermore, in this embodiment, since a minute voltage can be managed, a resolution higher than the conventional resolution (16 bits), for example, 20 bits or 24 bits can be used as the A / D converter. The range can be greatly increased. In other words, as a current sensor, a range including a small signal range suitable for control computation and a large signal range suitable for protection computation, for example, a range that is the sum of a small signal range and a large signal range is configured as a full scale range for analog signals As a resolution corresponding to the full scale range of the current sensor 10, a resolution larger than the resolution when one of the small signal range and the large signal range is set to the full scale range for the analog signal, for example, 20 bits or more. A high-precision digital data can be obtained by using a ΔΣ A / D converter 18 having a resolution of 1 mm, and a single current sensor 10 is shared as an input converter for control calculation and an input converter for protection calculation Can contribute to hardware simplification and cost reduction Can do. Further, the ΔΣ A / D converter 18 is not limited to 20 bits, and if it is equivalent to 24 bits, digital data with higher accuracy can be obtained.

  Next, another embodiment of the present invention will be described with reference to FIG. In the present embodiment, a ΔΣ A / D converter 40 having the same function as that of the ΔΣ A / D converter 18 is provided, and a serial / parallel conversion circuit 42 having the same function as that of the serial / parallel conversion circuit 28 is provided. The circuit 20 outputs an A / D conversion signal 701 a to the ΔΣ A / D converter 40, and also outputs an S / P conversion control signal 701 b to the serial / parallel conversion circuit 42, and further in the ΔΣ A / D converter 40. The input terminal of the ΔΣ modulation A / D conversion circuit is grounded, and the other configuration is the same as that of FIG. In this case, as shown in FIG. 8, the noise cancellation processing unit 26a of the microcomputer 26 is provided with multipliers 8a, 8b, and 8c and a differencer 8d. However, the offset error correction processing unit 26b and the gain error correction processing unit 26c are the same as those in FIG. The multiplier 8a multiplies the analog ground signal 501b output from the digital filter 18d by a gain K1, and the multipliers 8b and 8c respectively output analog ground signals 801a and 801b output from the digital filter built in the ΔΣ A / D converter 40, respectively. The gains K2 and K3 are multiplied and output. The difference unit 8d subtracts the output signals of the multipliers 8a, 8b, and 8c from the digital data 501a output from the digital filter 18c and outputs the result to the offset error correction processing unit 26b.

  In the present embodiment, by providing three parts with a ground potential as a signal source and sensing from signals from these three points, the influence of noise can be accurately removed, and a highly accurate signal component (Digital signal) can be extracted.

  Next, an application example when the analog-digital conversion apparatus according to the present invention is applied to a digital protection control system will be described with reference to FIG. The digital protection control system according to the present embodiment is configured as an element of an intelligent substation system. The A phase circuit breaker 50, the B phase circuit breaker 52, and the C phase circuit breaker 54, which are substation devices, include analog signals. Current sensor units 56, 58 and 60 and voltage sensors 62, 64 and 66 as digital conversion devices are provided. That is, the current sensor units 56, 58, and 58 are configured by an analog / digital converter when the current sensor 10 is used as an input converter, and the voltage sensors 62, 64, and 66 are voltage sensors instead of the current sensor 10. It is composed of an analog / digital conversion device when using. The current sensors 56, 58, 60 output noise-cancelled A / D conversion data 901a to 901f as optical signals, and the voltage sensor units 62, 64, 66 output noise-cancelled A / D conversion data 901d. ˜901f are output as optical signals. The optical signals are aggregated by the merging unit 68 and then output as serial data to the protection unit 70 or the control unit 72 via the optical cables 902a and 902b.

  The protection unit 70 receives data from the optical cable 902a, performs a detection calculation for detecting an accident and a protection calculation for removing the accident according to a preset program, and a control signal based on the calculation result is interrupted by the circuit breaker 50. , 52 and 54. The control unit 72 receives data from the optical cable 902b, performs control computation such as monitoring processing represented by tap control of substation equipment and measurement in accordance with a preset program, and controls the control signal according to the computation result. Output to the target.

  As described above, in this embodiment, by providing the circuit breakers 50, 52, and 54 as the substation equipment with an intelligent function, information can be shared, and data can be unified regardless of the device.

1 is a block configuration diagram of an analog / digital conversion apparatus showing an embodiment of the present invention. It is a circuit block diagram of a differential amplifier and a low-pass filter. It is a wave form diagram for demonstrating operation | movement of an A / D converter. It is a power spectrum figure which shows the signal to noise relationship of an A / D converter. It is a block block diagram of a noise cancellation process part, an offset error correction process part, and a gain error correction process part. It is a signal-to-noise power spectrum diagram for explaining a noise canceling method by processing of a microcomputer. It is a block block diagram which shows other embodiment of this invention. It is a block diagram for demonstrating the structure of the noise cancellation process part of the microcomputer in other embodiment of this invention. It is a block block diagram of the digital protection control system which shows the application example of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Current sensor 12 Integration circuit 14 Differential amplifier 16 Low pass filter 18 ΔΣ A / D converter 18a, 18b ΔΣ modulation A / D conversion circuit 18c, 18d Digital filter 18e Output interface circuit 20 Timing control circuit 22, 24 Clock oscillation circuit 26 Micro Computer 28, 42 Serial / parallel conversion circuit 30 Dual port memory 34 Work memory 36 Communication circuit 38 Electric / optical converter 40 ΔΣ A / D converter 50, 52, 54 Circuit breaker 56, 58, 60 Current sensor unit 62, 64, 66 Voltage sensor unit 68 Merging unit 70 Protection unit 72 Control unit

Claims (9)

When the analog signal from the power system is converted into a level of a small signal range suitable for control calculation for controlling the configuration of the power system according to the input level when the level of the analog signal is in the small signal region, When the level of the analog signal is in a large signal region higher than the small signal region, the signal level is converted to a level of a large signal range suitable for protection operation for protecting the power system according to the input level Conversion means, and analog / digital conversion means for converting the analog signal converted by the signal level conversion means into a digital signal according to a sampling frequency, the signal level conversion means having a small signal range suitable for the control calculation, A range including a large signal range suitable for the protection operation is set to a full scale level for the analog signal. The analog-to-digital conversion means has a resolution corresponding to the full-scale range of the signal level conversion means, and selects one of the small signal range and the large signal range as a full-scale range for the analog signal. An analog / digital converter having a resolution larger than that of Signal level conversion means for converting an analog signal from the power system into a small signal range level suitable for control calculation or a large signal range level suitable for protection calculation according to the input level, and the signal level conversion means Analog-to-digital conversion means for converting the converted analog signal into a digital signal according to a sampling frequency, and the signal level conversion means has a small signal range suitable for the control operation and a large signal range suitable for the protection operation. The analog / digital conversion means has a resolution of 20 bits or more as a resolution corresponding to the full scale range of the signal level conversion means. Conversion device. 3. The analog / digital conversion apparatus according to claim 1, wherein a ground potential of the analog / digital conversion means is used as a signal source, an analog signal from the signal source is synchronized with the analog / digital conversion means, and Auxiliary analog-to-digital conversion means for converting to a digital signal according to a sampling frequency, and arithmetic means for calculating a difference between the digital signal converted by the analog-digital conversion means and the digital signal converted by the auxiliary analog-digital conversion means An analog-to-digital converter characterized by comprising. 4. The analog / digital conversion device according to claim 3, wherein the analog / digital conversion means and the auxiliary analog / digital conversion means convert the analog signal into an element that converts the analog signal into the digital signal by a ΔΣ modulation method. An analog / digital conversion apparatus comprising: an integrator for integrating; and a delta modulator for delta modulating an output signal of the integrator. 5. The analog / digital conversion apparatus according to claim 4, wherein the analog / digital conversion means and the auxiliary analog / digital conversion means are formed on the same semiconductor chip. 6. The analog / digital conversion apparatus according to claim 3, wherein the arithmetic means includes a gain correction multiplier that multiplies a digital signal obtained by the conversion of the auxiliary analog / digital conversion means. And a noise canceling subtractor for calculating a difference between the digital signal multiplied by the gain correcting multiplier and the digital signal converted by the analog / digital converting means. Conversion device. 7. The analog / digital conversion device according to claim 6, wherein the calculation means includes an integrator for extracting a direct current component from a calculation result of the noise canceling subtractor, a calculation result of the noise canceling subtractor, and the integrator. And a gain error correction multiplier for multiplying the calculation result of the offset correction difference unit by a gain error correction coefficient and outputting the result. Analog / digital converter. 8. The analog / digital conversion apparatus according to claim 7, further comprising a photoelectric converter that converts an electrical signal output from the gain error correction multiplier into an optical signal and transmits the optical signal. apparatus. An analog / digital conversion device that converts an analog signal from the power system into a digital signal, and an operation for protecting / controlling the object to be protected / controlled based on the digital signal output from the analog / digital conversion device. 9. A digital protection control system comprising a protection / control arithmetic device that outputs a protection / control signal according to the protection / control target to the protection / control target, wherein the analog / digital control device is any one of claims 1 to 8. A digital protection control system comprising the analog-digital conversion device described in 1.

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