JPH09205369A - Secondary delta sigma modulator - Google Patents
Secondary delta sigma modulatorInfo
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- JPH09205369A JPH09205369A JP8033068A JP3306896A JPH09205369A JP H09205369 A JPH09205369 A JP H09205369A JP 8033068 A JP8033068 A JP 8033068A JP 3306896 A JP3306896 A JP 3306896A JP H09205369 A JPH09205369 A JP H09205369A
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、アナログ方式のデ
ルタシグマ（ΔΣ）変調器に関し、特に２次デルタシグ
マ変調器の回路構成に関する。The present invention relates to an analog delta-sigma (Δ デ ル タ) modulator, and more particularly to a circuit configuration of a second-order delta-sigma modulator.
【０００２】[0002]
【従来の技術】図５は、従来のアナログ方式の２次デル
タシグマ（ΔΣ）変調器の構成を示すブロック図であ
る。また、図６は、従来の２次ΔΣ変調器の原理的な構
成を示したシグナルフロー図、及び各部の信号を示した
ものである。2. Description of the Related Art FIG. 5 is a block diagram showing the configuration of a conventional analog second-order delta-sigma (ΔΣ) modulator. FIG. 6 shows a signal flow diagram illustrating a basic configuration of a conventional second-order ΔΣ modulator and signals of respective units.
【０００３】図６（Ａ）に示す積分回路ＩＮＴ−４０
１、４０２は、それぞれ図５のオペアンプ（ＯＰ−３０
１、ＯＰ−３０２）とスイッチ（Ｓ−３０１〜Ｓ−３１
２）とキャパシタ（Ｃ−３０１〜Ｃ−３０４）で構成さ
れている。The integrating circuit INT-40 shown in FIG. 6 (A).
Reference numerals 1 and 402 denote the operational amplifier (OP-30) shown in FIG.
1, OP-302) and switches (S-301 to S-31)
2) and capacitors (C-301 to C-304).
【０００４】従来の２次ΔΣ変調器の原理を示す図であ
る図６（Ａ）を参照して、この２次ΔΣ変調器の動作を
説明する。まず、入力信号（図６（Ｂ）参照）が端子ｉ
ｎに与えられると、差分回路４０３において、入力信号
とΔΣ符号（図６（Ｅ）参照）との差分がとられ、この
差信号が積分回路ＩＮＴ−４０１に入力される。The operation of this second-order ΔΣ modulator will be described with reference to FIG. 6A, which is a diagram showing the principle of a conventional second-order ΔΣ modulator. First, an input signal (see FIG. 6B) is applied to a terminal i.
n, the difference between the input signal and the ΔΣ code (see FIG. 6E) is obtained in the difference circuit 403, and this difference signal is input to the integration circuit INT-401.
【０００５】この積分回路ＩＮＴ−４０１の出力は、図
６（Ｃ）に示すようなものとなり、この積分回路ＩＮＴ
−４０１の出力は、差分回路４０４において、ΔΣ符号
（図６（Ｅ））との差分がとられ、この差信号が積分回
路ＩＮＴ−４０２に入力される。図６（Ｄ）は、この積
分回路ＩＮＴ−４０２の出力波形である。The output of the integrating circuit INT-401 is as shown in FIG.
The difference from the output of −401 is obtained by a difference circuit 404 from the ΔΣ code (FIG. 6E), and this difference signal is input to the integration circuit INT-402. FIG. 6D shows the output waveform of this integration circuit INT-402.
【０００６】２値量子化回路４０５では、前段の積分回
路ＩＮＴ−４０２の出力の正負を判定して、図６（Ｅ）
に示すようなデルタシグマ（ΔΣ）符号を出力する。こ
のΔΣ符号は次のサンプル点における近似信号として用
いるために遅延回路４０６に入力される。The binary quantization circuit 405 determines whether the output of the integration circuit INT-402 at the preceding stage is positive or negative, and obtains the result shown in FIG.
And outputs a delta sigma (ΔΣ) code as shown in FIG. This ΔΣ code is input to the delay circuit 406 for use as an approximate signal at the next sample point.
【０００７】いま、入力サンプル値系列（端子ｉｎに入
力されるサンプル値系列）のｚ変換をＸ（ｚ）、出力サ
ンプル値系列（端子ｏｕｔに入力されるサンプル値系
列）のｚ変換をＹ（ｚ）、２値量子化回路４０５による
量子化誤差のｚ変換をＱ（ｚ）、積分回路の伝達関数を
１／（１−ｚ-1）、更に遅延回路４０６の伝達関数をｚ
-1とすると、図６について、［｛Ｘ（ｚ）−ｚ-1Ｙ
（ｚ）｝（１−ｚ-1）-1−ｚ-1Ｙ（ｚ）］（１−ｚ-1）
-1＝Ｙ（ｚ）−Ｑ（ｚ）、の回路方程式から、次式
（１）が成り立つ。Now, the z-transform of the input sample value sequence (the sample value sequence input to the terminal in) is X (z), and the z-transform of the output sample value sequence (the sample value sequence input to the terminal out) is Y ( z) The z-transform of the quantization error by the binary quantization circuit 405 is Q (z), the transfer function of the integration circuit is 1 / (1−z −1 ), and the transfer function of the delay circuit 406 is z
Assuming −1 , as shown in FIG. 6, [｛X (z) −z −1 Y
(Z)｝ (1-z −1 ) −1 −z −1 Y (z)] (1-z −1 )
From the circuit equation of −1 = Y (z) −Q (z), the following equation (1) holds.
【０００８】 Ｙ(ｚ)＝Ｘ(ｚ)＋(１−ｚ-1)2Ｑ(ｚ) …(1)Y (z) = X (z) + (1−z −1 ) 2 Q (z) (1)
【０００９】ここで、（１−ｚ-1）の振幅周波数特性
（ｚ＝ｅｘｐ(jωT)）は、｜１−ｅｘｐ(-jωT)｜であ
るので、低域周波数成分を圧縮し、高域周波数成分を待
ち上げる特性を持つことが分かる。Here, since the amplitude frequency characteristic (z = exp (jωT)) of (1-z -1 ) is | 1-exp (-jωT) |, the low frequency components are compressed and the high frequency components are compressed. It can be seen that there is a characteristic of waiting for a frequency component.
【００１０】[0010]
【発明が解決しようとする課題】この従来の２次アナロ
グデルタシグマ変調器は、アナログ積分器が必要である
ため、オペアンプ等の高ゲインの増幅器が２つ必要とさ
れており、このため本変調器をＬＳＩ等で実現する場
合、そのマスク面積の内にオペアンプの占める割合が大
きくなり、従って多数の２次ΔΣ変調器を用いる場合、
全体的な面積も大きくなるという問題点があった。The conventional second-order analog delta-sigma modulator requires an analog integrator, and therefore requires two high-gain amplifiers such as operational amplifiers. When the modulator is realized by an LSI or the like, the ratio of the operational amplifier in the mask area becomes large. Therefore, when a large number of second-order ΔΣ modulators are used,
There has been a problem that the overall area is large.
【００１１】従って、本発明は、上記問題点を解消し、
２回の積分動作を１個の積分器を時分割多重使用するこ
とにより、少ないマスク面積で２次デルタシグマ（Δ
Σ）変調を実現することを可能とした２次デルタシグマ
（ΔΣ）変調器を提供することを目的とする。Therefore, the present invention solves the above problems,
By using time-division multiplexing of one integrator for two integration operations, a second-order delta sigma (Δ
Ii) An object of the present invention is to provide a second-order delta-sigma (ΔΣ) modulator capable of realizing modulation.
【００１２】[0012]
【課題を解決するための手段】前記目的は、本発明によ
る２次デルタシグマ変調器によれば、１回目の積分結果
を保持するためのスイッチ付きキャパシタと、２回目の
積分結果を保持するためのスイッチ付きキャパシタと、
を演算増幅器の帰還路に並設し、入力端子に入力された
入力信号とデルタシグマ（ΔΣ）符号出力との差分の第
１の積分操作と、該積分結果とこのデルタシグマ（Δ
Σ）符号出力との差分の第２の積分操作と、を一つの演
算増幅器で時分割多重で行い、前記第２の積分操作の結
果を２値量子化してデルタシグマ（ΔΣ）符号を出力す
る構成により達成される。According to the second-order delta-sigma modulator of the present invention, the above-mentioned object is to hold a capacitor with a switch for holding the first integration result and a second integration result. With a switched capacitor,
Are installed in parallel in the feedback path of the operational amplifier, and the first integration operation of the difference between the input signal input to the input terminal and the delta sigma (ΔΣ) code output, the integration result and this delta sigma (ΔΣ)
The second integration operation of the difference from the Σ) code output is time-division multiplexed with one operational amplifier, and the result of the second integration operation is binary-quantized to output a delta sigma (ΔΣ) code. Achieved by configuration.
【００１３】本発明の２次デルタシグマ変調器は、好ま
しくは、２つのスイッチ付きキャパシタ（「帰還キャパ
シタ」という）による負帰還が施されたオペアンプから
なる積分回路と、前記積分回路の出力を受ける２値量子
化回路と、入力端子と前記積分回路を接続し、アナログ
入力振幅、及び前記積分回路の振幅に比例した電荷を、
前記積分回路の帰還キャパシタに移す第１のスイッチ付
きキャパシタ回路と、前記積分回路に接続され、基準電
圧に比例した基準電荷を前記積分回路の帰還キャパシタ
に移す第２のスイッチ付きキャパシタ回路と、前記２値
量子化回路の出力に応じて前記基準電荷の前記積分回路
の帰還キャパシタへの転送を制御する手段と、を備えた
ことを特徴とする。[0013] The second-order delta-sigma modulator of the present invention preferably receives an output of the integration circuit including an operational amplifier to which negative feedback is performed by two capacitors with a switch (referred to as a "feedback capacitor"). A binary quantization circuit, an input terminal and the integration circuit are connected, and an analog input amplitude, and a charge proportional to the amplitude of the integration circuit,
A first capacitor circuit with a switch for transferring to a feedback capacitor of the integration circuit; a second capacitor circuit with a switch connected to the integration circuit for transferring a reference charge proportional to a reference voltage to a feedback capacitor of the integration circuit; Means for controlling transfer of the reference charge to the feedback capacitor of the integration circuit in accordance with the output of the binary quantization circuit.
【００１４】[0014]
【発明の実施の形態】本発明の実施の形態について図面
を参照して以下に詳細に説明する。図１は、本発明の一
実施形態の構成を示す図である。また、図２に、各スイ
ッチのコントロールタイミングを示す。図１に示したス
イッチｓ−１０１〜ｓ−１１０はコントロール信号がハ
イレベルでオン、ローレベルでオフとなる。なお、図２
において、［Ｓ」はスイッチＳ−１０１、「１」はスイ
ッチＳ−１０２、「２」はスイッチＳ−１０７、Ｓ−１
０８、「φ」はスイッチＳ−１０３、Ｓ−１０５、「φ
￣」はスイッチＳ−１０４、Ｓ−１０６の制御信号のタ
イミング波形を示している。また、図３に、回路シミュ
レータＳＰＩＣＥによる本実施形態のΔΣ変調器のシミ
ュレーション結果を示す。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a configuration of one embodiment of the present invention. FIG. 2 shows the control timing of each switch. The switches s-101 to s-110 shown in FIG. 1 are turned on when the control signal is at a high level and turned off when the control signal is at a low level. Note that FIG.
, [S] is switch S-101, “1” is switch S-102, “2” is switch S-107, S-1
08, “φ” indicates switches S-103, S-105, “φ”
“￣” indicates a timing waveform of a control signal of the switches S-104 and S-106. FIG. 3 shows a simulation result of the ΔΣ modulator of this embodiment by a circuit simulator SPICE.
【００１５】２次デルタシグマの動作を行うためには、
信号を２回積分する必要があり、時分割多重で積分する
ためには、前回の積分結果を保持しておくレジスタが必
要とされる。本発明の実施形態では、演算増幅器ＯＰ−
１０１の帰還路に並列に挿入されたキャパシタＣ−１
２、Ｃ−１３がこの働きを行う。In order to perform the operation of the second order delta sigma,
It is necessary to integrate the signal twice, and in order to integrate by time division multiplexing, a register for holding the previous integration result is required. In the embodiment of the present invention, the operational amplifier OP-
Capacitor C-1 inserted in parallel in the feedback path 101
2, C-13 performs this function.
【００１６】すなわち、本実施形態は、出力と反転入力
端の間に並列に挿入された２つのスイッチ付きキャパシ
タ（スイッチｓ−１０９、ｓ−１１０、キャパシタＣ−
１２）、及び（ｓ−１０７、ｓ−１０８、Ｃ−１３）に
よる負帰還が施されたオペアンプＯＰ−１０１が積分回
路を構成し、この積分回路の出力を入力する比較器（Ｃ
ＭＰ）からなる２値量子化回路１０２と、入力端子ｉｎ
と積分回路との間に挿入され、アナログ入力振幅、及び
積分回路の電圧振幅に比例した電荷を積分回路の帰還キ
ャパシタ（Ｃ−１１、Ｃ−１３）に転送する第１のスイ
ッチ付きキャパシタ回路（キャパシタＣ−１１、スイッ
チｓ−１０１、ｓ−１０３、ｓ−１０６）と、積分回路
に接続され、基準電圧（ＶＲ）に比例した基準電荷を積
分回路の帰還キャパシタに移す第２のスイッチ付きキャ
パシタ回路（キャパシタＣ−１１、スイッチｓ−１０
４、ｓ−１０６）と、を備え、さらに２値量子化回路１
０２の出力に応じて基準電荷の積分回路の帰還キャパシ
タ（Ｃ−１１、Ｃ−１３）への転送を制御する手段とし
て、遅延回路１０３の出力（Ｑ、Ｑ￣）に基づきスイッ
チｓ−１１１、ｓ−１１２のオン・オフを制御する。That is, in the present embodiment, two capacitors with switches (switches s-109, s-110, capacitor C-) inserted in parallel between the output and the inverting input terminal.
12) and the operational amplifier OP-101 to which the negative feedback by (s-107, s-108, C-13) has been applied constitutes an integrating circuit, and a comparator (C) to which the output of the integrating circuit is input.
MP) and an input terminal in
And a capacitor circuit with a first switch, which is inserted between the analog input amplitude and the voltage amplitude of the integrating circuit and transfers charges proportional to the voltage amplitude of the integrating circuit to the feedback capacitors (C-11, C-13) of the integrating circuit. Capacitor C-11, switches s-101, s-103, s-106) and a second switch-equipped capacitor that is connected to the integrating circuit and transfers a reference charge proportional to the reference voltage (VR) to the feedback capacitor of the integrating circuit. Circuit (capacitor C-11, switch s-10
4, s-106), and the binary quantization circuit 1
As a means for controlling the transfer of the reference charge to the feedback capacitors (C-11, C-13) of the integrating circuit in response to the output of the switch 02, the switches s-111, On / off of s-112 is controlled.
【００１７】図４は、本発明の実施の形態の原理的な構
成を示したシグナルフロー図である。FIG. 4 is a signal flow diagram showing the basic configuration of the embodiment of the present invention.
【００１８】図４を参照して、差分回路２０３とノード
（ｎｏｄｅ）−２０１との間に、並列接続されたスイッ
チｓ−２１１、ｓ−２１２、レジスタ（電荷を蓄積記憶
するキャパシタをレジスタＤ、Ｄ′として示す）２０
１、２０２は、差分回路２０３と共に、図１の帰還路に
スイッチ付きキャパシタを備えたオペアンプＯＰ１０１
による積分回路の構成を示している。また、２０５は２
値量子化回路、２０６は遅延回路を示している。レジス
タ２０１の入力端は切替スイッチｓ−２１０の端子に
接続され、切替スイッチｓ−２１０の端子には入力端
子ｉｎが最初接続されている。以下、図４を参照して、
本実施形態を説明する。Referring to FIG. 4, switches s- 211 and s- 212 connected in parallel between a difference circuit 203 and a node (node)-201, and a register (a capacitor for storing and storing electric charges are referred to as a register D, D ') 20
1 and 202, together with a difference circuit 203, an operational amplifier OP101 having a capacitor with a switch in the feedback path of FIG.
1 shows a configuration of an integrating circuit. 205 is 2
A value quantization circuit 206 is a delay circuit. The input terminal of the register 201 is connected to the terminal of the changeover switch s-210, and the terminal of the changeover switch s-210 is connected first to the input terminal in. Hereinafter, with reference to FIG.
This embodiment will be described.
【００１９】まず、入力信号が端子ｉｎに与えられる
と、第１回目の積分動作時にはスイッチｓ−２１０は
側、スイッチｓ−２１１はオン、ｓ−２１２はオフとな
り、差分回路２０３において入力信号とΔΣ符号（遅延
回路２０６の出力）との差分がとられ、この差信号がレ
ジスタ２０１に加えられる。First, when an input signal is given to the terminal in, the switch s-210 is turned on, the switch s-211 is turned on, and s-212 is turned off during the first integration operation. The difference from the ΔΣ code (output of the delay circuit 206) is obtained, and the difference signal is added to the register 201.
【００２０】更に、２回目の積分動作時には、スイッチ
ｓ−２１０は端子側、スイッチｓ−２１１はオフ、ｓ
−２１２はオンとなり、差分回路２０３において、同様
にして、レジスタ２０１に蓄積された差信号（１回目の
積分結果）とΔΣ符号との差分がとられ、この信号がレ
ジスタ２０２に加えられる。Further, at the time of the second integration operation, the switch s-210 is on the terminal side, the switch s-211 is off, and s
The signal −212 is turned on, and the difference circuit 203 calculates a difference between the difference signal (first integration result) accumulated in the register 201 and the ΔΣ sign in the same manner, and adds this signal to the register 202.
【００２１】最後の２値量子化回路２０５では、前段の
積分回路の出力の正負を判定して、図３に示すようなΔ
Σ符号を出力する。このΔΣ符号は次のサンプル点にお
ける近似信号として用いられるため遅延回路２０６に加
えられる。The last binary quantization circuit 205 determines whether the output of the integration circuit at the preceding stage is positive or negative, and determines whether the output is ΔΔ as shown in FIG.
Σ Output the sign. Since this ΔΣ code is used as an approximate signal at the next sample point, it is added to the delay circuit 206.
【００２２】いま、入力サンプル値系列のｚ変換をＸ
（ｚ）、出力サンプル値系列のｚ変換をＹ（ｚ）、２値
量子化回路による量子化誤差をＱ（ｚ）、積分回路の伝
達関数を１／（１−ｚ-1）、更に、遅延回路の伝達関数
をｚ-1とすると、第１回目の積分動作後では節点ｎｏｄ
ｅ−２０１の信号ｙ1は次式（２）のようになる。Now, the z-transform of the input sample value series is represented by X
(Z), the z-transform of the output sample value series is Y (z), the quantization error by the binary quantization circuit is Q (z), the transfer function of the integration circuit is 1 / (1−z −1 ), Assuming that the transfer function of the delay circuit is z −1 , the node nod after the first integration operation
signal y 1 of e-201 is expressed by the following equation (2).
【００２３】[0023]
【数１】 [Equation 1]
【００２４】従って、２回目の積分動作後には、図４か
ら次式（３）が成り立つ。Therefore, after the second integration operation, the following equation (3) holds from FIG.
【００２５】[0025]
【数２】 [Equation 2]
【００２６】これを整理すると次式（４）が導かれる。When this is arranged, the following equation (4) is derived.
【００２７】 Ｙ(ｚ)＝Ｘ(ｚ)＋(１−ｚ-1)2Ｑ(ｚ) …(4)Y (z) = X (z) + (1-z −1 ) 2 Q (z) (4)
【００２８】ここで、（１−ｚ-1）は振幅周波数特性は
｜１−ｅ(-jωT)｜であるので、低域周波数成分を圧縮
し、高域周波数成分を持ち上げる特性を持つことが分か
る。Here, since (1-z -1 ) has an amplitude frequency characteristic of | 1-e (-jωT) |, it has a characteristic of compressing low frequency components and raising high frequency components. I understand.
【００２９】[0029]
【発明の効果】以上説明したように、本発明の２次アナ
ログデルタシグマ変調器によれば、積分器を時分割多重
使用する機構とコントロール回路とを備え、一つの積分
器で２回の積分操作を時分割して行うようにしたため、
集積化する際に、従来の２次デルタシグマ変調器より少
ないマスク面積で変調器を構成できるという効果を有す
る。As described above, according to the second-order analog delta-sigma modulator of the present invention, a mechanism for using an integrator in a time-division multiplexing manner and a control circuit are provided. Since the operation is performed in a time-sharing manner,
When integrated, there is an effect that the modulator can be configured with a smaller mask area than the conventional second-order delta-sigma modulator.
【図１】本発明の一実施形態の構成を示す図である。FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.
【図２】本発明の一実施形態における各スイッチの制御
信号のタイミング波形を示す図である。FIG. 2 is a diagram showing a timing waveform of a control signal of each switch according to an embodiment of the present invention.
【図３】本発明の一実施形態のシミュレーション結果を
示す図である。FIG. 3 is a diagram showing a simulation result of one embodiment of the present invention.
【図４】本発明の原理的な構成を示したシグナルフロー
図である。FIG. 4 is a signal flow diagram showing a basic configuration of the present invention.
【図５】従来の２次アナログデルタシグマ変調器のブロ
ック図である。FIG. 5 is a block diagram of a conventional secondary analog delta-sigma modulator.
【図６】従来の２次デルタシグマ変調器の原理的な構成
を示したシグナルフロー図、及び各部の信号を示した図
である。FIG. 6 is a signal flow diagram showing a principle configuration of a conventional second-order delta-sigma modulator, and a diagram showing signals of respective parts.
ｓ−１０１〜ｓ−１１２、ｓ−２１０〜ｓ−１２１、Ｓ
−３０１〜Ｓ−３１２スイッチ Ｃ−１１〜Ｃ−１３ キャパシタ ＩＮＴ−４０１、ＩＮＴ−４０２ 積分回路（積分器） １０３、Ｄ３０１、２０６、４０６ 遅延回路 １０２、２０５、３０１、４０５ ２値量子化回路 ２０１、２０２ レジスタ ２０３、４０３、４０４ 差分回路s-101 to s-112, s-210 to s-121, S
-301 to S-312 switches C-11 to C-13 Capacitors INT-401, INT-402 Integrator (integrator) 103, D301, 206, 406 Delay circuit 102, 205, 301, 405 Binary quantization circuit 201 , 202 register 203, 403, 404 difference circuit
Claims (2)
シタと、２回目の積分結果を保持するためのスイッチ付
きキャパシタと、を演算増幅器の帰還路に並設し、 入力端子に入力された入力信号とデルタシグマ（ΔΣ）
符号出力との差分の第１の積分操作と、該積分結果とこ
のデルタシグマ（ΔΣ）符号出力との差分の第２の積分
操作と、を一つの演算増幅器にて時分割多重で行い、前
記第２の積分操作の結果を２値量子化してデルタシグマ
（ΔΣ）符号を出力することを特徴とする２次デルタシ
グマ変調器。1. In a second-order delta-sigma modulator, a switched capacitor for holding a first integration result and a switched capacitor for holding a second integration result are provided in a feedback path of an operational amplifier. Input signal and delta sigma (ΔΣ) input side by side in parallel
The first integration operation of the difference from the code output and the second integration operation of the difference between the integration result and the delta sigma (ΔΣ) code output are performed by one operational amplifier by time division multiplexing, A second-order delta-sigma modulator characterized by binary-quantizing the result of the second integration operation and outputting a delta-sigma (ΔΣ) code.
ャパシタ」という）による負帰還が施されたオペアンプ
からなる積分回路と、 前記積分回路の出力を受ける２値量子化回路と、 入力端子と前記積分回路を接続し、アナログ入力振幅、
及び前記積分回路の振幅に比例した電荷を、前記積分回
路の帰還キャパシタに移す第１のスイッチ付きキャパシ
タ回路と、 前記積分回路に接続され、基準電圧に比例した基準電荷
を前記積分回路の帰還キャパシタに移す第２のスイッチ
付きキャパシタ回路と、 前記２値量子化回路の出力に応じて前記基準電荷の前記
積分回路の帰還キャパシタへの転送を制御する手段と、 を備えたことを特徴とする２次デルタシグマ変調器。2. An integrating circuit composed of an operational amplifier in which negative feedback is provided by two switched capacitors (referred to as "feedback capacitors"), a binary quantizing circuit for receiving the output of the integrating circuit, an input terminal and the integrating circuit. Connect the circuit, analog input amplitude,
And a first switch-equipped capacitor circuit that transfers a charge proportional to the amplitude of the integration circuit to a feedback capacitor of the integration circuit; and a feedback capacitor of the integration circuit, the reference charge being connected to the integration circuit and proportional to a reference voltage. A second switch-equipped capacitor circuit, and means for controlling the transfer of the reference charge to the feedback capacitor of the integration circuit according to the output of the binary quantization circuit. Next delta sigma modulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8033068A JP2839000B2 (en) | 1996-01-26 | 1996-01-26 | Second-order delta-sigma modulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8033068A JP2839000B2 (en) | 1996-01-26 | 1996-01-26 | Second-order delta-sigma modulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09205369A true JPH09205369A (en) | 1997-08-05 |
| JP2839000B2 JP2839000B2 (en) | 1998-12-16 |
Family
ID=12376420
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8033068A Expired - Fee Related JP2839000B2 (en) | 1996-01-26 | 1996-01-26 | Second-order delta-sigma modulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2839000B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7567194B2 (en) | 2007-06-21 | 2009-07-28 | Sanyo Electric Co., Ltd. | Delta sigma modulator and delta sigma A/D converter |
| JP2010056713A (en) * | 2008-08-27 | 2010-03-11 | Nec Electronics Corp | DeltaSigma ANALOG-TO-DIGITAL CONVERTER |
| JP2016184792A (en) * | 2015-03-25 | 2016-10-20 | エスアイアイ・セミコンダクタ株式会社 | Δς modulator |
| JP2017147712A (en) * | 2015-05-27 | 2017-08-24 | パナソニックＩｐマネジメント株式会社 | AD converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6031315A (en) * | 1983-07-29 | 1985-02-18 | Nec Corp | Second order delta sigma modulator |
| JPH0583042A (en) * | 1991-01-15 | 1993-04-02 | Crystal Semiconductor Corp | Low-distorsion amplifier output stage for analog/digital converter |
| JPH06237175A (en) * | 1993-02-09 | 1994-08-23 | Mitsubishi Electric Corp | A/d converter circuit |
| JPH07249989A (en) * | 1994-03-11 | 1995-09-26 | Yamaha Corp | Analog/digital converter |
-
1996
- 1996-01-26 JP JP8033068A patent/JP2839000B2/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6031315A (en) * | 1983-07-29 | 1985-02-18 | Nec Corp | Second order delta sigma modulator |
| JPH0583042A (en) * | 1991-01-15 | 1993-04-02 | Crystal Semiconductor Corp | Low-distorsion amplifier output stage for analog/digital converter |
| JPH06237175A (en) * | 1993-02-09 | 1994-08-23 | Mitsubishi Electric Corp | A/d converter circuit |
| JPH07249989A (en) * | 1994-03-11 | 1995-09-26 | Yamaha Corp | Analog/digital converter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7567194B2 (en) | 2007-06-21 | 2009-07-28 | Sanyo Electric Co., Ltd. | Delta sigma modulator and delta sigma A/D converter |
| JP2010056713A (en) * | 2008-08-27 | 2010-03-11 | Nec Electronics Corp | DeltaSigma ANALOG-TO-DIGITAL CONVERTER |
| US7924192B2 (en) | 2008-08-27 | 2011-04-12 | Renesas Electronics Corporation | ΔΣ analog-to-digital converter |
| US8199040B2 (en) | 2008-08-27 | 2012-06-12 | Renesas Electronics Corporation | Analog-to-digital converter |
| JP2016184792A (en) * | 2015-03-25 | 2016-10-20 | エスアイアイ・セミコンダクタ株式会社 | Δς modulator |
| JP2017147712A (en) * | 2015-05-27 | 2017-08-24 | パナソニックＩｐマネジメント株式会社 | AD converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2839000B2 (en) | 1998-12-16 |
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