JPS6031315A - Second order delta sigma modulator - Google Patents

Abstract

PURPOSE:To attain low power consumption, low cost and miniaturization of a DELTASIGMA modulator itself by means of large circuit integration by constituting circuit components requiring highly accurate operation to an analog signal such as generation of an approximate signal, differential calculation between an input signal or a first stage integration signal and the approximate signal and integration calculation or the like with an operational amplifier, a capacitor and a switch. CONSTITUTION:An input analog signal is given to a terminal 501, a reference voltage is given to a terminal 502, the 1st clock pulse phi1 is given to a terminal 503 and the 2nd clock pulse phi2 is given to a terminal 504 and a DELTASIGMA code is outputted at a terminal 505. The 1st approximate signal is formed by the combination of the 2nd switched capacitor circuit and the 3rd switched capacitor circuit, and the 2nd approximate signal is formed by the combination of the 5th switched capacitor circuit and the 6th switched capacitor circuit. Since an inverting input of an operational amplifier 540 becomes an imaginary grounding point because of the negative feedback by a capacitor C4 and its potential is 0, a current to discharge an electric charge V(t1).C1 stored in a capacitor C1 to 0 flows through the conduction of S2 switches 513, 514.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AD converter, and more particularly to a delta-sigma (ΔΣ) encoder for encoding an analog signal with one bit per sample.

A ΔΣ modulation method is known as a simple method of digitally encoding an analog signal. FIG. 1 is a block diagram showing the basic configuration of a ΔΣ modulator, which encodes an input analog signal applied to an input line 101 and outputs a ΔΣ code, which is a binary digital signal, to a signal line 105. This circuit is a differential circuit 110. i-minute circuit 120 and binary quantization circuit 13
It is composed of many feedback loops including 0. The feedback loose delay is one sample, and is typically shown by the delay circuit 140 in FIG. 1, but when the input signal is a time continuous signal and the binary quantization circuit 130 has a sampling function. Since the sampling operation causes a delay of one sample, there is no need to provide the delay circuit 140. However, in the following explanation, all the signals shown in FIG. 1 will be treated as sample value sequences, that is, time-discrete signals.

Now, assume that an analog signal sampled at a period T is input to the signal line 101 in FIG. 1 as shown in FIG. 2 (1). In the difference circuit 110, the approximate signal appearing on the signal line 102 is subtracted from the input signal applied to the signal line 101, and a difference signal is outputted on the signal line 103. The approximate signal on the signal line 102 is a positive/negative binary signal as shown in FIG. 2(2), and the difference signal generated on the signal line 103 is as shown in FIG. 2(3). This difference signal is then passed to the integrator circuit 120.
The integrated value as shown in Fig. 2 (3) is sent to the signal line 10.
Occurs in 4. The binary quantization circuit 130 determines the polarity of the integral value on the signal line 104, and outputs the ΔΣ sign of the determination result onto the signal line IO5. This ΔΣ code is used as an approximate signal at the next sample point, so the delay circuit 14
given to 0. FIG. 2(5) is the ΔΣ code obtained by determining the polarity of the integral value shown in FIG. 2(4), and is ahead of the approximate signal in FIG. 2(2) by one sample.

The ΔΣ code string obtained on the signal line 105 has a pulse density according to the input signal amplitude, and if this code string is passed through a low-pass filter (LPF), a decoded signal of the original analog waveform can be obtained. . If this LPF is realized by a digital filter, the output after passing the ΔΣ code through the LPF will be a PCM (pulse code modulation) signal corresponding to the decoded waveform of the original analog waveform.

The above can be expressed mathematically as follows. That is,
The 2-transformation of the input sample value series on the signal line 101 is expressed as X (
Z), the Z transformation of the output sample value series obtained on the signal line 05 is designated as Y (Z), and the 2 transformation of the quantization error series by the binary quantization circuit is designated as Q(6), and the 2 of the integrating circuit 120 is If the transfer function is (1-3-1)-1 and the two-transfer function of the one-sample delay circuit 140 is Z-1, the circuit equation for FIG. 1 is as shown in equation (1).

(X(Z)-Z-'Y(z))(1-z-')-'-Y
CZ)-Q(Z) (15If you solve equation (1) for Y(2), you get y(z)-x(z)+(1-Z') Q(Z)(
2), the output signal Y (Z) is the input signal X (Z)
It can be seen that (1-11) times the quantization error Q (Z) is added to the quantization error Q (Z). Although the frequency spectrum of the quantization error Q (z) is flat, it undergoes spectrum shaping by the 2-transfer function (1-Z'').Z=ejωT
Therefore, it can be seen that 1(1-Z')lz=e jωT has the characteristic of compressing the low frequency component and having and increasing the high frequency component (up to 1/2T).

Therefore, such a ΔΣ modulator is suitable for use as a first-stage encoder of a so-called oversampling type AD converter. In an oversampled puppet converter, an analog signal is first encoded by a first-stage encoder at a sampling frequency much higher than the Nyquist rate of the analog signal, and the encoded output is passed through a digital LPF to band limit the Nyquist rate. Resample straight.

Inside the digital filter, one sample is expressed with high precision, for example 16 bits or 24 bits.
When the value ΔΣ sign is input, X(2) and (1
-Z-1') A digital representation of the sample value corresponding to the sum of the in-band components of Q(Z) is obtained. The aforementioned Toto<
The frequency characteristic of (1-Z-1) compresses the low frequency range, so the smaller the band of the digital LPF compared to the sampling frequency of the ΔΣ encoder, the smaller the quantization noise power that falls within the band. . Since the power component outside the band is still sufficiently attenuated by the output of the digital #LPF, this output signal can be sampled again to lower the sampling frequency. By the above operations, the binary Δ
A highly accurate AD conversion code output can be obtained from the Σ code.

In such oversample encoding, a simple configuration Δ
The analog signal is first digitized using the Σ modulator, and all subsequent processing is done digitally to obtain a highly accurate encoded output, which makes it easy to increase precision, is suitable for LSI implementation, and reduces consumption due to LSI implementation. Features such as reduction in power consumption and cost can be obtained.

However, on the other hand, in order to obtain the desired encoding accuracy at the desired sampling rate as the final encoder, the operating speed of the ΔΣ modulator, which is the first-stage encoder, must be considerably high. The lower the sampling rate of this first-stage encoder, the lower the LS
It becomes easier to realize I, etc.

FIG. 3 is a block diagram showing the basic structure of a second-order ΔΣ modulator that can reduce the sampling rate of the first-stage encoder. Reference numbers 301, 3o2 in Figure 3
．． 303 , 304 , 305 , 310 , 320
.

330 and 340 are reference numbers 101 in FIG.
102.

103, 104, 105, 110, 120,
130 and 140, respectively. That is,
In the second-order ΔΣ modulator shown in FIG. 3, a difference circuit 350 and an integration circuit 360 are added to the ΔΣ modulator described in FIG.

The operation of the second-order ΔΣ modulator shown in FIG. 3 is as shown in FIG. 4. That is, when an input signal as shown in FIG. 4(1) is applied to the signal line 301, the difference between this and the ΔΣ sign of FIG. 4(2) is calculated in the difference circuit 310, and the difference between this signal and the ΔΣ sign of FIG. 4(2) is obtained. A difference signal such as is obtained on signal line 303. The integration circuit 320 in FIG. 3 integrates this difference signal and produces the integration result as shown in FIG. The difference of the ΔΣ signs is taken, and a difference signal as shown in FIG. 4(5) is obtained on the signal line 306, which is integrated by the integrating circuit 360 to produce a waveform as shown in FIG. 4(6) on the signal line 307. The binary quantization circuit 330 determines whether the signal on the signal line 307 is positive or negative, and
A ΔΣ sign shown in FIG.

As in the case of the circuit of FIG. 1, the Z transformation of the input sample value series on signal line 301 is
The Z transformation of the output sample value series obtained on 05 is expressed as Y(Z
), the Z transformation of the quantization error series by the binary quantization circuit 330 is Q (Z), the Z transfer function of the integrating circuits 320 and 330 is (i-z-+)-1, and the 2-transfer function of the delay circuit 340 is 2-1, the following equation is obtained as the circuit equation for FIG.

((x(z)-Z-IY(Z))(1-2-1) -z
-+y(z))X(1-Z "-")-' = Y(
Z) -Q(Z) (3) Solving equation (3) for y (z) yields Y(Z)-X(Z)+ (1-Z -1)2Q(Z)
(4) becomes. Comparing equation (4) with equation (2), Q (Z
) is multiplied by (1-Z-1)2 instead of (1-Z-1)(7). (1-Z-1) and (
1-Z-1)" amplitude frequency characteristics are respectively l 1-e
'J''T1 and 1(1-εjωTi+), the degree of compression in the low frequency region is much greater in the latter, and therefore the second-order ΔΣ encoder is set at the same oversampling frequency as the first-order ΔΣ encoder. When operated, the signal band-to-noise ratio of the 2nd-order ΔΣ encoder can be made much larger, and conversely, to obtain the same signal-band-to-noise ratio, the 2nd-order ΔΣ encoder requires a lower oversampling frequency. Therefore, if a second-order ΔΣ modulator is used, the oversampled AD
It can be seen that the converter can be easily realized, especially by LSI.

However, in order to actually implement an oversampled AD converter using such a second-order ΔΣ modulator into an LSI, the second-order ΔΣ modulator itself, which is the first-stage encoder, must be easily made highly accurate, and it is difficult to implement it into an LSI. It must be suitable. By the way, when trying to realize a second-order ΔΣ modulator using the conventional technology, it is necessary to realize highly accurate integrators 320 and 360 in FIG. There was a problem with the way it was generated. In other words, if an integrator circuit is realized by a combination of a resistor and a capacitor, the time constant of the integrator circuit depends on the absolute values of the resistor and capacitor. Even if a leaky integrator, which is an approximation of integral, is realized, the desired resistance value and capacitor value are LS
There were problems such as it being difficult to implement within I and becoming extremely large. Furthermore, it is difficult to precisely control the resistance value and capacitor value within the LSI, resulting in problems such as variations in characteristics between individual encoders. Furthermore, it is required that the two levels of the approximate signal input to the differential circuit do not vary between individual encoders, and do not fluctuate due to changes in environmental conditions such as temperature.

An object of the present invention is to provide a new second-order ΔΣ modulator that can satisfy such requirements.

According to the present invention, first and second integrating circuits each include an operational amplifier subjected to negative feedback using a capacitor, a binary quantization circuit receiving the output of the second integrating circuit, and an input terminal and a first integrating circuit.
A first switched capacitor circuit connects the integrator circuit and transfers the charge proportional to the analog input amplitude to the feedback capacitor of the first integrator circuit; a second switched capacitor circuit that transfers the reference charge of 1 to the feedback capacitor of the first integrating circuit; is a third switched capacitor circuit that transfers second reference charges of different magnitudes and different polarities to the feedback capacitor of the first integrating circuit, and a first integrating circuit that connects the first integrating circuit and the second integrating circuit. a fourth switched capacitor circuit that transfers a charge proportional to the output amplitude of the circuit to a feedback capacitor of the second integrating circuit; and a third switched capacitor circuit that connects the reference voltage source and the second integrating circuit and is proportional to the reference voltage. a fifth switched capacitor circuit that transfers a reference charge to a feedback capacitor of a second integrating circuit; and a fifth switched capacitor circuit that connects the reference voltage source and the second integrating circuit and is proportional to the reference voltage but different from the third reference charge. The fourth polarity differs in size.
a sixth switched capacitor circuit that transfers the reference charge of the first and third reference charges to the feedback capacitor of the second integrating circuit;
and means for controlling the transfer to the feedback capacitor of the second integrating circuit.

FIG. 5 is a diagram showing an embodiment of a second-order ΔΣ modulator according to the present invention. Input analog signal to terminal 501, terminal 502
a reference voltage at terminal 503, a first clock pulse φ1 at terminal 503,
A second clock pulse φ2 is applied to the terminal 504,
A ΔΣ code is output to terminal 505.

The second-order ΔΣ modulator of the present invention includes switches 511 . 512
513, 514, a first switched capacitor circuit consisting of capacitor C1, and switches 515, 516
, 517.

518 and a second switched capacitor circuit consisting of a capacitor C2, and switches 519 , 520 , 521
, 522 and a capacitor C3, and an operational amplifier 540 and a capacitor C2.
a first integrating circuit consisting of switches 523 and 524;
, 525° 526 and a fourth switched capacitor circuit consisting of a capacitor C6, and switches 527 and 528.
．． 529, 530 and a fifth switch-equipped canister circuit consisting of capacitor C6, and switches 531, 53
2, 533, 534 and a sixth capacitor C7.
, a second integration circuit consisting of an operational amplifier 550 and a capacitor C8, a binary quantization circuit 560, and an AND circuit 570.

S1 switches 511, 512, 515, 516
, 519.

520, 523, 524, 527, 528,
531 and 532 are transmission gates whose opening and closing are controlled by the first clock pulse φ1 shown in FIG.
T-τ remains conductive in the interval τ0 shown in Figure y. There is no conduction in the section. S2 switches 513, 514,
521.522゜525, 526, 533, 534
is a transmission gate whose opening and closing are controlled by the second clock pulse φ2 shown in FIG. It operates at the timing of key φ2 of 1'' (operates in the same manner as the 82 switch), and remains non-conductive when the output of the binary quantization circuit 560 is 0''.

A first approximate signal is created by the combination of the second switched capacitor circuit and the third switched capacitor circuit,
A second approximate signal is created by the combination of the fifth switched capacitor circuit and the sixth switched capacitor circuit. The second approximation signal is equal to the first approximation signal with its sign (polarity) inverted. The first approximation signal is obtained by subtracting a fixed bias of 1 unit amplitude created by the third switched capacitor circuit from a unipolar binary signal of 2 units amplitude created by the second switched capacitor circuit. By this,
It is a bipolar binary signal with a single amplitude of ±11. The generation of the second approximation signal is also basically the same except for the polarity,
By subtracting the fixed bias of 1 unit amplitude from the unipolar binary signal of 2 unit amplitude, a bipolar binary signal of ±11 single amplitudes is obtained.

First, consider the operation of the circuit shown in FIG. 5 when φ1 is "1". At this time, in the first switched capacitor circuit, the S1 switches 511 and 512 are conductive and the S2 switches 513 and 514 are non-conductive, so that the analog input voltage V applied to the terminal 501 is applied to the capacitor C1.
(t) causes a charge of V(t)·C1 to flow in. The charge stored in capacitor C1 fluctuates as V (t) changes, but when pulse φ1 changes from 1" to "0", the input voltage V (tl) immediately before the change is stored. In other words, in this circuit, pulse φ1 is 1
The purpose of this is to sample and hold the input signal at the time when it changes from "0" to "0".

At this time, in the second switched capacitor circuit, the S1 switches 515 and 516 are conductive, and the S2' switch 517 is turned on.
, 518 are non-conductive, both ends of the capacitor C2 are short-circuited and the charge is zero. - In the capacitor circuit with switch of power tube 3, S1 switch 519, 520
conducts, and S2 switches 521 and 522 hold it.

Similarly, in the fourth switched capacitor circuit, the charge of the capacitor C3 is discharged to 0, and in the fifth switched capacitor circuit, the capacitor C6 is charged to the reference voltage E and holds the charge EC6. In the switched capacitor circuit, the charge of the capacitor C7 is discharged and becomes O.

Next, consider the state in which φ2 becomes 1". At this time, all 82 switches are conductive and all 81 switches are non-conductive. If the ΔΣ sign output is 1n, the S2' switch is conductive and "0". ”, it becomes non-conducting.

The negative input of the operational amplifier 540 receives negative feedback from the capacitor C4, and since the potential of the virtual ground point is O, S2
Due to the conduction of the switches 513 and 514, the capacitor C1
A current flows to discharge the charge V(tl)·C1 stored in the current to 0. Since this current flows through capacitor C2, the charge stored in C1 is transferred to capacitor C4.
will be moved to. Therefore, when the discharge of the capacitor C1 is completed, the output of the operational amplifier 540 is V(t
A voltage change of l)·c, ,'c occurs. At this time, current as an approximate signal further flows into the negative input of the operational amplifier 540 from the capacitors c2 and C8. Now if ΔΣ
If the sign output is "1" and the 82' switches 517 and 518 are conductive, the thunder gain of Kise no Kushita C9 is rapidly charged towards E・C7 from the 0 of the book sword F3≠,
The charging current at that time flows into the capacitor C4, and a voltage of -B C2/C4i is generated at the operational amplifier 540 at the time of completion of charging. Mogo; If the Chirun ΔΣ sign output is “0” W, this voltage change is 0.
It is. On the other hand, a current flows from the capacitor c3 to discharge the charge EC3 regardless of the state of the ΔΣ sign.
6, causing the output of the operational amplifier 540 to become overloaded by E C, /C at the time of completion of discharge. Here, assuming C2=2×C3 and summarizing the above, the voltage change at the output of the operational amplifier 540 is as follows.

When ΔΣ code is “O”, V(L+)Ct/C4+ PC8/C4(5) When ΔΣ code is “1”, v(tl)c+/c4EC3/C4(6) In other words, the differential circuit 310 in FIG. The difference signal calculation between the input signal and the approximate signal is performed. Note that equations (5) and (6) show only the changes in the output voltage of the operational amplifier, and the output of the operational amplifier performs the accumulation of this change, that is, the operation of the integrating circuit 320 in FIG. 3.

At this time, the fourth In the fifth and sixth switched capacitor circuits and the operational amplifier 550, the differential circuit 3 of FIG.
50 and the integration circuit 360 are operated. That is, when the output voltage of the operational amplifier 540 is W(t), the capacitor C4l is charged to W(t), and this charging current flows through the capacitor C8, so that the output voltage of the operational amplifier 550 becomes -W(t)・C5. A voltage change of /CM is caused. At this time, from the fifth switched capacitor circuit, Δ
When the Σ sign is "0", it is o1.When the Σ sign is "1", it is the charge EC of the capacitor C0.

A current discharging the current flows through capacitor C8.

Further, a current for charging the capacitor C9 to the voltage E flows from the sixth switched capacitor circuit through the capacitor c7. As a result, the voltage change at the output of the operational amplifier 550 occurs at the time when φ2 changes from 1'' to 0 (z=t,
) becomes the following. However, C,=2XC.

When the ΔΣ sign is “0”, W(tz) Cs/Ca ECt/Co (When the force ΔΣ sign is “1”, −W(t2) C5/C8+EC?/C1l (s) Both equations are (-1) As you can see by multiplying it, the fourth
The fifth and sixth switched capacitor circuits and the operational amplifier 550 perform the operations of the differential circuit 350 and the integrating circuit 360 in FIG.

Next, when φ2 changes to "0", capacitor CI.

C2 and C3 are from the operational amplifier 540, and the capacitor c
,.

C6yC7 are each separated from the operational amplifier 550, so the operational amplifiers 540 and 550 each have a φ2 of “
The output voltage immediately before becoming 0" is held until φ2 becomes "1" again. In the binary quantization circuit 560, φ
When 1 becomes 1", determine whether the output of the operational amplifier 550 is positive or negative. If it is negative, the ΔΣ sign is 1", and if it is positive, Δ
Outputs “0” as the Σ code. This ΔΣ sign is A,
is applied to ND circuit 570 to determine the value of φ2' at the next sample instant, and thus the polarity of the approximation signal. That is, the role of the 1-sample delay circuit in FIG. 3 is isometrically fulfilled by the sampling operation using the clock φ1 in the binary quantization circuit 560.

Further, the fourth switched capacitor circuit connecting the opera amplifiers 540 and 550 is configured to have no delay, making it possible to set the loop delay time to one sample.

As explained above, the circuit shown in FIG.
This realizes the same operation as the principle diagram of the next-order ΔΣ modulator. The parts that require high-precision calculations on analog signals, such as generation of approximate signals, calculation of differences between input signals or first-stage integral signals and approximate signals, and integral calculations, are composed of operational amplifiers, capacitors, and switches, and the capacitors also calculate their absolute values. Since it is used with attention paid to their ratio rather than their ratio, it is easy to convert it into an LSI using MO8 branch technique or the like. Furthermore, only one type of reference voltage source is required from the outside, and the accuracy of the approximate signal is determined only by the ratios of this reference voltage and the capacities C2 and C3 and C6 and C7, and is not affected by the ΔΣ code output pulse waveform or the like.

Also, since the gain factor for the input signal and approximate signal is arbitrarily determined by the capacitor ratio such as C1/C4 or C2/C4, the reference voltage can be set independently of the encoding dynamic range (maximum input signal range that can be encoded). There are also features that can be defined.

Furthermore, compared to the method of using a resistor and constantly passing current through the resistor, the present invention utilizes charging and discharging of a capacitor, so it is essentially suitable for lower power consumption. Taking all these features together, the second-order ΔΣ modulator according to the present invention is suitable for LSI integration.
By reducing the power consumption and cost of the ΔΣ modulator itself,
It is possible to easily realize an oversampling type AD converter that can be made compact and highly accurate at a relatively low sampling frequency.

In the above explanation, a method was used in which the input analog signal was held as a sample value in the capacitor C1 and then the charge was transferred to the integrator. It is also possible to directly input the signal to the integrator and calculate the difference from the approximate signal. In this case, the input signal at the end of 1'' of clock φ2 will be sampled.Also, the same effect can be achieved by switching the roles of the second and third or fifth and sixth switched capacitor circuits. It is also possible to obtain

Furthermore, in the explanation, C2-2×03. C6=2×07, but C2−2×C3suε, Ca “” 2×C?
In terms of characteristics, it may be better to have a slight deviation ε from ±ε. These also do not go outside the scope of the invention.

[Brief explanation of drawings]

FIG. 3 is a diagram showing operating waveforms in each part of the second-order ΔΣ modulator, FIG. 5 is a diagram showing an embodiment of the second-order ΔΣ modulator according to the present invention, and FIG. 6 is an explanation of the operation of FIG. 5. It is an auxiliary timing diagram of Sudame. In the figure reference numeral 110,
310, 350 are differential circuits, 120, 320, 3
60 is an integration circuit, 130 and 330 are binary quantization circuits,
140 and 340 are delay circuits; 511 and 512; ..., 533, 534 are pulses φ1. φ2. 540 and 550 are operational amplifiers, 560 is a binary quantization circuit, and 570 is an AND circuit.

Claims (1)

[Claims] The first and second integrating circuits each include an operational amplifier that is given negative feedback by a capacitor, the binary quantization circuit receives the output of the second integrating circuit, and the input terminal is connected to the first integrating circuit to obtain an analog input amplitude. A first switched capacitor circuit that transfers a proportional charge to a feedback capacitor of a first integrating circuit, and a first integrated circuit that connects a reference voltage source and the first integrating circuit to transfer a first reference charge proportional to the reference voltage to a first integrating circuit. a second switched capacitor circuit that connects the reference voltage source and the first integrating circuit to transfer the voltage to the feedback capacitor of the circuit; and a second switched capacitor circuit that connects the reference voltage source and the first integrating circuit; 2
a third switched capacitor circuit that transfers the reference charge of the reference charge to the feedback capacitor of the first integrating circuit; a fourth switched capacitor circuit that transfers a third reference charge proportional to the reference voltage to the feedback capacitor of the second integrating circuit, which connects the reference voltage source and the second integrating circuit; a fifth switched capacitor circuit connected to the reference voltage source and the second integrating circuit, and a fourth reference charge which is proportional to the reference voltage but has a different magnitude and polarity than the third reference charge; the second
a sixth switched capacitor circuit for transferring the first and third reference charges to the feedback capacitors of the first and second integrating circuits according to the output of the binary quantization circuit; 1. A second-order delta-sigma modulator, comprising: means for controlling transfer to a second-order delta-sigma modulator;