CN111262586B

CN111262586B - Second-order noise shaping successive approximation analog-to-digital converter

Info

Publication number: CN111262586B
Application number: CN202010210742.2A
Authority: CN
Inventors: 于奇; 黄文杰; 张启辉; 李靖; 宁宁
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-03-24
Filing date: 2020-03-24
Publication date: 2022-03-29
Anticipated expiration: 2040-03-24
Also published as: CN111262586A

Abstract

A second-order noise shaping successive approximation analog-to-digital converter belongs to the technical field of analog-to-digital conversion. The device is applicable to a single-ended capacitor array structure and a double-ended capacitor array structure and comprises a capacitor DAC module, a first integrator module, a preamplifier module, a second integrator module, a comparison module and a successive approximation logic module which are sequentially connected. The invention adopts double passive integrators to form a cascade integral feedback structure to realize second-order noise shaping, wherein the preamplifier module can be used as a preposed operational amplifier in a quantization stage and can also be used as a residual sampling operational amplifier in a residual sampling stage, thereby improving the reusability and eliminating the offset influence; the second-order shaping effect of the quantization noise on the output result is realized by integrating the residual error after the successive approximation for two times, and the method has the characteristics of low power consumption and high precision.

Description

Second-order noise shaping successive approximation analog-to-digital converter

Technical Field

The invention belongs to the technical field of analog-digital conversion, and relates to a high-precision second-order noise shaping successive approximation analog-digital converter.

Background

For many medium precision applications, Successive Approximation Register (SAR) Analog-to-Digital converters (ADCs) are popular because of their energy efficiency. However, when the accuracy of the SAR-ADC exceeds 10 bits, its energy efficiency is rapidly reduced due to comparator noise, and at the same time, the chip area becomes large due to the increase of the capacitor array. For high precision low speed applications, Δ Σ -adc (delta Sigma adc) is a widely used structure because it utilizes oversampling and noise shaping, so high precision can be achieved with a low resolution quantizer. The hybrid SAR-ADC is basically applied to high speed, but relatively little research is done in improving accuracy.

Recently, studies on the architecture of the hybrid ADC have increased significantly, especially for the ADC combining the advantages of SAR and Δ Σ, in 2012, the ADC of the first Noise Shaping (Noise Shaping, NS) (j.a.fredenburg and m.p.flunn, "a 90-MS/s 11-MHz-bandwidth 62-dB SNDR Noise-Shaping SAR ADC," IEEE j.solid-State Circuits, vol.47, No.12, pp.2898-2904, dec.2012 ") was published, which implements integration of residuals by an active integrator, thereby implementing the effect of first-order Noise Shaping. In the Noise shaping NS-ADC (z.chen, m.miyahara, and a.matsuzawa, "a 9.35-enob.14.8 f/conv. -step full-passive Noise-shaping SAR ADC," in IEEE symp.vlsi Circuits dig.,. June 2015, pp.c64-C65.) of the following passive integrator, the existence of the active integrator is eliminated, and effective reduction of power consumption is achieved, but the effect of Noise shaping is severely limited, the zero point of the Noise Transfer Function (NTF) can only be 0.5, and the input signal swing is also cut in half. Another CIFF noise shaping SAR ADC architecture (w.guo and n.sun, "a 12 b-ENOB 61 μ W noise-shaping SAR ADC with a passive integrator," in proc.42nd eur.solid-State Circuits con. (escirc), Sep 2016, pp.405-408.) that employs a passive integrator and implements a zero at 0.75 discloses first order noise shaping by a four-terminal comparator.

Conventional noise-shaped successive approximation ADCs (NS-SAR ADCs) are classified into two major categories, one is a Cascaded integral fed-forward (CIFF) structure, and the other is an Error Feedback (EF) structure. The CIFF structure directly loads the residual of the capacitor array after SAR operation to one end of the comparator through the integrator L1(z), while the EF structure directly feeds the residual back to the input end. Both have advantages, first the EF structure requires an operational amplifier to amplify the residual to cancel the reduction factor caused by the redistribution of charge that the residual feeds back to the input capacitance, while the CIFF structure requires an integrator, which may be a passive integrator, to be loaded at one end of the comparator. Compared with a cascade integral feedback CIFF structure, the residual feedback EF structure is easier to realize a second-order structure, but the operational amplifier of the EF structure has the defects of high power consumption and incapability of accurately controlling the amplification factor.

Disclosure of Invention

Aiming at the defects that a second-order structure is not easy to realize in the cascaded integral feedback structure compared with a residual feedback structure, and the high power consumption of an operational amplifier and the inaccurate control of the amplification factor in the realization of the second-order structure by the residual feedback structure, the invention provides a second-order noise shaping successive approximation analog-to-digital converter, and the second-order quantization noise shaping effect of the cascaded integral feedback structure is realized by using a double passive integrator.

The invention provides a second-order noise shaping successive approximation analog-to-digital converter, which comprises a successive approximation analog-to-digital converter of a single-end capacitor array and a successive approximation analog-to-digital converter of a double-end capacitor array, wherein the technical scheme of the successive approximation analog-to-digital converter of the single-end capacitor array is as follows:

a second-order noise-shaping successive approximation analog-to-digital converter comprises a single-end capacitor DAC module, a comparison module and a successive approximation logic module,

the single-ended capacitor DAC module comprises a first capacitor array, a first control switch array and a first reset switch, one end of each switch in the first control switch array is connected with an input signal, a reference positive voltage or a reference negative voltage, and the other end of each switch is connected with the output end of the single-ended capacitor DAC module after passing through a corresponding capacitor in the first capacitor array; the first reset switch is connected between the output end of the single-ended capacitor DAC module and the reference ground;

the input end of the successive approximation logic module is connected with the output end of the comparison module, the control signal output end of the successive approximation logic module outputs a control signal for controlling each switch in the first control switch array, and the data output end of the successive approximation logic module outputs an output signal of the successive approximation analog-to-digital converter;

the successive approximation analog-to-digital converter further comprises a first integrator module, a preamplifier module and a second integrator module,

the first integrator module comprises a first integrating switch, a first integrating capacitor, a third reset switch and a fourth reset switch,

one end of the first integrating switch is used as the input end of the first integrator module, and the other end of the first integrating switch is connected with one end of the fourth reset switch and is connected with the reference ground after passing through the first integrating capacitor;

one end of the third reset switch is connected with the other end of the fourth reset switch and serves as the output end of the first integrator module, and the other end of the third reset switch is connected with the reference ground;

a first positive input end of the preamplifier module is connected with an output end of the single-ended capacitor DAC module and an input end of the first integrator module, a second positive input end of the preamplifier module is connected with an output end of the first integrator module, a first negative input end and a second negative input end of the preamplifier module are connected with a reference ground, and an output end of the preamplifier module is connected with an input end of the second integrator module;

the second integrator module comprises a first sampling capacitor, a second integrating capacitor, a second reset switch and a second integrating switch,

one end of the first sampling capacitor is used as the input end of the second integrator module, and the other end of the first sampling capacitor is connected with one end of the second reset switch and one end of the second integration switch and is used as the first output end of the second integrator module;

the other end of the second reset switch is connected with the reference ground;

one end of the second integrating capacitor is connected with the other end of the second integrating switch and serves as a second output end of the second integrator module, and the other end of the second integrating capacitor is connected with a reference ground;

and a first positive input end of the comparison module is connected with a first output end of the second integrator module, a second negative input end of the comparison module is connected with a second output end of the second integrator module, and a second positive input end and the first negative input end of the comparison module are connected with a reference ground.

Specifically, the preamplifier module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein the sizes of the second NMOS transistor and the third NMOS transistor are equal, the sizes of the fourth NMOS transistor and the fifth NMOS transistor are equal, and the size ratio of the fourth NMOS transistor to the second NMOS transistor is equal to the ratio of the capacitance value of the first integrating capacitor to the total capacitance value of the first capacitor array in the single-ended capacitor DAC module;

the grid electrode of the second NMOS tube is used as a first positive input end of the preamplifier module, the drain electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode and the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube and the grid electrode of the third PMOS tube and is used as an output end of the preamplifier module, and the source electrode of the second NMOS tube is connected with the source electrodes of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube and the drain electrode of the first NMOS tube;

the grid electrode of the first NMOS tube is connected with bias voltage, and the source electrode of the first NMOS tube is connected with the power ground;

the grid electrode of the third NMOS tube is used as a first negative input end of the preamplifier module, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the grid electrode of the fourth PMOS tube and the drain electrode of the fourth PMOS tube;

the grid electrode of the fourth NMOS tube is used as a second positive input end of the preamplifier module, and the grid electrode of the fifth NMOS tube is used as a second negative input end of the preamplifier module;

the source electrodes of the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are connected with a power supply voltage.

Specifically, the comparison module comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first inverter and a second inverter, wherein the seventh NMOS transistor and the eighth NMOS transistor have the same size, the ninth NMOS transistor and the tenth NMOS transistor have the same size, and the size ratio of the tenth NMOS transistor to the seventh NMOS transistor is equal to the ratio of the capacitance value of the second integrating capacitor to the capacitance value of the first sampling capacitor;

the grid electrode of the seventh NMOS tube is used as a first positive input end of the comparison module, the drain electrode of the seventh NMOS tube is connected with the drain electrode of the ninth NMOS tube and the source electrode of the eleventh NMOS tube, and the source electrode of the seventh NMOS tube is connected with the source electrodes of the eighth NMOS tube, the ninth NMOS tube and the tenth NMOS tube and the drain electrode of the sixth NMOS tube;

a grid electrode of the eighth NMOS tube is used as a first negative input end of the comparison module, and a drain electrode of the eighth NMOS tube is connected with a drain electrode of the tenth NMOS tube and a source electrode of the twelfth NMOS tube;

a grid electrode of a ninth NMOS tube is used as a second positive input end of the comparison module, and a grid electrode of a tenth NMOS tube is used as a second negative input end of the comparison module;

the grid electrode of the sixth NMOS tube is connected with the grid electrodes of the fifth PMOS tube and the eighth PMOS tube and is connected with a clock signal, and the source electrode of the sixth NMOS tube is connected with a power ground;

the grid electrode of the sixth PMOS tube is connected with the drain electrodes of the seventh PMOS tube, the eighth PMOS tube and the twelfth NMOS tube as well as the grid electrode of the eleventh NMOS tube and the input end of the second phase inverter, the drain electrode of the sixth PMOS tube is connected with the drain electrodes of the fifth PMOS tube and the eleventh NMOS tube, the grid electrodes of the seventh PMOS tube and the twelfth NMOS tube as well as the input end of the first phase inverter, and the source electrode of the sixth PMOS tube is connected with the source electrodes of the fifth PMOS tube, the seventh PMOS tube and the eighth PMOS tube and is connected with the power supply voltage;

the output end of the first inverter is used as the output end of the comparison module.

Specifically, the reference ground is a median voltage of the reference positive voltage and the reference negative voltage.

The technical scheme of the successive approximation analog-to-digital converter with the double-end capacitor array comprises the following steps:

a second-order noise-shaping successive approximation analog-to-digital converter comprises a double-end capacitor DAC module, a comparison module and a successive approximation logic module,

the double-end capacitor DAC module comprises a second capacitor array, a second control switch array, a fifth reset switch, a third capacitor array, a third control switch array and a sixth reset switch,

one end of each switch in the second control switch array is connected with the forward input signal, the reference positive voltage or the reference negative voltage, and the other end of each switch is connected with the forward output end of the double-end capacitor DAC module after passing through the corresponding capacitor in the second capacitor array; the fifth reset switch is connected between the forward output end of the double-end capacitor DAC module and the reference ground;

one end of each switch in the third control switch array is connected with a negative input signal, a reference positive voltage or a reference negative voltage, and the other end of each switch is connected with a negative output end of the double-end capacitor DAC module after passing through a corresponding capacitor in the third capacitor array; the sixth reset switch is connected between the negative output end of the double-end capacitor DAC module and the reference ground;

the positive input end of the successive approximation logic module is connected with the positive output end of the comparison module, the negative input end of the successive approximation logic module is connected with the negative output end of the comparison module, the first control signal output end of the successive approximation logic module outputs a control signal for controlling each switch in the second control switch array, the second control signal output end of the successive approximation logic module outputs a control signal for controlling each switch in the third control switch array, and the data output end of the successive approximation logic module outputs an output signal of the successive approximation analog-to-digital converter;

the successive approximation analog-to-digital converter further comprises a preamplifier module, two first integrator modules and two second integrator modules,

a first positive input end of the preamplifier module is connected with a positive output end of the double-end capacitor DAC module and an input end of a first one of the first integrator modules, a second positive input end of the preamplifier module is connected with an output end of the first one of the first integrator modules, a first negative input end of the preamplifier module is connected with a negative output end of the double-end capacitor DAC module and an input end of a second one of the first integrator modules, a second negative input end of the preamplifier module is connected with an output end of the second one of the first integrator modules, a positive output end of the preamplifier module is connected with an input end of the first one of the second integrator modules, and a negative output end of the preamplifier module is connected with an input end of the second one of the second integrator modules;

a first positive input end of the comparison module is connected to a first output end of a first one of the second integrator modules, a second negative input end of the comparison module is connected to a second output end of the first one of the second integrator modules, a second positive input end of the comparison module is connected to a second output end of a second one of the second integrator modules, and a first negative input end of the comparison module is connected to a first output end of the second one of the second integrator modules.

Specifically, the preamplifier module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein the sizes of the second NMOS transistor and the third NMOS transistor are equal, the sizes of the fourth NMOS transistor and the fifth NMOS transistor are equal, and the size ratio of the fourth NMOS transistor to the second NMOS transistor is equal to the ratio of the capacitance value of the first integrating capacitor to the total capacitance value of the second capacitor array or the third capacitor array in the double-end capacitor DAC module;

the grid electrode of the second NMOS tube is used as a first positive input end of the preamplifier module, the drain electrode of the second NMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode and the drain electrode of the first PMOS tube, the drain electrode of the second PMOS tube and the grid electrode of the third PMOS tube and is used as a positive output end of the preamplifier module, and the source electrode of the second NMOS tube is connected with the source electrodes of the third NMOS tube, the fourth NMOS tube and the fifth NMOS tube and the drain electrode of the first NMOS tube;

the grid electrode of the third NMOS tube is used as a first negative input end of the preamplifier module, and the drain electrode of the third NMOS tube is connected with the drain electrode of the fifth NMOS tube, the grid electrode of the second PMOS tube, the drain electrode of the third PMOS tube and the grid electrode and the drain electrode of the fourth PMOS tube and is used as a negative output end of the preamplifier module;

the output end of the first phase inverter is used as the positive output end of the comparison module, and the output end of the second phase inverter is used as the negative output end of the comparison module.

The invention has the beneficial effects that: according to the invention, a cascade integral feedback structure is formed by adopting double passive integrators to realize second-order noise shaping, and the second-order shaping effect of the quantized noise on the output result is realized by integrating the residual error after successive approximation for two times; according to the invention, the preamplifier module is introduced between the comparison module and the DAC capacitor array, so that the preamplifier can be used as a pre-operational amplifier during comparison and also can be used as a second-stage residual sampling operational amplifier, the reusability is improved, the output offset storage of the open-loop amplifier is realized, the influence of offset is eliminated, the noise of the open-loop operational amplifier can realize first-order shaping, and meanwhile, the noise of the comparison module is subjected to second-order shaping, so that the low power consumption is realized and the high precision is also realized; meanwhile, another cascaded integral feedback (CIFF feedback) branch is introduced between the open-loop operational amplifier and the comparison module, and second-order noise shaping is integrally realized.

Drawings

Fig. 1 is a signal flow diagram of a cascaded integral feedback CIFF structure (fig. 1(a)) and an error feedback EF structure (fig. 1(b)) of a noise-shaping ADC.

Fig. 2 is a system block diagram of a second-order noise-shaping successive approximation analog-to-digital converter according to an embodiment of the present invention, in which a single-ended capacitor array structure is adopted.

Fig. 3 is a circuit structure diagram of a second-order noise-shaping successive approximation analog-to-digital converter adopting a single-ended capacitor array structure according to the present invention.

Fig. 4 is a circuit implementation structure diagram of a preamplifier module in a second-order noise-shaping successive approximation analog-to-digital converter according to the present invention.

Fig. 5 is a circuit implementation structure diagram of a comparison module (LATCH) in a second-order noise-shaped successive approximation analog-to-digital converter according to the present invention.

Fig. 6 is a timing control diagram of a second-order noise-shaping successive approximation analog-to-digital converter according to the present invention.

Fig. 7 is a frequency spectrum diagram of a simulation output result of a second-order noise-shaped successive approximation analog-to-digital converter according to the present invention.

Fig. 8 is a circuit structure diagram of a second-order noise-shaping successive approximation analog-to-digital converter adopting a double-end capacitor array structure according to the present invention.

Detailed Description

The technical scheme of the invention is further explained by embodiments in the following with reference to the attached drawings.

The invention provides a second-order noise shaping successive approximation analog-to-digital converter, and provides two forms of a single-end capacitor array structure and a double-end capacitor array structure, as shown in fig. 3, the invention adopts the single-end capacitor array structure to realize the structure block diagram of the second-order noise shaping successive approximation analog-to-digital converter, which comprises a single-end capacitor DAC module, a first integrator module, a preamplifier module, a second integrator module, a comparison module (LATCH) and a successive approximation Logic module (SAR Logic), wherein the capacitor DAC module is a single-end capacitor DAC module and comprises a first capacitor array C_DACA first control switch array S_DACAnd a first reset switch S_R1One end of each switch in the first control switch array is connected with an input signal Vin, a reference positive voltage Vrefp or a reference negative voltage Vrefn, and the other end of each switch passes through the first capacitor array respectivelyThe output end of the single-end capacitor DAC module is connected with the back of the corresponding capacitor; first capacitor array C_DACIs connected with each other and is connected with one end of a first reset switch SR1 and the output end of a single-end capacitor DAC module, and a first capacitor array C_DACThe lower plates of the capacitors are respectively connected with a first control switch array S_DACOne end of the middle switch; first reset switch S_R1And the single-ended capacitor DAC module is connected between the output end of the single-ended capacitor DAC module and the reference ground. A successive approximation Logic module (SAR Logic) generates a control signal for controlling each switch in the first control switch array according to the output signal of the comparison module. The output end of the single-ended capacitor DAC module is connected with the first positive input end of the preamplifier module and the input end of the first integrator module.

The input terminal of the first integrator module is connected to the output terminal of the single-ended capacitor DAC module, and the output terminal is connected to the second positive input terminal of the preamplifier module, as shown in FIG. 3, the first integrator module includes a first integrating switch S_I1A first integrating capacitor C_I1And a third reset switch S_R3And a fourth reset switch S_R4First integral switch S_I1As the input of the first integrator module, and the other end is connected to the fourth reset switch S_R4And through a first integrating capacitor C_I1The rear is connected with a reference ground; third reset switch S_R3Is connected with a fourth reset switch S_R4And the other end of the first integrator module is used as the output end of the first integrator module, and the other end of the first integrator module is connected with the reference ground.

The first positive input end of the preamplifier module is connected with the output end of the single-ended capacitor DAC module and the input end of the first integrator module, the second positive input end of the preamplifier module is connected with the output end of the first integrator module, the first negative input end and the second negative input end of the preamplifier module are connected with the reference ground, and the output end of the preamplifier module is connected with the input end of the second integrator module. As shown in fig. 4, an implementation circuit structure of the preamplifier module is provided, which includes a first PMOS transistor MP0, a second PMOS transistor MP1, a third PMOS transistor MP2, a fourth PMOS transistor MP3, a first NMOS transistor MN0, a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3, and a fifth NMOS transistor MN4, wherein the second NMOS transistor MN1 and the third NMOS transistor MN2 are first NMOS transistorsThe input pair transistors are equal in size, the fourth NMOS transistor and the fifth NMOS transistor are second input pair transistors which are equal in size, and the size ratio of the fourth NMOS transistor MN3 to the second NMOS transistor MN1 is equal to that of the first integrating capacitor C_I1And a first capacitor array C in the single-ended capacitor DAC module_DACThe ratio of the total capacitance value of (c); the gate of the second NMOS transistor MN1 is used as the first positive input end V of the preamplifier module_inp1The drain electrode of the preamplifier module is connected with the drain electrode of the fourth NMOS tube MN3, the grid electrode and the drain electrode of the first PMOS tube MP0, the drain electrode of the second PMOS tube MP1 and the grid electrode of the third PMOS tube MP2, and the source electrodes of the preamplifier module are connected with the source electrodes of the third NMOS tube MN2, the fourth NMOS tube MN3 and the fifth NMOS tube MN4 and the drain electrode of the first NMOS tube MN 0; the grid of the first NMOS transistor MN0 is connected with a bias voltage V_biasThe source electrode of the transistor is connected with a power ground; the grid of the third NMOS pipe MN2 is used as a first negative input end V of the preamplifier module_inn1The drain electrode of the PMOS transistor is connected with the drain electrode of a fifth NMOS transistor MN4, the grid electrode of a second PMOS transistor MP1, the drain electrode of a third PMOS transistor MP2 and the grid electrode and the drain electrode of a fourth PMOS transistor MP 3; the gate of the fourth NMOS transistor MN3 is used as the second positive input end V of the preamplifier module_inp2The grid of the fifth NMOS pipe MN4 is used as the second negative input end V of the preamplifier module_inn2(ii) a The source electrodes of the first PMOS transistor MP0, the second PMOS transistor MP1, the third PMOS transistor MP2 and the fourth PMOS transistor MP3 are connected with a power supply voltage V_DD。

The input end of the second integrator module is connected with the output end of the preamplifier, the first output end of the second integrator module is connected with the first positive input end of the comparison module, and the second output end of the second integrator module is connected with the second negative input end of the comparison module. As shown in fig. 3, the second integrator module includes a first sampling capacitor Cs and a second integrating capacitor C_I2A second reset switch S_R2And a second integral switch S_I2One end of the first sampling capacitor Cs is used as the input end of the second integrator module, and the other end of the first sampling capacitor Cs is connected with the second reset switch S_R2And a second integrating switch S_I2And as a first output of the second integrator module; second reset switch S_R2The other end of the first switch is connected with a reference ground; second integrating capacitor C_I2One end of is connected with a second integral switch S_I2And the other end of the second integrator module is used as a second output end of the second integrator module, and the other end of the second integrator module is connected with the reference ground.

The comparison module is of a four-input structure, a first positive input end of the comparison module is connected with a first output end of the second integrator module, a second negative input end of the comparison module is connected with a second output end of the second integrator module, and a second positive input end and the first negative input end of the comparison module are connected with a reference ground. As shown in fig. 5, an implementation structure of the comparison module is provided, which includes a sixth NMOS transistor MN5, a seventh NMOS transistor MN6, an eighth NMOS transistor MN7, a ninth NMOS transistor MN8, a tenth NMOS transistor MN9, an eleventh NMOS transistor MN10, a twelfth NMOS transistor MN11, a fifth PMOS transistor MP4, a sixth PMOS transistor MP5, a seventh PMOS transistor MP6, an eighth PMOS transistor MP7, a first inverter INV0, and a second inverter INV1, wherein the seventh NMOS transistor MN6, the eighth NMOS transistor MN7, the ninth NMOS transistor MN8, and the tenth NMOS transistor MN9 are input transistors of the comparison module, the seventh NMOS transistor MN6 and the eighth NMOS transistor MN7 are the first input transistor of the same size, the ninth NMOS transistor MN8 and the tenth NMOS transistor MN9 are the second input transistor of the same size, and an integral ratio of the tenth NMOS transistor MN9 and the seventh NMOS transistor MN6 is equal to a second integral ratio of the second capacitor C_I2And a first sampling capacitor C_SThe ratio of the capacitance values of (a); the grid electrode of the seventh NMOS transistor MN6 is used as a first positive input end Vinp1 of the comparison module, the drain electrode of the seventh NMOS transistor MN6 is connected with the drain electrode of the ninth NMOS transistor MN8 and the source electrode of the eleventh NMOS transistor MN10, and the source electrode of the seventh NMOS transistor MN is connected with the source electrodes of the eighth NMOS transistor MN7, the ninth NMOS transistor MN8, the tenth NMOS transistor MN9 and the drain electrode of the sixth NMOS transistor MN 5; the gate of the eighth NMOS transistor MN7 is used as the first negative input terminal Vinn1 of the comparison module, and the drain thereof is connected to the drain of the tenth NMOS transistor MN9 and the source of the twelfth NMOS transistor MN 11; the gate of the ninth NMOS transistor MN8 is used as the second positive input terminal Vinp1 of the comparison module, and the gate of the tenth NMOS transistor MN9 is used as the second negative input terminal Vinn2 of the comparison module; the grid electrode of the sixth NMOS transistor MN5 is connected with the grid electrodes of the fifth PMOS transistor MP4 and the eighth PMOS transistor MP7 and is connected with an external given clock signal clk, and the source electrode of the sixth NMOS transistor MN5 is connected with the power ground; the grid electrode of the sixth PMOS tube MP5 is connected with the drain electrodes of the seventh PMOS tube MP6, the eighth PMOS tube MP7 and the twelfth NMOS tube MN11, the grid electrode of the eleventh NMOS tube MN10 and the input end of the second inverter INV1, and the drain electrode thereof is connected with the fifth PMOS tube MP4 and the eleventh NMOS tubeThe drain electrode of MN10, the gates of the seventh PMOS transistor MP6 and the twelfth NMOS transistor MN11, and the input end of the first inverter INV0, the sources of which are connected with the sources of the fifth PMOS transistor MP4, the seventh PMOS transistor MP6 and the eighth PMOS transistor MP7 and connected with the power supply voltage V_DD(ii) a An output end of the first inverter INV0 is used as an output end of the comparing module.

The reference ground is a median voltage of the reference positive voltage Vrefp and the reference negative voltage Vrefn, the voltage value is not 0, the power ground is a power ground signal, and the voltage value is 0.

The preamplifier module can be used as a pre-operational amplifier in a quantization stage and can also be used as a residual error sampling operational amplifier in a residual error sampling stage, so that the reusability is improved. At the same time, the second-stage residual error integral capacitance is the second integral capacitance C_I2A first integrating capacitor C connected with the first stage_I1Namely, the isolation is complete, so that the size of the residual error sampling capacitor of the second stage is effectively reduced, the power consumption of the operational amplifier is reduced, and the speed is also improved. In addition, the passive integrator CIFF structure can realize noise transmission of

NTF(z)＝(1-a₁z^-1)·(1-a₂z^-1) (1)

The invention integrates the residual error after successive approximation twice, realizes the second-order shaping of the output result of the quantization noise, can realize the second-order noise shaping effect of zero points a1 and a2, and obviously improves the effective digit of the system. Wherein the zero points a1 and a2 satisfy

According to the invention, another CIFF feedback branch is introduced between the open-loop operational amplifier and the comparison module LATCH, so that second-order noise shaping is integrally realized, the invention can realize second-order noise shaping by using a double passive integrator, the noise of the open-loop operational amplifier can realize first-order shaping, low power consumption is realized, and high precision is realized at the same time.

In the SAR ADC having the single-ended capacitor array structure provided in this embodiment, the fourth NMOS transistor MN3 and the second NMOS transistor MN1 in the pre-operational amplifier module are connectedThe size ratio is set to the first integrating capacitor C in the first integrator module_I1Size of and capacitance array C of the capacitance DAC module_DACThe ratio of the total capacitance magnitude of (c); setting the size ratio of the tenth NMOS transistor MN9 to the seventh NMOS transistor MN6 in the comparison module as the second integrating capacitor C in the second integrator module_I2Is proportional to the size of the first sampling capacitor Cs of the second integrator block.

In the single-ended capacitor array structure proposed in this embodiment, the capacitor array C of the capacitor DAC module_DACA binary weighted capacitor array is employed for SAR-ADC operation. Setting a first integrating module and a first integrating capacitor C_I1Capacitor size and capacitor array C of capacitor DAC module_DACThe ratio of the total capacitance magnitude of (a) is g₁. Setting the second integrating capacitor C of the second integrator module_I2Is given by the ratio of the magnitude of the first sampling capacitance Cs of the second integrator block to the magnitude of the first sampling capacitance Cs of the second integrator block, is g₂The size ratio of the fifth NMOS transistor MN4 to the second NMOS transistor MN1 in the comparison module LATCH is also equal to g₂. Therefore g₁And g₂Satisfy the requirement of

The front-end operational amplifier module circuit is shown in fig. 4, wherein a second NMOS transistor MN1, a third NMOS transistor MN2, a fourth NMOS transistor MN3 and a fifth NMOS transistor MN4 are input transistors of the front-end operational amplifier, the second NMOS transistor MN1 and the third NMOS transistor MN2 are first input pair transistors with equal size, and the fourth NMOS transistor MN3 and the fifth NMOS transistor MN4 are second input pair transistors with equal size; the gate terminal of the second NMOS transistor MN1 is a first input positive terminal Vinp1 of the preamplifier module, and is connected with the upper plate of the capacitor array CDAC of the capacitor DAC module and the first reset switch S_R1And a first integrating switch S in the first integrator block_I1One end (input end of the first integrator block); the gate end of the third NMOS transistor MN2 is the first input negative end Vinn1 of the preamplifier module and is connected with the reference ground; the fourth NMOS tube MN3 is the second input positive end Vinp2 of the preamplifier module and is connected with the first integrator moduleThird reset switch S in block_R3And a fourth reset switch S_R4One end (output end of the first integrator module); the gate terminal of the fifth NMOS transistor MN4 is the second input negative terminal Vinn2 of the preamplifier module, and is connected to the ground reference. The size ratio of the fourth NMOS transistor MN3 to the second NMOS transistor MN1 is also equal to g₁. Considering that the input offset of the first input pair of the preamplifier module is Vos1, the gain is a, the input offset of the second input pair of the preamplifier module is Vos2, and the output positive terminal Vop of the preamplifier module (the output positive terminal Vop of the preamplifier module only used in the single-ended capacitor array is connected to the input terminal of the second integrator module, so the output positive terminal Vop of the preamplifier module is used as the output terminal of the preamplifier module, except that the output positive terminal Vop and the output positive terminal Von of the preamplifier module are respectively connected to the input terminals of the two second integrator modules in the double-ended capacitor array) satisfies the requirement that

V_op＝A·(V_inp1-V_inn1-V_os1+g₁·(V_inp2-V_inn2-V_os2)) (4)

The comparison module LATCH is a dynamic LATCH of the second-order noise shaping SAR-ADC with the novel CIFF structure, and has a comparison LATCH function, as shown in fig. 5, a circuit structure diagram of the comparison module is given, an input tube of the comparison module includes a seventh NMOS tube MN6, an eighth NMOS tube MN7, a ninth NMOS tube MN8 and a tenth NMOS tube MN9, the seventh NMOS tube MN6 and the eighth NMOS tube MN7 are first input pair tubes of the comparison module, and have equal sizes, and the ninth NMOS tube MN8 and the tenth NMOS tube MN9 are second input pair tubes of the comparison module, and have equal sizes; the gate terminal of the seventh NMOS transistor MN6 is the first positive input terminal Vinp1 of the comparison module LATCH, and is connected to one terminal of the first sampling capacitor Cs in the second integrator module and the second reset switch S_R2And a second integrating switch S_I2One end (first output end of second integrator module); the gate terminal of the eighth NMOS transistor MN7 is the first input negative terminal Vinn1 of the comparison module LATCH, and is connected to the reference ground; the gate end of the ninth NMOS transistor MN8 is the second input positive terminal Vinp2 of the comparison module LATCH, and is connected to the reference ground; the gate terminal of the tenth NMOS transistor MN9 is the comparison module LATCHA second negative input terminal Vinn2 connected to a second integrating capacitor C in the second integrator module_I2And a second integration switch S of a second integrator module_I2One terminal (second output terminal of the second integrator module). The size ratio of the tenth NMOS transistor MN9 to the seventh NMOS transistor MN6 is also equal to g₂. Considering the offset and noise of the comparison module LATCH as V_{N_LATCH}And the noise and the imbalance of the first input pair tube and the second input pair tube in the comparison module are included. When the quantization stage of the ADC system is finished, the voltage of the LATCH input end of the comparison module satisfies

V_inp1-g₂·V_inn2-(A·Q+V_{N_LATCH})＝0 (5)

Wherein Q is the quantization error of the ADC system.

The timing control of the novel CIFF structure second-order noise shaping SAR-ADC of the single-ended capacitor array structure proposed in this embodiment includes a sampling phase, a quantization phase, a residual sampling phase, a residual integration phase, and a reset phase, and its timing diagram is shown in fig. 6. Phi_SFirst control switch array S being a single-ended capacitor DAC module_DACAnd the phase of the connection input signal Vin; phi_R1First reset switch S being a single-ended capacitor DAC module_R1A closed phase; phi_CThe gate ends of an eighth PMOS tube MP7, a fifth PMOS tube MP4 and a sixth NMOS tube MN5 in the comparison module LATCH are connected and controlled for the phase of a clock signal clk of the comparison module LATCH; phi_R2For the second reset switch S in the second integrator module_R2A closed phase; phi_I1For the first integration switch S in the first integrator module_I1A closed phase; phi_I2For the second integration switch S in the second integrator module_I2A closed phase; phi_R3For the third reset switch S in the first integrator module_R3Closed phase and fourth reset switch S in the first integrator block_R3The phase of disconnection.

The timing analysis switch operation is started next, the timing diagram is shown in fig. 6, and the ADC system transfer function is inferred.

1) Sampling phase (start of sampling K-1). A first reset switch S_R1The closing process is carried out in a closed mode,the control switch array SDAC is connected with an input signal Vin, and after the input signal is established, the first reset switch S is connected_R1Open, control switch array SDAC connection Vrefn, the input signal is sampled into the capacitor array, so the upper plate voltage

V_DAC＝-Vin(K-1) (6)

2) And (5) a quantization stage. The control switch array S of the capacitor DAC module is controlled successively by comparing the output result of the LATCH module_DACAnd sequentially connecting the lower plates of the capacitor array with Vrefp or Vrefn until all the capacitors are switched. At the end of quantization the upper plate voltage, i.e. the residual is

V_res(K-1)＝V_DAC＝Dout(K-1)-Vin(K-1) (7)

3) And a residual error sampling stage. A second reset switch S_R2Closed and then opened. Then the residual signal in the residual sampling stage is amplified by the preamplifier and sampled onto the first sampling capacitor Cs, and equation (4) is satisfied, so that the voltage on the first sampling capacitor Cs is

4) A first stage residual integration stage. The first integral is switched on and off_I1Closed, capacitive array C_DACCharge on and a first integrating capacitance C_I1Is combined and redistributed, and S_I1Switching on and off until the next residual integration begins, C_I1Does not change, and C is the Kth quantization time based on the next quantization time_I1At a voltage of

In the Z domain is represented as

To obtain

5) And a second stage residual integration stage. A first reset switch S_R1And a third reset switch S_R3Closed, fourth reset switch S_R4Is turned off and then the second integrating switch S is switched on_I2Closed and opened again after the integration is finished. The residual is integrated into the capacitance C_I2In the above, the input terminal voltages of the preamplifier modules are all referenced to the ground, and the formula (4) is satisfied, and at this time, the output positive terminal of the preamplifier is

V_op＝A·(-V_os1+g₁·(-V_os2)) (11)

Second integral switch S_I2After closure, C_SCharge on and C_I2Is combined and redistributed, and S_I2Switching on and off until the next residual integration begins, C_I2Does not change, based on the time of next quantization, C_I2At a voltage of

By substituting V by equation (11) and equation (8)_opAnd

to obtain this time C_I2Voltage of

Converted into the Z domain and substituted into equation (10)

And introducing equation (3) to obtain the voltage of the second integrator:

this voltage is connected to the negative second input terminal Vinn2 of the comparison module LATCH.

6) A reset phase. A second reset switch S_R2Closed and then opened, capacitor C_SThe charge on is reset and the offset voltage of the operational amplifier is stored by the capacitor C according to equation (11)_SIn the above, the preamplification offset is eliminated in the next quantization.

7) And entering the K sampling quantization. The operation is the same as step 1), the voltage of the upper polar plate meets the requirement

V_DAC＝-Vin(K) (15)

Then quantization is entered. At the end of the quantization, the voltage at the first positive input Vinp1 of the comparison module LATCH is

When the quantization is finished, the quantization error and the input voltage of the comparator satisfy the formula (5), the formulas (3), (9), (16) and (13) are substituted and converted into a Z domain, and the relation between the output signal Dout and the input voltage Vin, the quantization noise Q and the offset of the comparison module LATCH and the noise VN _ LATCH is obtained as follows:

the noise transfer function of the system can be obtained as

According to the above analysis, the SAR ADC having the single-ended capacitor array structure provided in this embodiment adopts a CIFF structure to implement second-order noise shaping, where offset storage may be performed on the preamplifier, so as to eliminate the influence of offset, and second-order noise shaping may also be implemented on the noise of the comparison module LATCH. Fig. 7 simulates an output frequency spectrum diagram of the second-order noise shaping SAR-ADC circuit of the CIFF structure of this embodiment, based on an 8-bit binary capacitance-weight capacitance DAC array, the oversampling rate is 8, and the effective number of output bits filtered by a digital filter is 13.76 bits.

The second-order noise shaping successive approximation analog-to-digital converter provided by the invention is also suitable for a double-end capacitor array structure, as shown in fig. 8, compared with the SAR ADC with a single-end capacitor array structure, the capacitor DAC module in the SAR ADC with the double-end capacitor array structure is a double-end capacitor DAC module, the double-end capacitor DAC module is two single-end capacitor DAC module structures and comprises a second capacitor array, a second control switch array, a fifth reset switch, a third capacitor array, a third control switch array and a sixth reset switch, one end of each switch in the second control switch array is connected with a forward input signal VIP, a reference positive voltage Vrefp or a reference negative voltage Vrefn, and the other end of each switch is connected with a forward output end of the double-end capacitor DAC module after passing through a corresponding capacitor in the second capacitor array; the fifth reset switch is connected between the forward output end of the double-end capacitor DAC module and the reference ground; one end of each switch in the third control switch array is connected with a negative input signal VIN, a reference positive voltage Vrefp or a reference negative voltage Vrefn, and the other end of each switch is connected with a negative output end of the double-end capacitor DAC module after passing through a corresponding capacitor in the third capacitor array; and the sixth reset switch is connected between the negative output end of the double-end capacitor DAC module and the reference ground.

For the SAR ADC with the double-end capacitor array structure, the number of the corresponding first integrator modules and the number of the corresponding second integrator modules are two, the two first integrator modules are respectively connected with the positive output end and the negative output end of the double-end capacitor DAC module, and the two second integrator modules are respectively connected with the positive output end and the negative output end of the preamplifier module. The preamplifier module in the double-end structure comprises a positive output end and a negative output end, the positive output end is connected with the input end of the first second integrator module, the negative output end is connected with the input end of the second integrator module, and the negative output end is connected with the input end of the second integrator module. The first positive input end of the comparison module is connected with the first output end of the first second integrator module, the second negative input end of the comparison module is connected with the second output end of the first second integrator module, the first negative input end of the comparison module in the double-ended structure is connected with the first output end of the second integrator module, the second positive input end of the comparison module in the double-ended structure is connected with the second output end of the second integrator module, the output end of the comparison module in the double-ended structure comprises a positive output end and a negative output end, and the positive output end and the negative output end are both connected to the SAR Logic.

In the SAR ADC with the double-ended structure, the preamplifier module and the comparison module may also adopt the structures shown in fig. 4 and 5, and the difference from the single-ended structure is that the preamplifier module uses the drain terminal of the second NMOS transistor MN1 as the positive output terminal of the preamplifier module, the drain terminal of the third NMOS transistor MN2 as the negative output terminal of the preamplifier module, and in the comparison module, the output terminal of the first inverter INV0 as the positive output terminal of the comparison module, and the output terminal of the second inverter INV1 as the negative output terminal of the comparison module. The principle and operation of the double-ended structure are similar to the single-ended structure and will not be described herein.

Although the circuit structure of the second-order noise-shaping SAR-ADC according to the present invention has been disclosed by way of example, it is not intended to limit the present invention, and those skilled in the art may make insubstantial changes or modifications without departing from the spirit of the present invention.

Claims

1. A second-order noise-shaping successive approximation analog-to-digital converter comprises a single-end capacitor DAC module, a comparison module and a successive approximation logic module,

characterized in that the successive approximation analog-to-digital converter further comprises a first integrator module, a preamplifier module and a second integrator module,

2. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, wherein the preamplifier module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein the second NMOS transistor and the third NMOS transistor are equal in size, the fourth NMOS transistor and the fifth NMOS transistor are equal in size, and the size ratio of the fourth NMOS transistor to the second NMOS transistor is equal to the ratio of the capacitance value of the first integrating capacitor to the total capacitance value of the first capacitor array in the single-ended capacitor DAC module;

3. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1 or 2, wherein the comparison module comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first inverter and a second inverter, wherein the seventh NMOS transistor and the eighth NMOS transistor have the same size, the ninth NMOS transistor and the tenth NMOS transistor have the same size, and the size ratio of the tenth NMOS transistor and the seventh NMOS transistor is equal to the ratio of the capacitance value of the second integration capacitor and the capacitance value of the first sampling capacitor;

4. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 1, wherein the reference ground is a median voltage of the reference positive voltage and the reference negative voltage.

5. A second-order noise-shaping successive approximation analog-to-digital converter comprises a double-end capacitor DAC module, a comparison module and a successive approximation logic module,

characterized in that the successive approximation analog-to-digital converter further comprises a preamplifier module, two first integrator modules and two second integrator modules,

6. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 5, wherein the preamplifier module comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor, wherein the second NMOS transistor and the third NMOS transistor are equal in size, the fourth NMOS transistor and the fifth NMOS transistor are equal in size, and the size ratio of the fourth NMOS transistor to the second NMOS transistor is equal to the ratio of the capacitance value of the first integrating capacitor to the total capacitance value of the second capacitor array or the third capacitor array in the double-end capacitor DAC module;

7. The second-order noise-shaping successive approximation analog-to-digital converter according to claim 5 or 6, wherein the comparison module comprises a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first inverter and a second inverter, wherein the seventh NMOS transistor and the eighth NMOS transistor are equal in size, the ninth NMOS transistor and the tenth NMOS transistor are equal in size, and the size ratio of the tenth NMOS transistor and the seventh NMOS transistor is equal to the ratio of the capacitance value of the second integration capacitor and the capacitance value of the first sampling capacitor;