CN110190853B - First-order modulator based on static pre-amplifier integrator - Google Patents

Abstract

The invention discloses a first-order modulator based on a static pre-amplifier integrator, including: a static pre-amplifier integrator, a four-input differential comparator, two DAC capacitor arrays, and a binary counter with a modulus of N, wherein the input The differential signal is connected to the input terminal of the static preamplifier integrator, and the output terminal is connected to the two inverting input terminals of the differential comparator; the two output terminals of the differential comparator are respectively connected to the input terminal of the counter and the input of the two DAC capacitor arrays The output terminals of the two DAC capacitor arrays are respectively processed with the input differential signal and connected to the two positive input terminals of the differential comparator; the output terminal of the counter is used as the output of the entire modulator. The present invention saves the integral operation, saves most of the power consumption brought by the integrator, and greatly accelerates the establishment speed of the comparator; to a certain extent, it reduces the misjudgment caused by the metastable state of the comparator, and improves the efficiency of the entire modulator. effective number of bits to achieve ADC performance with Nyquist bandwidth.

Description

A First Order Modulator Based on Static Preamp Integrator

technical field

The invention relates to a first-order modulator based on a static preamp integrator, belonging to the technical field of integrated circuits.

Background technique

With the rapid development of semiconductor technology, high-speed and high-precision analog-to-digital converters have been widely used in digital communications, military radar and other fields. Successive approximation analog-to-digital converter (SAR ADC), as one of the current mainstream ADC products, can well balance the requirements of speed and power consumption after deep submicron. In the successive approximation analog-to-digital converter, due to the limitation of capacitance mismatch and KT/C noise, it is difficult to achieve very high precision requirements after the ADC precision is greater than 12Bit, and irrational factors also limit the speed of the ADC. Since 2009, the hybrid SAR structure has gradually become a research hotspot for high-speed and high-precision ADCs, such as hybrid pipeline-SAR, flash-SAR, etc. In many hybrid structures, when the accuracy reaches 14Bit or more, it will be greatly affected by various non-ideal factors such as quantization noise, comparator noise, comparator offset, operational amplifier offset, DAC capacitor array mismatch, and power supply ripple. Therefore, the effective number of bits (ENOB) is generally 2 to 3 Bit lower than the precision.

In order to achieve better suppression of noise, noise-shaping SAR has become the preferred structure. A common local noise-shaping SAR ADC workflow diagram is shown in Figure 1. The SAR ADC firstly performs rough quantization on the input signal, and at the same time generates a high-bit digital output code, and sends the margin Vres to the noise shaping loop. The sampling data X of this structure is converted into a digital signal Y by the ADC after passing through the processing module A(z). In order to close the loop, the converted digital signal must be converted into an analog signal through a DAC, and then fed back to the input terminal through a module B(z) to make a difference with the margin Vres. In the first-order linear model, considering that there is a quantization error ε in the output Y of the ADC module, the structure can be obtained to satisfy the following relationship:

[V _res -Y·B(z)]A(z)+ε=Y (1)

Solutions have to:

The above shows that the margin Vres and the quantization noise ε respectively pass through two different transfer functions:

Y＝V _res S(z)+ε N(z) (3)

where S(z) is the signal transfer function, N(z) is the noise transfer function, in order to implement a low-pass data converter and maintain effective noise shaping, S(z) is the low-pass filter characteristic, N(z) is the high-pass characteristic. If B(z)=1, it is required that A(z) must have the form of an integrator to obtain the desired response.

However, this hybrid SAR ADC based on noise shaping also has some deficiencies, because the shaping of each margin is not only for a single margin, but for the previous (k-1) or The last (k-2) margins are operated simultaneously, so the bandwidth of the entire noise-shaping SAR ADC is determined by the bandwidth of the noise-shaping loop. Since noise shaping generally uses oversampling and an integrator with low-pass filtering characteristics to achieve noise shaping, the actual signal bandwidth is <Nyquist bandwidth, thus limiting the performance of the overall ADC. At the same time, since the voltage integrated by the integrator is a small amount each time, the requirements for offset, noise, and speed of the comparator are particularly high, and it is easily affected by PVT changes.

Contents of the invention

The technical problem to be solved by the present invention is to provide a first-order modulator based on a static pre-amplifier integrator in order to suppress noise while achieving Nyquist bandwidth performance, while taking into account high-speed and low-power application scenarios need.

The present invention specifically adopts the following technical solutions to solve the above technical problems:

A first-order modulator based on a static preamplifier integrator, including: a static preamplifier integrator, a four-input differential comparator, two DAC capacitor arrays, and a binary counter with a modulus of N, wherein the input differential signal is connected to a static The input terminal of the preamplifier, and the output terminal of the static preamplifier is connected to the two inverting input terminals of the differential comparator; the two output terminals of the differential comparator are respectively connected to the input terminal of the counter and two DAC capacitor arrays The input terminals of the two DAC capacitor arrays are connected to the two positive input terminals of the differential comparator after the output terminals of the two DAC capacitor arrays are respectively processed with the input differential signal; and the output terminal of the counter is used as the output terminal of the whole modulator.

Further, as a preferred technical solution of the present invention, the static preamplifier integrator is composed of a preamplifier stage and an output stage.

及其源极接电源电压VDD。Further, as a preferred technical solution of the present invention, the pre-amplification stage in the static pre-amplifier integrator includes: a complementary input NMOS pair composed of NMOS transistors M1 and M2, and a PMOS pair composed of PMOS transistors M3 and M4 Tube, a clock control tube composed of NMOS tube M5 and PMOS tube M6, wherein the clock control signal CLK is connected to the gate of NMOS tube M5, the source of NMOS tube M5 is grounded and its drain is connected to the source of NMOS tubes M1 and M2 respectively The gate of the NMOS transistor M1 is connected to the input signal Vip, and its drain is connected to the drain of the PMOS transistor M3; the gate of the NMOS transistor M2 is connected to the input signal Vin, and its drain is connected to the drain of the PMOS transistor M4; The gate of M3 is connected to the input signal Vip, and its source is connected to the drain of the PMOS transistor M6; the gate of the PMOS transistor M4 is connected to the input signal Vin, and its source is connected to the drain of the PMOS transistor M6; the gate of the PMOS transistor M6 pole connection clock control signal

Its source is connected to the power supply voltage VDD.

分别连接PMOS管M10、M11的栅极，且PMOS管M10的漏极连接静态预放积分器的输出端Vop，其源极连接PMOS管M12的漏极，PMOS管M11的漏极连接静态预放积分器的输出端Von，其源极连接PMOS管M13的漏极；PMOS管的源极和PMOS管M13的源极接电源电压VDD。Further, as a preferred technical solution of the present invention, the output stage in the static preamplifier integrator includes: a common-gate input pair transistor composed of NMOS transistors M7 and M8, a reset transistor M9, an integrating capacitor Cint, and a common-mode feedback Capacitors C1 and C2, a clock control tube composed of PMOS transistors M10 and M11, and a current tube composed of PMOS transistors M12 and M13, wherein the clock control signal CLK is connected to the gates of NMOS transistors M7 and M8, and the sources of NMOS transistors M7 and M8 The poles are respectively connected to the pre-amplification stage, and the drain of the NMOS transistor M7 is connected to the output terminal Vop of the static preamplifier integrator, and the drain of the NMOS transistor M8 is connected to the output terminal Von of the static preamplifier integrator; the gate of the reset transistor M9 is connected to Reset signal Reset, and its source and drain are respectively connected to the output terminals Von and Vop of the static pre-amplifier integrator; the two ends of the integrating capacitor Cint are respectively connected to the output terminals Von and Vop of the static pre-amplifier integrator; the common-mode feedback capacitor C1 and After C2 is short-circuited, both ends are respectively connected to the output terminals Von and Vop of the static pre-amplifier integrator, and they are connected to the gates of NMOS transistors M12 and M13 after short-circuiting; the clock control signal

The gates of the PMOS transistors M10 and M11 are connected respectively, and the drain of the PMOS transistor M10 is connected to the output terminal Vop of the static preamplifier integrator, its source is connected to the drain of the PMOS transistor M12, and the drain of the PMOS transistor M11 is connected to the static preamplifier The source of the output terminal Von of the integrator is connected to the drain of the PMOS transistor M13; the source of the PMOS transistor and the source of the PMOS transistor M13 are connected to the power supply voltage VDD.

The present invention adopts above-mentioned technical scheme, can produce following technical effect:

The first-order modulator based on the pre-amplifier integrator of the present invention only needs one integration operation and 2 ^N times of voltage comparison operations to complete each conversion, so compared with traditional first-order modulators, it needs 2 ^N times of integration operations and 2 ^N times The voltage comparison operation saves 2 ^N -1 integration operations and saves most of the power consumption brought by the integrator; at the same time, because the static open-loop integrator amplifies the input voltage signal by 2 ^N times, it greatly speeds up the comparator Establishment speed; at the same time, it also reduces the "misjudgment" caused by the metastable state of the comparator to a certain extent, thereby increasing the effective number of bits of the entire modulator; in addition, due to local oversampling, and repeated comparisons of the same margin Quantization can realize the ADC performance of the Nyquist bandwidth, so when the modulator is used in a hybrid ADC, it does not limit the bandwidth of the ADC, so that the ADC can realize the normal Nyquist signal bandwidth.

Description of drawings

Figure 1 is an equivalent block diagram of a traditional first-order noise shaping sigma-delta ADC.

FIG. 2 is a schematic diagram of the first-order modulator ISDM based on the pre-amplifier integrator of the present invention.

Fig. 3 is a circuit diagram of a static pre-amplification integrator in an embodiment of the present invention.

Fig. 4 is a system clock diagram of the ISDM modulator in the embodiment of the present invention.

Fig. 5 is a simulation waveform diagram of the input and output of the pre-amplifier integrator in the embodiment of the present invention.

FIG. 6 is a simulation waveform diagram for a certain input signal in the embodiment of the present invention.

Fig. 7 is a comparison diagram of the effective number of digits of the ISDM combined with the SAR ADC of the present invention and the traditional ADC with the change of the comparator noise.

Detailed ways

Embodiments of the present invention will be described below in conjunction with the accompanying drawings.

As shown in Fig. 2, the present invention has designed a kind of first-order modulator ISDM based on the static preamplifier integrator, mainly includes: a static preamplifier integrator Int, a four-input differential comparator, two DAC capacitor arrays DAC_N, A binary counter with a modulus of N, in which the input differential signals Vip and Vin are connected to the input terminals of the static pre-amplifier integrator, and the output terminals of the static pre-amplifier integrator are connected to the two inverting input terminals of the differential comparator; the differential comparator The two output terminals of the counter are respectively connected to the input terminals of the counter and the input terminals of the two DAC capacitor arrays; the output terminals of the two DAC capacitor arrays are connected to the differential comparator after the summing node operation processing and the input differential signals Vip and Vin respectively The two positive inputs; and, the output of the counter as the output of the entire modulator.

As shown in FIG. 3 , it is a circuit diagram of a static pre-amplification integrator in an embodiment of the present invention, and the static pre-amplification integrator is composed of a pre-amplification stage and an output stage.

及其源极接电源电压VDD。Specifically, the pre-amplification stage in the static pre-amplifier integrator includes: a complementary input NMOS pair consisting of NMOS transistors M1 and M2, a PMOS pair consisting of PMOS transistors M3 and M4, an NMOS transistor M5, and a PMOS transistor M6. The clock control tube composed of clock control signal CLK is connected to the gate of NMOS transistor M5, the source of NMOS transistor M5 is grounded to GND and its drain is connected to the sources of NMOS transistors M1 and M2 respectively; the gate of NMOS transistor M1 is connected to The input signal Vip, and its drain is connected to the drain of the PMOS transistor M3; the gate of the NMOS transistor M2 is connected to the input signal Vin, and its drain is connected to the drain of the PMOS transistor M4; the gate of the PMOS transistor M3 is connected to the input signal Vip, And its source is connected to the drain of the PMOS transistor M6; the gate of the PMOS transistor M4 is connected to the input signal Vin, and its source is connected to the drain of the PMOS transistor M6; the gate of the PMOS transistor M6 is connected to the clock control signal

Its source is connected to the power supply voltage VDD.

分别连接PMOS管M10、M11的栅极，且PMOS管M10的漏极连接静态预放积分器的输出端Vop，其源极连接PMOS管M12的漏极，PMOS管M11的漏极连接静态预放积分器的输出端Von，其源极连接PMOS管M13的漏极；PMOS管M12的源极和PMOS管M13的源极接电源电压VDD。Specifically, the output stage in the static pre-amplifier integrator includes: a common-gate input pair consisting of NMOS transistors M7 and M8, a reset transistor M9, an integrating capacitor Cint, common-mode feedback capacitors C1 and C2, and a PMOS transistor M10, The clock control tube composed of M11 and the current tube composed of PMOS tubes M12 and M13, wherein the clock control signal CLK is connected to the gates of NMOS tubes M7 and M8, and the source of NMOS tube M7 is connected to the drain of NMOS tube M1 in the pre-amplification stage The source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M2 in the pre-amplification stage, and the drain of the NMOS transistor M7 is connected to the output terminal Vop of the static preamplifier integrator, and the drain of the NMOS transistor M8 is connected to the static preamplifier The output terminal Von of the integrator; the gate of the reset transistor M9 is connected to the reset signal Reset, and its source and drain are respectively connected to the output terminals Von and Vop of the static preamplifier integrator; the two ends of the integrating capacitor Cint are respectively connected to the static preamplifier integral The output terminals Von and Vop of the device; the common-mode feedback capacitors C1 and C2 are short-circuited to obtain a short-circuit point, and after short-circuiting, the two ends of the common-mode feedback capacitors C1 and C2 are respectively connected to the output terminals Von and Vop of the static pre-amplifier integrator , and the short-circuit point is also connected to the gates of PMOS transistors M12 and M13; the clock control signal

The gates of the PMOS transistors M10 and M11 are connected respectively, and the drain of the PMOS transistor M10 is connected to the output terminal Vop of the static preamplifier integrator, its source is connected to the drain of the PMOS transistor M12, and the drain of the PMOS transistor M11 is connected to the static preamplifier The source of the output terminal Von of the integrator is connected to the drain of the PMOS transistor M13; the source of the PMOS transistor M12 and the source of the PMOS transistor M13 are connected to the power supply voltage VDD.

The differential comparator is composed of four input ports Vxp, Vxn, Vyp, and Vyn, wherein Vxp is obtained by summing the input signal Vip and the output signal of a DAC capacitor array DAC_P; Vxn is obtained by summing the input signal Vin and another DAC The output signal of the capacitor array DAC_N is obtained by summing; Vyp and Vyn are respectively connected to the output ports Vop and Von of the static preamplifier integrator. The comparator has two output ports Dout+ and Dout-, where Dout+ is connected to one input terminal of the binary counter and the input terminal of a DAC capacitor array DAC_P; Dout- is connected to one input terminal of the binary counter and the input terminal of another DAC capacitor array DAC_N . The two input terminals of the binary counter Counter are respectively connected to the output terminals Dout+ and Dout-, and the output terminal of the binary counter Counter is an NBit binary stream signal.

Based on the circuit structure of the above-mentioned static pre-amplifier integrator, based on the clock diagram shown in Figure 4, its working process is specifically:

NMOS管M5、M6、M10、M11同时导通，输入信号Vip、Vin分别经过互补输入对管M1、M2、M3、M4被放大，放大都得信号通过NMOS管M7、M8对输出节点的积分电容Cint进行充电，C1、C2作为工模反馈电容，其短接点随着输出节点充电逐渐上升，当该点电压上升到等于VDD-|V_thp|时，NMOS管M12、M13截止，其中，|V_thp|表示PMOS管的阈值电压，积分时间结束，充电的时间就是CLK高电平持续时间Tint。(1) When the clock control signal CLK=1, the clock control signal

NMOS tubes M5, M6, M10, and M11 are turned on at the same time, and the input signals Vip and Vin are amplified through complementary input pair tubes M1, M2, M3, and M4 respectively, and the amplified signals pass through the integral capacitance of the NMOS tubes M7 and M8 on the output node Cint is charged, and C1 and C2 are used as the feedback capacitors of the working model. The short-circuit point gradually rises with the charging of the output node. When the voltage at this point rises to equal to VDD-|V _thp |, the NMOS transistors M12 and M13 are turned off, where |V _thp |Indicates the threshold voltage of the PMOS tube, the integration time is over, and the charging time is the CLK high level duration Tint.

NMOS管M5、M6、M10、M11同时截止，输出节点电压差保持在积分电容Cint上。(2) When the clock control signal CLK=0, the clock control signal

The NMOS transistors M5, M6, M10, and M11 are cut off at the same time, and the output node voltage difference remains on the integrating capacitor Cint.

(3) When the reset signal Reset=1, the output node is reset to the output common-mode voltage, the voltage difference between the two ends of the integrating capacitor Cint becomes 0, and the integrator completes a complete working process.

The working principle of the ISDM modulator in the embodiment of the present invention is based on the clock diagram as shown in Figure 4, and specifically includes the following processes:

为低电平时，积分器对输入信号进行积分放大，积分时间与积分器增益由CLK高电平持续时间决定。(1) When the reset signal Reset=1, the entire modulator is reset. When the clock control signal CLK is high level, the clock control signal

When it is low level, the integrator performs integral amplification on the input signal, and the integration time and integrator gain are determined by the duration of CLK high level.

为高电平时，电路进入循环比较状态，在每个比较时钟CMP＝1时，比较器比较此时输入信号Vip-Vin的差值与积分信号Vyp-Vyn之间的大小关系：(2) When the clock control signal CLK is low level, the clock control signal

When it is high level, the circuit enters the cyclic comparison state. When each comparison clock CMP=1, the comparator compares the difference between the input signal Vip-Vin and the integral signal Vyp-Vyn at this time:

If Vip-Vin<Vyp-Vyn is satisfied, then Dout+=1, Dout-=0, and the counter increases by 1;

If Vip-Vin>Vyp-Vyn is satisfied, Dout+=0, Dout-=1, and the counter is decremented by 1.

The DAC generates a voltage signal related to Dout+, Dout- and feeds it back to the input summing node and makes a difference with the input signal. The positive or negative of the generated voltage depends on Dout+, Dout- equal to 1 or 0. In this stage, the output voltage of the integrator remains on the integral capacitor Cint until the last comparison cycle ends, and Cint is reset again. Finally, according to the counting result of the counter, the amplitude of the plate voltage signal on the DAC capacitor array of the ADC can be known, that is, the input terminal of the comparator is:

In the formula, Dout+, Dout- are the output results of each comparison of the comparator, N represents the number of comparisons, generally N=2 ⁿ , n is the ADC precision, V _ref (i) is the reference voltage generated by each DAC, if it is a first-order Incremental modulation, then V _ref is a constant value.

The pre-amplifier integrator of the present invention is simulated, and its input and output waveforms are shown in FIG. 5 . It can be seen from Fig. 5 that the integrator can pre-amplify the input differential signal with a gain of 8.1 times. The present invention carries out behavioral simulation for a 3Bit first-order incremental modulator, and the required integrator gain is about 8 times. For an input differential small signal, the integrated signals Vyp, Vyn and the comparator input terminal signals Vxp, Vxn follow the The change of the number of comparisons is shown in Figure 6. In the case shown in Figure 6, the output digital code of the comparator is: 11111111.

For the performance test of the hybrid ISDM-SAR ADC, 9Bit SAR+2Bit ISDM (11Bit precision) was selected for comparative testing with the SAR ADC with 11Bit. In the test, the same comparator input noise was added to the two comparators at the same time, and the ADC Effective digits, as shown in Figure 7. It can be seen from FIG. 7 that the hybrid ISDM-SAR ADC has a better noise suppression effect, so the present invention has certain application value.

In summary, the present invention only needs one integration operation and 2 ^N voltage comparison operations to complete each conversion, so compared with the traditional first-order modulator, it saves 2 ^N -1 integration operations and saves most of the integrator’s cost. At the same time, because the static open-loop integrator amplifies the input voltage signal by 2 ^N times, the establishment speed of the comparator is greatly accelerated; at the same time, the misjudgment caused by the metastable state of the comparator is also reduced to a certain extent, thus The effective number of bits of the entire modulator is improved; in addition, due to local oversampling and repeated comparison and quantization of the same margin, the ADC performance of the Nyquist bandwidth can be achieved.

The embodiments of the present invention have been described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and can also be made without departing from the gist of the present invention within the scope of knowledge possessed by those of ordinary skill in the art. Variations.

Claims (4)

1. A first order modulator based on a static pre-amp integrator, comprising: the digital-to-analog converter comprises a static open-loop pre-amplifier integrator, a four-input differential comparator, two DAC capacitor arrays and a binary counter with the modulus of N, wherein an input differential signal is connected with the input end of the static pre-amplifier integrator, and the output end of the static pre-amplifier integrator is connected with two reverse input ends of the differential comparator; two output ends of the differential comparator are respectively connected with the input end of the counter and the input ends of the two DAC capacitor arrays; the output ends of the two DAC capacitor arrays are respectively connected to two positive input ends of the differential comparator after being subjected to operation processing with the input differential signals; and the output end of the counter is used as the output end of the whole modulator.

2. A first order modulator based on a static open-loop pre-amplifier integrator as claimed in claim 1, characterized in that the static open-loop pre-amplifier integrator consists of a pre-amplifier stage and an output stage.

3. The static pre-amplifier integrator-based first order modulator of claim 2, wherein the pre-amplifier stage in the static open-loop pre-amplifier integrator comprises: the clock control circuit comprises complementary input NMOS paired transistors consisting of NMOS transistors M1 and M2, PMOS paired transistors consisting of PMOS transistors M3 and M4, and a clock control transistor consisting of an NMOS transistor M5 and a PMOS transistor M6, wherein a clock control signal CLK is connected with a grid electrode of the NMOS transistor M5, a source electrode of the NMOS transistor M5 is grounded, and a drain electrode of the NMOS transistor M5 is respectively connected with source electrodes of the NMOS transistors M1 and M2; the grid electrode of the NMOS tube M1 is connected with an input signal Vip, and the drain electrode of the NMOS tube M1 is connected with the drain electrode of the PMOS tube M3; the grid electrode of the NMOS tube M2 is connected with an input signal Vin, and the drain electrode of the NMOS tube M2 is connected with the drain electrode of the PMOS tube M4; the grid of the PMOS tube M3 is connected with an input signal Vip, and the source electrode of the PMOS tube M3 is connected with PMOSA drain of tube M6; the grid electrode of the PMOS tube M4 is connected with the input signal Vin, and the source electrode of the PMOS tube M4 is connected with the drain electrode of the PMOS tube M6; grid electrode connection clock control signal of PMOS (P-channel metal oxide semiconductor) transistor M6

And its source is connected to the supply voltage VDD.

4. The static pre-amplifier integrator-based first order modulator of claim 1, wherein the output stage of the static open-loop pre-amplifier integrator comprises: the amplifier comprises a common-gate input geminate transistor consisting of NMOS transistors M7 and M8, a reset transistor M9, an integral capacitor Cint, common-mode feedback capacitors C1 and C2, a clock control transistor consisting of a PMOS transistor M10 and a PMOS transistor M11, and a current transistor consisting of a PMOS transistor M12 and a PMOS transistor M13, wherein a clock control signal CLK is connected with the grids of the NMOS transistors M7 and M8, the sources of the NMOS transistors M7 and M8 are respectively connected to a pre-amplification stage, the drain of the NMOS transistor M7 is connected with the output end Vop of a static pre-amplification integrator, and the drain of the NMOS transistor M8 is connected with the output end Von of the static pre-amplification integrator; the grid electrode of the Reset tube M9 is connected with a Reset signal Reset, and the source electrode and the drain electrode of the Reset tube M9 are respectively connected with the output ends Von and Vop of the static preamplification integrator; two ends of the integrating capacitor Cint are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator; after short circuit, two ends of the common mode feedback capacitors C1 and C2 are respectively connected with the output ends Von and Vop of the static pre-amplifier integrator, and after short circuit, the common mode feedback capacitors are connected with the grid electrodes of the PMOS tubes M12 and M13; clock control signal

The grid electrodes of the PMOS tubes M10 and M11 are respectively connected, the drain electrode of the PMOS tube M10 is connected with the output end Vop of the static preamplification integrator, the source electrode of the PMOS tube M10 is connected with the drain electrode of the PMOS tube M12, the drain electrode of the PMOS tube M11 is connected with the output end Von of the static preamplification integrator, and the source electrode of the PMOS tube M13 is connected with the drain electrode of the PMOS tube M13; the source electrode of the PMOS tube M12 and the source electrode of the PMOS tube M13 are connected with the power voltage VDD.

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