CN109302185A - A kind of cyclic analog-to-digital converters and its conversion method being multiplexed operational amplifier - Google Patents
A kind of cyclic analog-to-digital converters and its conversion method being multiplexed operational amplifier Download PDFInfo
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- CN109302185A CN109302185A CN201811267845.1A CN201811267845A CN109302185A CN 109302185 A CN109302185 A CN 109302185A CN 201811267845 A CN201811267845 A CN 201811267845A CN 109302185 A CN109302185 A CN 109302185A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
- H03M1/1285—Synchronous circular sampling, i.e. using undersampling of periodic input signals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
Abstract
The invention discloses a kind of cyclic analog-to-digital converters for being multiplexed operational amplifier, first residue multi-gain amplification unit and the second surplus multi-gain amplification unit share an operational amplifier.In half period, first residue multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier；Second surplus multi-gain amplification unit carries out surplus gain using operational amplifier and amplifies operation；In adjacent other half period, first residue multi-gain amplification unit carries out surplus gain amplification using operational amplifier, and the second surplus multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier.A kind of cyclic analog-to-digital converters and its D conversion method being multiplexed operational amplifier provided by the invention, enable to the conversion rate of analog-digital converter to double, while also reducing power consumption.
Description
Technical field
The invention belongs to semiconductor integrated circuit design fields, and in particular to a kind of circulation pattern for being multiplexed operational amplifier
Number converter and its conversion method.
Background technique
Analog-digital converter mainly includes single slope analog-to-digital converter, gradual approaching A/D converter and circular form modulus
Converter.Although single slope analog-to-digital converter has the preferable linearity, it is difficult to meet high-speed a/d conversion and height simultaneously
The requirement of gray level resolution.Because if resolution ratio will increase M bit, clock periodicity required for it is counted must increase to 2M -1Times；Even if usually shortening conversion time by increasing clock frequency, which is still difficult to realize high-speed transitions.Gradually force
Plesiotype analog-digital converter is generally turned using the modulus of 8 or 9bit in practical application since the characteristic of its low-power consumption is widely used
Parallel operation；However gradual approaching A/D converter needs the very high internal Digital To Analog converter of a precision, and passes in image
10bit relatively difficult to achieve and higher resolution on the column of sensor.Cyclic analog-to-digital converters can in small area implementation high-resolution,
And the thought based on flow-line modulus converter, higher conversion ratio may be implemented.
An operational amplifier is required in existing cyclicity analog-digital converter in each margin gain amplifying circuit
For amplifying, i.e., half period is kept, and lower half period realizes operation amplifier, when so generating 1bit needs one
The time in clock period, and operational amplifier has the time of half to be in idle state, reduces turning for cyclic analog-to-digital converters
Throw-over rate, this traditional cyclic analog-to-digital converters structure are no longer satisfied the application of high gray resolution image and high frame per second.
In particular with the raising of pixel resolution and frame per second, the pixel rate of CIS is also gradually increased in most of applications.In order to realize
High pixel rate, while the performance of low noise is kept, high-resolution analog-digital converter is at the key for meeting these performance requirements
Factor.
Summary of the invention
Technical problem to be solved by the invention is to provide it is a kind of be multiplexed operational amplifier cyclic analog-to-digital converters and
Its conversion method enables to the conversion rate of cyclic analog-to-digital converters to double, while also reducing power consumption.
To achieve the goals above, the present invention adopts the following technical scheme: a kind of circulation pattern for being multiplexed operational amplifier
Number converter, including the first sub- ADC unit, the second sub- ADC unit, the first logic unit, the second logic unit, first residue increase
Beneficial amplifying unit, the second surplus multi-gain amplification unit and digital calibration unit, wherein the output end of the first sub- ADC unit
Simultaneous connection word calibration unit and the first logic unit, the output end of first logic unit connect the first residue and increase
The output end of the input terminal of beneficial amplifying unit, the first residue multi-gain amplification unit connects the first sub- ADC unit；It is described
The output end simultaneous connection word calibration unit and the second logic unit of second sub- ADC unit, second logic unit it is defeated
Outlet connects the input terminal of the second surplus multi-gain amplification unit, the output end connection of the second surplus multi-gain amplification unit
The second sub- ADC unit；
The first residue multi-gain amplification unit and the second surplus multi-gain amplification unit share an operational amplifier.Half
In a period, first residue multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier；Second surplus multi-gain amplification unit
Surplus gain is carried out using operational amplifier and amplifies operation；In adjacent other half period, first residue gain amplification is single
Member carries out surplus gain amplification using operational amplifier, and the second surplus multi-gain amplification unit carries out sampling holding, puts without operation
Big device.
Further, the first residue multi-gain amplification unit and the second surplus multi-gain amplification unit include: capacitor C1, electricity
Hold C2, capacitor C3, capacitor C1 ', capacitor C2 ', capacitor C3 ' and operational amplifier；
Wherein, input terminal VinIt is connected to N1 node by switch S1, N1 node is connected to described more than second by switch S2
Flow gain amplifying unit output end Vout, N1 node pass through switch S31 connection capacitor C1A left side it is extreme, N1 node passes through switch S32
Connect capacitor C2A left side it is extreme, N1 node passes through switch S34 connection capacitor C3A left side it is extreme；Capacitor C1, capacitor C2With capacitor C3's
It is right extremely to connect N4 node, signal V simultaneouslyrefpN2 node, signal V are connected to by switch S11refnIt is connected to by switch S13
N3 node, by switch S12 connection between N2 node and N3 node, N2 node is connected to capacitor C by switch S332Left pole
End, N3 node are connected to electrode C by switch S353A left side it is extreme, N4 node is connected to common-mode signal V by switch S37cm, N4
Node is connected to N5 node by switch S36, and N5 node is connected to the cathode of operational amplifier, and N5 node passes through switch S38
It is connected to common-mode signal Vcm, common-mode signal VcmIt is connected to the anode of operational amplifier, the output end of operational amplifier is described the
The output end V of one surplus multi-gain amplification unitout, the output end V of the first residue multi-gain amplification unitoutWith capacitor C1A left side
Pass through switch S39 connection between pole plate；
The output end V of the first residue multi-gain amplification unitoutPass through switch S41 connection capacitor C1' a left side it is extreme, institute
State the output end V of first residue multi-gain amplification unitoutPass through switch S42 connection capacitor C2' a left side it is extreme, the first residue
The output end V of multi-gain amplification unitoutPass through switch S44 connection capacitor C3' a left side it is extreme, capacitor C1', capacitor C2' and capacitor C3’
The right side extreme connect N4 ' node, signal V simultaneouslyrefpN2 ' node, signal V are connected to by switch S21refnConnected by switch S23
It is connected to N3 ' node, by switch S22 connection between N2 ' node and N3 ' node, N2 ' node is connected to capacitor by switch S43
C2' a left side it is extreme, N3 ' node is connected to electrode C by switch S453' a left side it is extreme, N4 ' node is connected to N5 by switch S46
Node, N5 node are connected to the cathode of operational amplifier, common-mode signal VcmIt is connected to the anode of operational amplifier, operational amplifier
Output end be the second surplus multi-gain amplification unit output end Vout；And the second surplus multi-gain amplification unit is defeated
Outlet VoutWith capacitor C1' left pole plate between pass through switch S49 connection；
Wherein, the disconnection conducting of the switch S1 and switch S38 pass through signal K1Control, the switch S2, switch S37,
The disconnection of switch S46 passes through signal psi1Control, the switch S31, switch S32, switch S34, switch S43, switch S45,
The disconnection of switch S49 passes through signal psi1DControl, the disconnection of the switch S36, switch S47 pass through signal psi2Control
System；The disconnection of the switch S41, switch S42, switch S44, switch S33, switch S35, switch S39 pass through signal psi2DControl
System.
Further, the capacitor C2Capacitance be equal to capacitor C3Capacitance, and be the capacitor C1Capacitance
Half；The capacitor C2' capacitance be equal to capacitor C3' capacitance, and be the capacitor C1' capacitance half,
The capacitor C1Capacitance be equal to the C1' capacitance.
A kind of method that cyclic analog-to-digital converters carry out analog-to-digital conversion, includes the following steps:
S01: in first half period, signal K1, signal psi1And signal psi1DFor high level, the switch conduction controlled,
Signal psi2And signal psi2DSwitch for low level, control disconnects, and first residue multi-gain amplification unit keeps sampling, and will adopt
Sample result is output to the first sub- ADC unit；
S02: in second half period, signal K1, signal psi1And signal psi1DSwitch for low level, control disconnects,
Signal psi2And signal psi2DFor high level, the switch conduction of control, the first sub- ADC unit obtains first quantization 2bit number
According to, and it is transferred to first logic unit, first logic unit carries out logical process according to reception result, and controls and open
Close S11, switch S12With switch S13Carry out surplus gain amplification；The output signal V obtained at this timeoutAmplify in the second surplus gain
It is kept sampling in unit, and sampling structure is output to the second sub- ADC unit；
S03: in the third half period, signal psi1And signal psi1DFor high level, the switch conduction of control, signal K1、
Signal psi2And signal psi2DSwitch for low level, control disconnects, and the second sub- ADC unit obtains second quantization 2bit number
According to, and it is transferred to second logic unit, second logic unit carries out logical process according to reception result, and controls and open
Close S21, switch S22With switch S23Carry out surplus gain amplification；The output signal V obtained at this timeoutAmplify in first residue gain
It is kept sampling in unit, and sampling structure is output to the first sub- ADC unit；
S04: step S02 and S03 are repeated and carries out the 4th to the m-th half period, successively alternate treatment VoutData, until
Obtain final M bit data, wherein M is the even number more than or equal to 2；
S05: M bit data are exported in the M+1 half period, to realize analog-to-digital conversion.
Further, the first sub- ADC unit obtains first quantization 2bit data and first quantization in the step S02
1bit data, the second sub- ADC unit obtains second quantization 2bit data and second quantization 1bit data in step S03.
Further, in the step S04 m-th half period neutron ADC unit obtain the M-1 quantization 2bit data and
The M-1 quantization 1bit data is added by dislocation, obtains final Mbit data；Wherein, first quantization 1bit data is to
M-2 quantization 1bit data are not involved in dislocation and are added, and the M-1 quantization 1bit data participates in dislocation and be added.
Further, in the step S02, as the switch S11And S12Conducting, the switch S13When disconnection, described
The output signal V of one surplus multi-gain amplification unitout=2Vin-Vrefp；As the switch S12And S13Conducting, the switch S11It is disconnected
When opening, the output signal V of the first residue multi-gain amplification unitouT=2Vin-Vrefn；As the switch S11And S13Conducting, institute
State switch S12When disconnection, the output signal V of the first residue multi-gain amplification unitout=2Vin-Vcm, wherein VrefnIt is described
The minimum input value of cyclic analog-to-digital converters, VrefpFor the maximum input level of the cyclic analog-to-digital converters, Vcm=(Vrefp
+Vrefn)/2。
Further, in the step S03, as the switch S21And S22Conducting, the switch S23When disconnection, described
The output signal V of two surplus multi-gain amplification unitsout=2Vin-Vrefp；As the switch S22And S23Conducting, the switch S21It is disconnected
When opening, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vrefn；As the switch S21And S23Conducting, institute
State switch S22When disconnection, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vcm, wherein VrefnIt is described
The minimum input value of cyclic analog-to-digital converters, VrefpFor the maximum input level of the cyclic analog-to-digital converters, Vcm=(Vrefp
+Vrefn)/2。
Further, signal K in the step S011The operational amplifier is resetted while becoming high level
Operation.
Further, signal K in the step S021Failing edge in signal psi1Failing edge after arrive.
The invention has the benefit that conventional single stage cyclic analog-to-digital converters are carried out two-stage cascade by the present invention, realize
While one surplus multi-gain amplification unit carries out sampling and keeps, another surplus multi-gain amplification unit carries out surplus gain amplification
Function can satisfy the CIS application of higher speed so that the conversion rate of cyclic analog-to-digital converters doubles；The present invention
In surplus multi-gain amplification unit use operational amplifier multiplexing form, reduce power consumption；By the adjusting of timing, convenient for real
The switching of existing resolution ratio；In the case where low noise, high-precision analog-to-digital conversion may be implemented；It simultaneously can also be with smaller face
Product realizes higher resolution ratio.
Detailed description of the invention
Attached drawing 1 is cyclic analog-to-digital converters structural framing figure in the present invention.
Attached drawing 2 is the circuit diagram of surplus multi-gain amplification unit in the present invention.
Attached drawing 3 be 10bit cyclic analog-to-digital converters carry out analog-to-digital conversion timing diagram and its corresponding data generate and
Processing schematic.
Attached drawing 4 is the timing schematic diagram of the cyclic analog-to-digital converters of 12bit.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, with reference to the accompanying drawing to specific reality of the invention
The mode of applying is described in further detail.
As shown in Fig. 1, a kind of cyclic analog-to-digital converters being multiplexed operational amplifier in the present invention, including the first son
ADC unit, the second sub- ADC unit, the first logic unit, the second logic unit, first residue multi-gain amplification unit, the second surplus
Multi-gain amplification unit and digital calibration unit, wherein the output end simultaneous connection word calibration unit of the first sub- ADC unit and the
One logic unit, the input terminal of the output end connection first residue multi-gain amplification unit of the first logic unit, first residue gain
The output end of amplifying unit connects the first sub- ADC unit；The output end simultaneous connection word calibration unit of second sub- ADC unit and
Second logic unit, the output end of the second logic unit connect the input terminal of the second surplus multi-gain amplification unit, and the second surplus increases
The output end of beneficial amplifying unit connects the second sub- ADC unit.First residue multi-gain amplification unit and the second surplus gain amplification are single
Member shares an operational amplifier.First residue multi-gain amplification unit and the second surplus multi-gain amplification unit share an operation and put
Big device.In half period, first residue multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier；Second surplus increases
Beneficial amplifying unit carries out surplus gain using operational amplifier and amplifies operation；In adjacent other half period, first residue
Multi-gain amplification unit carries out surplus gain amplification using operational amplifier, and the second surplus multi-gain amplification unit carries out sampling holding,
Without operational amplifier.
Based on conventional pipeline type thought, cyclic analog-to-digital converters with the structure of flow-line modulus converter level-one into
Row loop computation realizes the high speed analog-to-digital conversion under small area.In conventional cyclic analog-to-digital converters, operational amplifier is
It keeps being also used for amplifying for sampling, i.e., half period is kept, and next half period realizes amplification operation, therefore often produces
As soon as raw 1bit needs the time of a clock cycle, then realizing that the analog-digital converter of 10bit needs 10 clock cycle.And this
First residue multi-gain amplification unit MDAC1 and first residue multi-gain amplification unit MDAC2 shares an operational amplifier in invention,
Referring specifically to attached drawing 2:
First residue multi-gain amplification unit and the second surplus multi-gain amplification unit include: capacitor C in the present invention1, capacitor C2、
Capacitor C3, capacitor C1', capacitor C2', capacitor C3' and operational amplifier.Wherein, input terminal VinN1 section is connected to by switch S1
Point, N1 node are connected to the second surplus multi-gain amplification unit output end V by switch S2out, N1 node pass through switch S31 connection
Capacitor C1A left side it is extreme, N1 node passes through switch S32 connection capacitor C2A left side it is extreme, N1 node passes through switch S34 connection capacitor C3
A left side it is extreme；Capacitor C1, capacitor C2With capacitor C3The right side extreme connect N4 node, signal V simultaneouslyrefpIt is connected to by switch S11
N2 node, signal VrefnIt is connected to N3 node by switch S13, passes through switch S12 connection, N2 section between N2 node and N3 node
Point is connected to capacitor C by switch S332A left side it is extreme, N3 node is connected to electrode C by switch S353A left side it is extreme, N4 node
Common-mode signal V is connected to by switch S37cm, N4 node is connected to N5 node by switch S36, and N5 node is connected to operation and puts
The cathode of big device, and N5 node is connected to common-mode signal V by switch S38cm, common-mode signal VcmIt is connected to operational amplifier
Anode, the output end of operational amplifier are the output end V of first residue multi-gain amplification unitout, first residue multi-gain amplification unit
Output end VoutWith capacitor C1Left pole plate between pass through switch S39 connection.
The output end V of first residue multi-gain amplification unitoutPass through switch S41 connection capacitor C1' a left side it is extreme, more than first
The output end V of flow gain amplifying unitoutPass through switch S42 connection capacitor C2' a left side it is extreme, first residue multi-gain amplification unit
Output end VoutPass through switch S441 connection capacitor C3' a left side it is extreme, capacitor C1', capacitor C2' and capacitor C3' the right side it is extremely same
When connect N4 ' node, signal VrefpN2 ' node, signal V are connected to by switch S21refnN3 ' section is connected to by switch S23
Point, by switch S22 connection between N2 ' node and N3 ' node, N2 ' node is connected to capacitor C by switch S432' left pole
End, N3 ' node are connected to electrode C by switch S453' a left side it is extreme, N4 ' node is connected to N5 node, N5 by switch S46
Node is connected to the cathode of operational amplifier, common-mode signal VcmIt is connected to the anode of operational amplifier, the output of operational amplifier
End is the output end V of the second surplus multi-gain amplification unitout；And second surplus multi-gain amplification unit output end VoutWith capacitor
C1' left pole plate between pass through switch S49 connection.
Wherein, the disconnection conducting of switch S1 and switch S38 pass through signal K1Control, switch S2, switch S37, switch S46
Disconnection passes through signal psi1Control, the disconnection of switch S31, switch S32, switch S34, switch S43, switch S45, switch S49
Pass through signal psi1DControl, the disconnection of switch S36, switch S47 pass through signal psi2Control；Switch S41, switch S42,
The disconnection of switch S44, switch S33, switch S35, switch S39 pass through signal psi2DControl.
That is, one of operational amplifier is simulated with dotted line in the present invention in two surplus multi-gain amplification units,
Two input negative terminals of operational amplifier all connect N5 point, positive to terminate common-mode voltage Vcm, output end all connects in Vout, operational amplifier
It is used in turn in MDAC1 and MDAC2 respectively.When MDAC1 carries out holding work, the capacitor bottom crown for charging is directly connect
In common mode terminal, without using arriving operational amplifier；MDAC2 carries out surplus gain amplification work using operational amplifier at this time, i.e.,
It realizes
Vout=2*Vin-VX
Wherein VxFor in margin gain amplifying circuit, according to the quantization of upper level sub-adc converter as a result, believing input
Number carrying out subtraction operation needs the reference value that subtracts.Due to the multiplexing for carrying out operational amplifier, every half period will
Generate the digital code of 2bit.Because every half period just generates the digital code of 2bit, using the first sub- ADC unit and the second son
ADC unit handles V respectivelyoutSignal, quantify for the output result to upper level, export corresponding digital code.Most
Rear stage is the sub- ADC unit of one of them comparator containing there are three of two sub- ADC units, carries out the quantization of afterbody.
As shown in Fig. 3, the processing time of each signal magnitude is then determined by the clock frequency of cyclic analog-to-digital converters,
Clk i.e. in figure handles the input data of an analog-digital converter according to the resolution ratio M of system requirements, and the time needed is M/
2 clocks, and exported in M+1 half period.Therefore an analog-digital converter is corresponded to for each column pixel
Imaging sensor, row readout interval timing are as shown in Figure 3.
Each switch is by non-overlapping clock control in MDAC shown in Fig. 3, wherein signal psi1,φ1DAnd φ2, φ2DWhen
Sequence is as shown in figure 3, signal K1Control the input of signal and the reset of operational amplifier in analog-digital converter.It is adopted to meet sole plate
Sample, therefore signal K1Failing edge must be in signal psi1Failing edge after arrive.
It illustrates how to pass through operation so that cyclic analog-to-digital converters carry out the conversion process of 10bit data as an example in detail below
Data readout process is realized in amplifier multiplexing.
According to 1.5bit Digital calibration algorithm, in the cyclic analog-to-digital converters, it is assumed that the input of analog-digital converter is believed
Number range is VrefnTo Vrefp, i.e., completely width is Vrefp-Vrefn, common mode Vcm=(Vrefp+Vrefn)/2.First sub- ADC unit and second
The threshold voltage of two comparators is respectively V in sub- ADC unitthn=Vcm-(Vrefp-Vrefn)/8, Vthp=Vcm+(Vrefp-
VrefnThe comparator threshold voltage of)/8, last 1bit is then Vcm.For the quantization knot of first half period analog-digital converter output
Fruit d1, can use binary representation, respectively 00,01,10, then existing
Then according to the quantized result of first sub- ADC unit, corresponding MDAC carries out surplus gain to input signal and puts
Big operation, i.e.,
Vout=2*Vin-VX
Quantized result d1 removes control switch (S in Fig. 2 after logic circuit operation11\S12\S13Or S21\S22\S23)
Amount.Specific mode is as shown in Figure 3.Because there are C1=2*C2=2*C3, C1'=2*C2'=2*C3', and C1=C1'.So only
Work as S21=S22When=1 (expression closes the switch), Vx=Vrefp；Work as S22=S23When=1, Vx=Vrefn；Work as S21=S23When=1, then
Vx=Vcm。
Such as with continued reference to attached drawing 3, reset level or the specific conversion regime of signal level include following step in the present invention
It is rapid:
S01: in first half period, signal K1, signal psi1And signal psi1DFor high level, the switch conduction controlled,
Signal psi2And signal psi2DSwitch for low level, control disconnects, and first residue multi-gain amplification unit keeps sampling, and will adopt
Sample result is output to the first sub- ADC unit；
S02: in second half period, signal K1, signal psi1And signal psi1DSwitch for low level, control disconnects,
Signal psi2And signal psi2DFor high level, the switch conduction of control, the first sub- ADC unit obtains first quantization 2bit data
a1, b1, and it is transferred to first logic unit, first logic unit carries out logical process according to reception result, and controls
Switch S11, switch S12With switch S13Carry out surplus gain amplification；The output signal V obtained at this timeoutIt is put in the second surplus gain
It is kept sampling in big unit, and sampling structure is output to the second sub- ADC unit.As switch S11And S12Conducting, switch S13It is disconnected
When opening, the output signal Vo of first residue multi-gain amplification unitut=2Vin-Vrefp；As switch S12And S13Conducting, switch S11It disconnects
When, the output signal V of first residue multi-gain amplification unitout=2Vin-Vrefn；As switch S11And S13Conducting, switch S12It disconnects
When, the output signal V of first residue multi-gain amplification unitout=2Vin-Vcm, wherein VrefnMost for cyclic analog-to-digital converters
Small input value, VrefpFor the maximum input level of cyclic analog-to-digital converters, Vcm=(Vrefp+Vrefn)/2。
S03: in the third half period, signal psi1And signal psi1DFor high level, the switch conduction of control, signal K1、
Signal psi2And signal psi2DSwitch for low level, control disconnects, and the second sub- ADC unit obtains second quantization 2bit data
a2, b2, and it is transferred to second logic unit, second logic unit carries out logical process according to reception result, and controls
Switch S21, switch S22With switch S23Carry out surplus gain amplification；The output signal V obtained at this timeoutIt is put in first residue gain
It is kept sampling in big unit, and sampling structure is output to the first sub- ADC unit.As switch S21And S22Conducting, switch S23It is disconnected
When opening, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vrefp；As switch S22And S23Conducting, switch S21It disconnects
When, the output signal Vo of the second surplus multi-gain amplification unitut=2Vin-Vrefn；As switch S21And S23Conducting, switch S22It disconnects
When, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vcm, wherein VrefnMost for cyclic analog-to-digital converters
Small input value, VrefpFor the maximum input level of cyclic analog-to-digital converters, Vcm=(Vrefp+Vrefn)/2。
S04: step S02 and S03 are repeated and carries out the 4th to the m-th half period, successively alternate treatment VoutData, until
Obtain final M bit data, wherein M is the even number more than or equal to 2.
It is worth noting that: the first sub- ADC unit obtains first quantization 2bit data a in above-mentioned steps S021, b1With
One quantization 1bit data c1, the second sub- ADC unit obtains second quantization 2bit data a in step S032, b2It is measured with second
Change 1bit data c2, until m-th half period, first sub- ADC unit obtain the M-1 quantization 2bit data in step S04
aM-1, bM-1With the M-1 quantization 1bit data cM-1, in dislocation additive process, first quantization 1bit data is to M-2
Quantization 1bit data are not involved in addition, the M-1 quantization 1bit data cM-1Dislocation is participated in be added.
The specific dotted line frame as shown in Data generate time in attached drawing 3, the Data correction mode obtained every time is such as
Dotted line frame shown in trim.
S05: M bit data are exported in the M+1 half period, to realize analog-to-digital conversion.
If above-mentioned D conversion method is applied in CIS, since the imaging sensor in CIS includes reset signal and is adopted
Sample signal, therefore, a complete analog-to-digital conversion period include that the analog-to-digital conversion of reset level and the modulus of signal level turn
It changes.Specifically, in imaging sensor, when the RT signal for controlling reset signal is high level, sampling obtains the reset electricity of pixel
It is flat, the analog-to-digital conversion of reset level is carried out using the above method.When the TX for controlling sampled signal is high level, sample into second
After a data, signal K1It is set as high again, sampling obtains the signal level of pixel, carries out signal level using the above method again
Analog-to-digital conversion.Wherein, intermediate can there are certain delay times, specific timing needs to be examined according to the angle that CIS system is applied
Consider.After the reset level and signal level of a cycle complete analog-to-digital conversion, continues beginning RT signal and switched to by high level
Low level starts the reset level of a new round and the analog-to-digital conversion of signal level.
Same reason please refers to attached drawing 4 when cyclic analog-to-digital converters structure needs to export 12bit in the present invention,
By adjusting the corresponding number of cycles of clk, so that it may realize the adjustment of analog-to-digital converter resolution, specific D conversion method
Still as described in the above method.For identical input range value, in the case where circuit global noise is low, so that it may realize more
High conversion accuracy.Specific sampling hold mode and the analog-digital converter output phase of above-mentioned 10bit are same, only clk corresponding week
Phase number increases by one, is not described in detail herein.
The process has dexterously been multiplexed amplifier, and two surplus multi-gain amplification units work alternatively, so that analog-to-digital conversion
Cycle time half.If applying in CIS system, the corresponding row period can shorten about half, then for same big
Small pixel array, has been more greatly improved the frame per second of imaging sensor, therefore the structure is suitable for high speed
In CIS system.
The present invention has carried out structure improvement to common cyclic analog-to-digital converters, so that in the feelings for not increasing extra power consumption
Under condition, the conversion rate of analog-digital converter is doubled.And according to system needs, it is adjustable to can be made a/d resolution
Mode, high-resolution implementation is simple and rate be still able to maintain it is higher.In the case where system noise is relatively low, realize high
Resolution ratio is improved the precision of analog-to-digital conversion.If analog-digital converter is applied in high speed CIS system application in the present invention
In, it also will be helpful to the quality for improving image.
The above description is only a preferred embodiment of the present invention, and the embodiment is not intended to limit patent protection of the invention
Range, thus it is all with the variation of equivalent structure made by specification and accompanying drawing content of the invention, it similarly should be included in this
In the protection scope of invention appended claims.
Claims (10)
1. a kind of cyclic analog-to-digital converters for being multiplexed operational amplifier, which is characterized in that including the first sub- ADC unit, second
Sub- ADC unit, the first logic unit, the second logic unit, first residue multi-gain amplification unit, the second surplus multi-gain amplification unit
With digital calibration unit, wherein the output end simultaneous connection word calibration unit and the first logic list of the first sub- ADC unit
Member, the output end of first logic unit connect the input terminal of the first residue multi-gain amplification unit, the first residue
The output end of multi-gain amplification unit connects the first sub- ADC unit；The output end simultaneous connection of the second sub- ADC unit
The output end of word calibration unit and the second logic unit, second logic unit connects the second surplus multi-gain amplification unit
Input terminal, the output end of the second surplus multi-gain amplification unit connects the second sub- ADC unit；
The first residue multi-gain amplification unit and the second surplus multi-gain amplification unit share an operational amplifier.At half week
In phase, first residue multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier；Second surplus multi-gain amplification unit uses
Operational amplifier carries out surplus gain and amplifies operation；In adjacent other half period, first residue multi-gain amplification unit is adopted
Surplus gain amplification is carried out with operational amplifier, the second surplus multi-gain amplification unit carries out sampling holding, is not necessarily to operational amplifier.
2. a kind of cyclic analog-to-digital converters for being multiplexed operational amplifier according to claim 1, which is characterized in that described
First residue multi-gain amplification unit and the second surplus multi-gain amplification unit include: capacitor C1, capacitor C2, capacitor C3, capacitor C1 ',
Capacitor C2 ', capacitor C3 ' and operational amplifier；
Wherein, input terminal VinIt is connected to N1 node by switch S1, N1 node is connected to second surplus by switch S2 and increases
Beneficial amplifying unit output end Vout, N1 node pass through switch S31 connection capacitor C1A left side it is extreme, N1 node passes through switch S32 connection
Capacitor C2A left side it is extreme, N1 node passes through switch S34 connection capacitor C3A left side it is extreme；Capacitor C1, capacitor C2With capacitor C3Right pole
It holds while connecting N4 node, signal VrefpN2 node, signal V are connected to by switch S11refnN3 section is connected to by switch S13
Point, by switch S12 connection between N2 node and N3 node, N2 node is connected to capacitor C by switch S332A left side it is extreme, N3
Node is connected to electrode C by switch S353A left side it is extreme, N4 node is connected to common-mode signal V by switch S37cm, N4 node
It is connected to N5 node by switch S36, N5 node is connected to the cathode of operational amplifier, and N5 node passes through switch S38 connection
To common-mode signal Vcm, common-mode signal VcmIt is connected to the anode of operational amplifier, the output end of operational amplifier is described more than first
The output end V of flow gain amplifying unitout, the output end V of the first residue multi-gain amplification unitoutWith capacitor C1Left pole plate
Between pass through switch S39 connection；
The output end V of the first residue multi-gain amplification unitoutPass through switch S41 connection capacitor C1' a left side it is extreme, described first
The output end V of surplus multi-gain amplification unitoutPass through switch S42 connection capacitor C2' a left side it is extreme, the first residue gain is put
The output end V of big unitoutPass through switch S44 connection capacitor C3' a left side it is extreme, capacitor C1', capacitor C2' and capacitor C3' right pole
It holds while connecting N4 ' node, signal VrefpN2 ' node, signal V are connected to by switch S21refnIt is connected to by switch S23
N3 ' node, by switch S22 connection between N2 ' node and N3 ' node, N2 ' node is connected to capacitor C by switch S432'
Left extreme, N3 ' node is connected to electrode C by switch S453' a left side it is extreme, N4 ' node is connected to N5 section by switch S46
Point, N5 node are connected to the cathode of operational amplifier, common-mode signal VcmIt is connected to the anode of operational amplifier, operational amplifier
Output end is the output end V of the second surplus multi-gain amplification unitout；And the output of the second surplus multi-gain amplification unit
Hold VoutWith capacitor C1' left pole plate between pass through switch S49 connection；
Wherein, the disconnection conducting of the switch S1 and switch S38 pass through signal K1Control, the switch S2, switch S37, switch
The disconnection of S46 passes through signal psi1Control, the switch S31, switch S32, switch S34, switch S43, switch S45, switch
The disconnection of S49 passes through signal psi1DControl, the disconnection of the switch S36, switch S47 pass through signal psi2Control；Institute
The disconnection for stating switch S41, switch S42, switch S44, switch S33, switch S35, switch S39 passes through signal psi2DControl.
3. a kind of cyclic analog-to-digital converters for being multiplexed operational amplifier according to claim 2, which is characterized in that described
Capacitor C2Capacitance be equal to capacitor C3Capacitance, and be the capacitor C1Capacitance half；The capacitor C2'
Capacitance is equal to capacitor C3' capacitance, and be the capacitor C1' capacitance half；The capacitor C1Capacitance etc.
In the C1' capacitance.
4. a kind of method for carrying out analog-to-digital conversion using cyclic analog-to-digital converters as claimed in claim 2, which is characterized in that packet
Include following steps:
S01: in first half period, signal K1, signal psi1And signal psi1DFor high level, the switch conduction of control, signal
φ2And signal psi2DSwitch for low level, control disconnects, and first residue multi-gain amplification unit keeps sampling, and sampling is tied
Fruit is output to the first sub- ADC unit；
S02: in second half period, signal K1, signal psi1And signal psi1DSwitch for low level, control disconnects, signal
φ2And signal psi2DFor high level, the switch conduction of control, the first sub- ADC unit obtains first quantization 2bit data, and
It is transferred to first logic unit, first logic unit carries out logical process, and control switch S according to reception result11、
Switch S12With switch S13Carry out surplus gain amplification；The output signal V obtained at this timeoutIn the second surplus multi-gain amplification unit
It is kept sampling, and sampling structure is output to the second sub- ADC unit；
S03: in the third half period, signal psi1And signal psi1DFor high level, the switch conduction of control, signal K1, signal
φ2And signal psi2DSwitch for low level, control disconnects, and the second sub- ADC unit obtains second quantization 2bit data, and
It is transferred to second logic unit, second logic unit carries out logical process, and control switch S according to reception result21、
Switch S22With switch S23Carry out surplus gain amplification；The output signal V obtained at this timeoutIn first residue multi-gain amplification unit
It is kept sampling, and sampling structure is output to the first sub- ADC unit；
S04: step S02 and S03 are repeated and carries out the 4th to the m-th half period, successively alternate treatment VoutData, until obtaining
Final M bit data, wherein M is the even number more than or equal to 2；
S05: M bit data are exported in the M+1 half period, to realize analog-to-digital conversion.
5. according to the method described in claim 4, it is characterized in that, the first sub- ADC unit obtains first in the step S02
Quantify 2bit data and first quantization 1bit data, the second sub- ADC unit obtains second quantization 2bit data in step S03
With second quantization 1bit data.
6. according to the method described in claim 5, it is characterized in that, m-th half period neutron ADC unit in the step S04
The M-1 quantization 2bit data and the M-1 quantization 1bit data are obtained, is added by dislocation, obtains final Mbit data；Its
In, first quantization 1bit data to the M-2 quantization 1bit data are not involved in dislocation and are added, the M-1 quantization 1bit data
Dislocation is participated in be added.
7. according to the method described in claim 4, it is characterized in that, in the step S02, as the switch S11And S12Conducting,
The switch S13When disconnection, the output signal V of the first residue multi-gain amplification unitout=2Vin-Vrefp；When the switch
S12And S13Conducting, the switch S11When disconnection, the output signal V of the first residue multi-gain amplification unitouT=2Vin-Vrefn；
As the switch S11And S13Conducting, the switch S12When disconnection, the output signal V of the first residue multi-gain amplification unitout
=2Vin-Vcm, wherein VrefnFor the minimum input value of the cyclic analog-to-digital converters, VrefpFor the circular form analog-to-digital conversion
The maximum input level of device, Vcm=(Vrefp+Vrefn)/2。
8. according to the method described in claim 4, it is characterized in that, in the step S03, as the switch S21And S22Conducting,
The switch S23When disconnection, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vrefp；When the switch
S22And S23Conducting, the switch S21When disconnection, the output signal V of the second surplus multi-gain amplification unitout=2Vin-Vrefn；
As the switch S21And S23Conducting, the switch S22When disconnection, the output signal V of the second surplus multi-gain amplification unitout
=2Vin-Vcm, wherein VrefnFor the minimum input value of the cyclic analog-to-digital converters, VrefpFor the circular form analog-to-digital conversion
The maximum input level of device, Vcm=(Vrefp+Vrefn)/2。
9. according to the method described in claim 4, it is characterized in that, signal K in the step S011While becoming high level pair
The operational amplifier carries out reset operation.
10. according to the method described in claim 4, it is characterized in that, signal K in the step S021Failing edge in signal psi1
Failing edge after arrive.
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