CN103986470B - Low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and converter - Google Patents
Low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and converter Download PDFInfo
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Abstract
The invention relates to the field of digital-analog hybrid integrated circuit design, aims to increase the conversion rate of a monoclinic ADC and provides the analog-digital converter which is simple in structure and low in power consumption. According to the adopted technical scheme of a low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and a converter, the converter is composed of a ramp generator, a counter, comparators, multiplexer switches and a register; the ramp generator generates a ramp voltage Vramp and k reference voltages VrefK, wherein K=1, 2, 3..., K; each of the k reference voltages VrefK is supplied to the corresponding comparator through one of the corresponding multiplexer switches; the ramp voltage Vramp is supplied to each comparator. The low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and the converter are mainly applied to digital-analog hybrid integrated circuit design.
Description
Technical field
The present invention relates to hybrid digital-analog integrated circuit design field, particularly to low-power consumption row level many reference voltages monocline mould
Number conversion method and converter.
Technical background
Cmos image sensor has that integrated level is high, low in energy consumption and low cost and other advantages, is widely used in IMAQ neck
Domain.ADC is the important component part of cmos image sensor it is achieved that converting analog signals into the function of data signal.Mesh
Front application ADC in cmos image sensors has three types：Pixel-level ADC, row level ADC and chip-scale ADC.Row level ADC
Compared with chip-scale ADC, relatively low to ADC rate request, reduce design difficulty；Compared with Pixel-level ADC, improve filling because
Son, thus improve the photoelectric transformation efficiency of imageing sensor, therefore row level ADC is widely applied.But row level ADC also face
Face some challenges：Row level ADC is limited to Pixel Dimensions on col width；Imbalance between the column and the column can introduce row level fixed mode
Noise.
For row level ADC in cmos image sensor, existing main implementation has monocline ADC, successive approximation analog to digital C
With circulation A DC etc..Wherein, monocline ADC is most widely used.Because its circuit structure is simple, each column only needs to a comparator
And register, area occupied is little；Each arranging shares a slope, and between row, uniformity is good.Fig. 1 show in cmos image sensor
The structured flowchart of monocline ADC and the course of work.When conversion starts, analog input signal Vin is sampled holding, then counter control
Ramp generator processed produces ramp voltage Vramp, and is compared with Vin.When Vramp is more than Vin, comparator output occurs
Upset, Counter Value now is preserved by control register, the as result of quantization.
But monocline ADC has individual significant drawbacks it is simply that switching rate is slow, and monocline ADC of N position at least needs 2NThe individual clock cycle
Just can complete once to change.This shortcoming limits the application in the occasion such as big pel array or high frame frequency for monocline ADC.In order to carry
Its switching rate high, needs its structure is improved, existing technology has：
1) monocline ADC of slope step-size change, it is directly proportional to light intensity theory according to picture element signal noise, by ramp voltage
It is changed to step-length to raise with voltage and increase, that is, create a nonlinear slope similar to exponential increase, shorten conversion
Time, and do not reduce the performance of imageing sensor.
2) two step monocline ADC.Quantizing process is divided into thick quantization and thin quantization two steps by this structure.It will be oblique during thick quantization
Slope voltage is stored on electric capacity, for carefully quantifying further.But the electric charge injection of MOS switch can introduce larger error.
3) many slopes ADC.As its name suggests, it is quantified using multiple different interval ramp voltages simultaneously, can become
Speed quantization speed again.But need multiple ramp generators, and power consumption can increase a lot.
Content of the invention
For overcoming the deficiencies in the prior art, accelerate the switching rate of monocline ADC, realize analog-digital converter structure letter simultaneously
Single, low in energy consumption.For this reason, the present invention adopts the technical scheme that, low-power consumption row level many reference voltages monocline analog-digital converter, by oblique
Slope generator, counter, comparator, multidiameter option switch, register composition, ramp generator produces ramp voltage Vramp and k
Individual reference voltage Vref K, K=1,2,3 ..., k；Each road voltage in k reference voltage Vref K passes through the many of each row respectively
One of road selecting switch switch is supplied to the comparator of this row；Ramp voltage Vramp is also respectively supplied to the ratio of each row
Compared with device.
Ramp generator is made to produce Vramp and k reference voltage Vref K of ramp voltage, K=1,2,3 ..., k；K reference
Each road voltage in voltage VrefK is supplied to the comparison of this row respectively by one of multidiameter option switch of each row switch
Device；Ramp voltage Vramp is also respectively supplied to the comparator of each row；Wherein, the course of work is divided into thick quantization and thin quantization two
The individual stage：
Thick quantization stage：Switch S1～the Sk of k reference voltage Vref K connection closes in order successively, so that each row is compared
The Vin1- end of device be sequentially connected to reference voltage Vref 1, Vref2 ... Vrefk, formed k plateau voltage, Vramp is defeated simultaneously
Go out maximum level Vrefp, thus the Vin1+ end of each row comparator is also Vrefp always, then the poor VR of Vin1+ and Vin1- is to pass
The step signal subtracting；The Vin2+ of each row comparator/- one differential signal Vsig of end input, and Vsig is compared with VR,
Vsig during beginning<VR, comparator is output as 0, works as Vsig>During VR, comparator overturns as 1, simultaneously by the thick value quantifying counter
It is stored in memory；
Thin quantization stage：Whole quantizing range Vref=Vrefp-Vrefn is divided into k thin quantized interval, each row according to
The thick result quantifying, controls each analog switch to make comparator be connected to correct reference voltage, thus have selected corresponding thin amount
Change interval, if thick quantized result is K, then switch SK conducting, comparator Vin1- end is connected to VrefK；Have selected (k-K)/
kVrefTo (k-K-1)/kVrefThin quantized interval；Vramp produces the Vin1+ end that ramp voltage is supplied to each row comparator, its model
Enclose for Vrefp-Vref/ k to Vrefp；The poor VR of therefore Vin1+ and Vin1- is the ramp voltage through translation, and with Vsig same
One thin quantized interval, signal Vsig is compared with slope VR, and when the two is almost equal, comparator output inverts,
And the thin value quantifying counter is stored in memory；Thick quantized result is a high position, thin quantized result is as low level, you can close
Become to obtain final quantized result.
Compared with the prior art, the technical characterstic of the present invention and effect：
Quantified by being divided into thickness two step, the switching rate of monocline ADC can be greatly improved.For monocline ADC of N position,
Quantization every time at least needs 2NClock cycle；And m position is slightly quantified, thin this structure m+n=N quantifying in n position, then need at least
2m+2nThe individual clock cycle.
Compared with existing many ramp structures, this technology lower power consumption, structure are simple.Many ramp structures need generation many
Individual slope, therefore Ramp generator complex structure.And this technology only needs to produce a slope.In addition, the slope of each generation
Need to drive the comparator of all row through a very big buffer, when therefore adopting multiple slope, these buffer meetings
Greatly increase power consumption.And this technology using single slope although each reference voltage is also required to connect buffer, but because its be straight
Stream level, so low to the rate request of buffer, power consumption also decreases.Therefore can be added from more reference voltages
Fast switching rate, and it is not result in that buffer power consumption too increases.
Brief description
Fig. 1 is the structural framing of monocline ADC and course of work schematic diagram that prior art provides,
Fig. 2 is the Organization Chart of many reference voltages monocline ADC that the present invention provides,
Fig. 3 is the ramp voltage of present invention offer and the schematic diagram of many reference voltages,
Fig. 4 is many reference voltages monocline ADC course of work schematic diagram that the present invention provides.
Specific embodiment
The present invention has carried out to many slopes ADC improving it is proposed that single slope, the structure of multiple reference voltages.It can be big
The big switching rate accelerating monocline ADC, structure is simple simultaneously, low in energy consumption.
The present invention to improve monocline ADC using the structure on single slope, multiple reference voltage, and structure is as shown in Figure 2.Slope
And reference voltage generator generation Vramp and k reference voltage Vref K of ramp voltage (K=1,2,3 ..., k), it is supplied to each row
Use.As shown in figure 3, the scope of ramp voltage is the 1/k of quantizing range (Vref=Vrefp-Vrefn), each joins its waveform
Examine voltage and quantizing range is divided into k thin quantized interval.Each column circuits include comparator, multidiameter option switch, logic electricity
Road and storage circuit.Two column circuits are only drawn for the sake of simple, for each row, its structure ＆ working mechanism is homogeneous in accompanying drawing 2
With.Its course of work is divided into thick quantization and two stages of thin quantization：
Thick quantization stage：Analog switch S1～the Sk of each row closes in order successively, so that the Vin1- end of comparator is connected successively
Be connected to reference voltage Vref 1, Vref2 ... Vrefk, formed k plateau voltage, simultaneously Vramp export maximum level Vrefp, because
And Vin1+ end is also Vrefp always, shown in voltage waveform such as Fig. 4 (a).The poor VR of so Vin1+ and Vin1- is the platform successively decreasing
Rank signal, shown in Fig. 4 (b).The Vin2+ of comparator/- end input differential signal Vsig, and Vsig is compared with VR, start
When Vsig<VR, comparator is output as 0, works as Vsig>During VR, comparator overturns as 1, as shown in Fig. 4 (c), will slightly quantify to count simultaneously
The value of number device is stored in memory.
Thin quantization stage：Whole quantizing range (Vref=Vrefp-Vrefn) is divided into k thin quantized interval.According to thick
The result quantifying, controls each analog switch to make comparator be connected to correct reference voltage, thus have selected corresponding thin quantization
Interval, such as shown in Fig. 4 (a), switch S2 conducting, comparator Vin1- end is connected to Vref2, that is, have selected (k-2)/k VrefExtremely
(k-1)/k·VrefThin quantized interval.Vramp produces the Vin1+ end that ramp voltage is supplied to comparator, in the range from Vrefp-
Vref/ k to Vrefp.The poor VR of therefore Vin1+ and Vin1- is the ramp voltage through translation, and with Vsig in same thin quantization
Interval, such as shown in Fig. 4 (b).Signal Vsig is compared with slope VR, when the two is almost equal, comparator output occurs
Reversion, and the thin value quantifying counter is stored in memory.Using thick quantized result DCoarse as a high position, thin quantized result
DFine is as low level, you can synthesis obtains final quantized result.
For making the object, technical solutions and advantages of the present invention become apparent from, provide the present invention below in conjunction with example and implement
The specific descriptions of mode.Explanation first taking many reference voltages of 12 as a example.Using single slope, eight reference voltages
Structure, whole quantizing range has been divided into 8 thin quantized intervals.3 thick quantized result can be obtained in thick quantization stage, according to
This result selects thin quantized interval, is then carefully quantified, obtains 9 thin quantized result, finally can synthesize 12 quantizations
Result.One quantifies cycle needs at least 23+29Clock cycle, and according to traditional monocline ADC structure, then need at least 212When
The clock cycle can improve nearly 8 times it is seen that quantifying speed.
With reference to a cmos image sensor example come the invention will be further described：Cmos image senses
Device pel array totally 1024 row, the available Layout width of every row reading circuit is 30 μm.Wherein row level ADC requires 12 essences
Degree, the quantization cycle is 64us.Many reference voltages monocline ADC adopts eight reference voltages, can meet the requirement of speed and precision, and
Power consumption will not too be increased.Can be estimated as follows according to the requirement to buffer bandwidth for this example：Single ramp buffer
Power consumption 8mW, single Voltage Reference Buffer power consumption is 1.2mW, many slopes ADC on eight slopes providing according to prior art
Structure, then buffer total power consumption be up to 65.2mW, and the buffer total power consumption of many reference voltages ADC structure is only 17.6mW.
Claims (2)
1. a kind of low-power consumption row level many reference voltages monocline analog-digital converter, is characterized in that, by ramp generator, counter, ratio
Compared with device, multidiameter option switch, register composition, ramp generator produces Vramp and k reference voltage Vref K of ramp voltage, K
=1,2,3 ..., k；Each road voltage in k reference voltage Vref K passes through one of multidiameter option switch of each row respectively
Switch is supplied to the comparator of this row；Ramp voltage Vramp is also respectively supplied to the comparator of each row.
2. a kind of low-power consumption row level many reference voltages monocline D conversion method, is characterized in that, comprise the following steps：
Ramp generator is made to produce Vramp and k reference voltage Vref K of ramp voltage, K=1,2,3 ..., k；K reference voltage
Each road voltage in VrefK passes through the comparator that one of multidiameter option switch of each row switch is supplied to this row respectively；
Ramp voltage Vramp is also respectively supplied to the comparator of each row；Wherein, the course of work is divided into thick quantization and two ranks of thin quantization
Section：
Thick quantization stage：Switch S1～the Sk of k reference voltage Vref K connection closes in order successively, makes each row comparator
Vin1- end be sequentially connected to reference voltage Vref 1, Vref2 ... Vrefk, formed k plateau voltage, simultaneously Vramp output
High level Vrefp, thus the Vin1+ end of each row comparator is also V alwaysrefp, then the poor VR of Vin1+ and Vin1- is the platform successively decreasing
Rank signal；The Vin2+ of each row comparator/- one differential signal Vsig of end input, and Vsig is compared with VR, during beginning
Vsig<VR, comparator is output as 0, works as Vsig>During VR, comparator overturns as 1, is stored to the thick value quantifying counter simultaneously
In reservoir；
Thin quantization stage：Whole quantizing range Vref=Vrefp-VrefnIt is divided into k carefully quantized interval, each row are according to thick quantization
As a result, each analog switch is controlled to make comparator be connected to correct reference voltage, thus have selected corresponding thin quantized interval, if
Thick quantized result is K, then switch SK conducting, comparator Vin1- end is connected to VrefK；Have selected [(k-K)/k] Vref
To [(k-K-1)/k] VrefThin quantized interval；Vramp produces the Vin1+ end that ramp voltage is supplied to each row comparator, its model
Enclose forTo Vrefp；The poor VR of therefore Vin1+ and Vin1- is the ramp voltage through translation, and with Vsig same
One thin quantized interval, signal Vsig is compared with slope VR, and when the two is equal, comparator output inverts, and will
The thin value quantifying counter is stored in memory；Thick quantized result is a high position, thin quantized result obtains as low level, i.e. synthesis
Final quantized result.
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| KR20160109001A (en) * | 2015-03-09 | 2016-09-21 | 에스케이하이닉스 주식회사 | Comparator using multi input differential pair and differential sampling, and analog-digital converting apparatus using that |
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