CN102386923B - Asynchronous successive approximation analog-to-digital converter and conversion method - Google Patents
Asynchronous successive approximation analog-to-digital converter and conversion method Download PDFInfo
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- CN102386923B CN102386923B CN201110280963.8A CN201110280963A CN102386923B CN 102386923 B CN102386923 B CN 102386923B CN 201110280963 A CN201110280963 A CN 201110280963A CN 102386923 B CN102386923 B CN 102386923B
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Abstract
The invention discloses an asynchronous successive approximation analog-to-digital converter and a conversion method. The asynchronous successive approximation analog-to-digital converter comprises: a sampling network, a main capacitor array, an auxiliary capacitor array, a comparator and a logic control circuit. The sampling network of the main capacitor array uses a bootstrap switch. The sampling network of the auxiliary capacitor array uses a CMOS switch. Each two same capacitors in the main capacitor array are in a group. A capacitance value size is reduced as two times relationship. Top crowns of all the capacitors and the bootstrap switch are connected and output to the comparator. The each two same capacitors in the auxiliary capacitor array are in one group. The capacitance value size is reduced as four times relationship. The top crowns of all the capacitors and the CMOS switch are connected and output to the comparator. The comparator comprises a preamplifier and a latch and compares the size of an output voltage of the main capacitor array and the auxiliary capacitor array. The logic control circuit uses an asynchronous sequential control capacitor array to successively complete switching. A power consumption efficiency of the analog-to-digital converter can be effectively raised. And demands of capacitor coupling and a peripheral circuit can be reduced. The method is suitable for a deep-submicron low voltage design.
Description
Technical field
The present invention relates to a kind of asynchronous gradually-appoximant analog-digital converter and conversion method, be particularly related to a kind of by improving retrieval mode, improve power consumption efficiency, reduce electric capacity coupling and peripheral circuit demand, and be applicable to the asynchronous gradually-appoximant analog-digital converter of deep-submicron low supply voltage.
Technical background
Gradually-appoximant analog-digital converter is a kind of type that is applied to medium accuracy, medium sample rate, with respect to other types analog to digital converters such as flash-type, pipeline-types, the highest power consumption efficiency is arranged, and in medical treatment and portable equipment, is widely used.
Traditional synchronous gradually-appoximant analog-digital converter needs a High Speed System clock (transducer of sample frequency is resolved figure place doubly), no matter be to produce in inside, or from sheet, directly input all can increase the extra power consumption of chip, allows the high power consumption efficiency of successive approximation have a greatly reduced quality.
Because gradually-appoximant analog-digital converter need to be used the capacitor array that twice increases progressively, the coupling between minimum and maximum electric capacity has limited the overall precision of analog to digital converter.Adopt specific capacitance and centrosymmetric laying out pattern can reduce the impact of this restriction, but can not be from address this problem at all, a lot of designs adopt the mode of figure adjustment to improve the precision of electric capacity coupling.
The reference voltage that gradually-appoximant analog-digital converter is connected on the electric capacity bottom crown by switching successively approaches final result, the electric charge consumed in switch-capacitor is the main source of this type of analog to digital converter power consumption, and the switching mode that service efficiency is higher also becomes one of main direction of studying of further raising power consumption efficiency.
Summary of the invention
The object of the invention is, by a kind of asynchronous gradually-appoximant analog-digital converter and conversion method are provided, improvement approaches searching algorithm and uses asynchronous sequencing control, improve the power consumption efficiency of gradually-appoximant analog-digital converter, reduce electric capacity coupling and peripheral circuit demand, and be applicable to the deep-submicron low supply voltage.
The present invention adopts following technological means to realize:
A kind of asynchronous gradually-appoximant analog-digital converter comprises: sampling network, main capacitance array, attached capacitor array, comparator and logic control circuit.
The sampling network of main capacitance array is connected respectively to normal phase input end and the reverse input end of difference analogue input signal by two bootstrap type switches; The sampling network of attached capacitor array is connected to the common mode reference voltage of analog input signal by two cmos switches.
An end of the top crown of all electric capacity and the aforementioned bootstrap type switch input comparator that links together in the main capacitance array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of twice, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array.
An end of the top crown of all electric capacity and the aforementioned cmos switch input comparator that links together in attached capacitor array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of four times, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array.
Comparator is by comparing the voltage of main capacitance array and attached capacitor array top crown, the signal of exporting comparative result and relatively completing.
Logic control circuit receives from the comparative result of comparator and compares settling signal, correspondingly alternately switch respectively main capacitance array and attached capacitor array until complete all comparisons of once sampling, and then all bottom crown control signals are reset to initial value start to sample next time.
A kind of asynchronous D conversion method that successively approaches comprises following several step:
Step 1: the bottom crown control signal of resetting all is initial value.
Step 2: according to comparative result for the first time, switch one group of control signal that electric capacity is corresponding maximum in attached capacitor array: if comparative result for just, is+1/2Vref (difference analogue input reference signal+arrive-Vref of Vref between) by its output switching; If comparative result, for negative, by its output switching is-1/2Vref.
Step 3: after completing steps 2 again according to one group of maximum control signal that electric capacity is corresponding in the comparative result of new round switching main capacitance array: if 1. step 2 comparative result is for just: if this comparative result for just, the operation of switched-3/4Vref; If this comparative result is negative, the operation of switched-1/4Vref.2. if step 2 comparative result is for negative: if this comparative result for just, the operation of switched+1/4Vref; If this comparative result is negative, the operation of switched+3/4Vref.
Step 4: by that analogy, repetitive cycling step 2 and step 3 until be switched to the main capacitance array and attached capacitor array in one group of minimum electric capacity, then export the binary code relatively obtained and convert signal, finishing this sample conversion process, waiting for and entering next time.
In main capacitance array and attached capacitor array, every two electric capacity are one group, and one is played the effect that adds reference voltage, and another plays the effect that deducts reference voltage, and changing the initial value of its control signal in sampling process just can complete operation.
The present invention compared with prior art, has following obvious advantage and beneficial effect:
The present invention uses the gradually-appoximant analog-digital converter of asynchronous sequencing control, be operated under low-voltage and (be less than 1 volt), has saved the link that peripheral circuit provides the High Speed System clock.By the searching algorithm that approaches after improving, the coupling demand to electric capacity in tradition analog to digital converter of the same type is relax to in the past 4 times, and reduced the power consumption in the electric capacity handoff procedure.Because comparison reference voltage is used supply voltage and ground, therefore no longer need conducting resistance with the buffer provided in the cmos switch of signal changes in amplitude and peripheral circuit.
In sum, the present invention has realized the asynchronous gradually-appoximant analog-digital converter of Low-voltage Low-power, has improved power consumption efficiency, has reduced electric capacity coupling and peripheral circuit demand.
The accompanying drawing explanation
The structured flowchart that Fig. 1 is asynchronous gradually-appoximant analog-digital converter;
The circuit diagram that Fig. 2 is asynchronous gradually-appoximant analog-digital converter in the embodiment of the present invention;
The circuit diagram that Fig. 3 is comparator in the embodiment of the present invention;
The structure chart that Fig. 4 is logic control circuit in the embodiment of the present invention;
The circuit diagram that Fig. 5 is logic control circuit unit 1 in the embodiment of the present invention;
The circuit diagram that Fig. 6 is logic control circuit unit 2 in the embodiment of the present invention;
The sequential schematic diagram that Fig. 7 is comparator in the embodiment of the present invention;
The simulation result schematic diagram that Fig. 8 is main capacitance array and attached capacitor array output in the embodiment of the present invention;
The fast Fourier transform simulation result schematic diagram that Fig. 9 is analog to digital converter output in the embodiment of the present invention.
Symbol description:
201: the main capacitance array; 202: attached capacitor array; 203: the bootstrap type sampling switch; 204: comparator; 205: logic control circuit;
801: analog input signal; 802: the main capacitance array output signal; 803: attached capacitor array output signal.
Specific implementation method
Below in conjunction with Figure of description, specific embodiments of the invention are illustrated:
As shown in Figure 1, the structured flowchart of a kind of asynchronous gradually-appoximant analog-digital converter of the present invention comprises: sampling network, main capacitance array, attached capacitor array, comparator and logic control circuit.What in the embodiment of the present invention, realize is the gradually-appoximant analog-digital converter of 8 bits, 50 megahertz sample rates.
The input signal of main capacitance array, owing to being time dependent analog signal, therefore adopts the bootstrap type sampling switch; The input signal of attached capacitor array is common mode reference voltage, and temporal evolution, therefore do not adopt the CMOS sampling switch.
Fig. 2 has provided the circuit diagram of main capacitance array and attached capacitor array.The main capacitance array comprises the electric capacity that 13 top crowns link together, the bottom crown ground connection of 1 electric capacity wherein, capacitance size is C*262/3 (C is specific capacitance), every two of other 12 electric capacity are one group, bottom crown is by the output process inverter controlling of logic control circuit, maximum one group is 32*C, and minimum one group is 1*C; Attached capacitor array comprises the electric capacity that 9 top crowns link together, the bottom crown ground connection of 1 electric capacity wherein, capacitance size is C*770/3, every two of other 8 electric capacity are one group, bottom crown is by the output process inverter controlling of logic control circuit, maximum one group is 64*C, and minimum one group is 1*C.
Fig. 3 has provided the circuit diagram of comparator.Input adopts two differential pairs, and wherein IP and IN are the output of main capacitance array, and REF1 and REF2 are the output of attached capacitor array.On the left of Fig. 3 is prime amplifier, enlarges the gap between voltage to be compared; Right side is latch (latch), and the gap between voltage is further enlarged to supply voltage and ground.For peripheral circuits, prime amplifier is not to use reference current source to do biasing, but introduce clock signal, by voltage-controlled current source, does biasing, so can when not needing amplification, turn off amplifier yet and reduce power consumption.Similarly, clock signal can be turn-offed latch when comparator is idle.Relatively settling signal is that the output of latch is obtained through after NOR gate.
Fig. 4 has provided the structure chart of logic control circuit, mainly by unit 1 and unit 2, formed, wherein 1 grade of all unit is linked togather the enable signal that provides successively respectively rear 8 comparisons of once sampling, and 2 of unit complete a part of post-processing function of unit 1 output signal.Last combinational logic converts the output of unit 2 to main, the needed control signal of attached capacitor array.Fig. 5 has provided the circuit diagram of unit 1, and wherein set and set_next are interfaces at the corresponding levels and previous stage and rear one-level, and rdy is the comparison settling signal, and cmp is the comparator enable signal; Fig. 6 has provided the circuit diagram of unit 2, and cmp_out is the comparative result of comparator, and rst is reset signal, all can be effectively once before each sampling, and set is in Fig. 4 or the output of door, and rdy is the comparison settling signal, and bit is analog to digital converter digital code to be exported.Fig. 7 has provided the sequential chart of comparator, and the cmp enable signal is effectively low, through the comparative result of comparator output after a while cmp_out, and stablizes relatively settling signal rdy of rear output at comparative result.
Fig. 8 has provided in the situation that sinusoidal analog signal is inputted, the variation of output signal when main capacitance array and attached capacitor array switched voltage.With traditional approach, compare, power consumption efficiency is improved.Fig. 9 is the fast Fourier transform simulation result of analog to digital converter output.
Implement key of the present invention and be to design asynchronous sequential circuit, due to impact parasitic on load and line and between line, there will be time delay in various degree and the increase of rise and fall time between each control signal, this problem can affect the realization of asynchronous control function on the one hand, can reduce on the other hand the sample rate of analog to digital converter.Address this problem, need the device size that strengthens key node to reduce rise and fall time, and the rdy signal is done to enough time delays, guarantee in the situation that process deviation is exported and is ready to when rdy is effective.
In sum, the present invention has reached purpose of design by this embodiment, has realized a kind of asynchronous gradually-appoximant analog-digital converter, have power consumption efficiency high, to electric capacity coupling and the low characteristics of peripheral circuit requirement.The present invention is not limited to above-described embodiment, can be in the situation that do not depart from scope and spirit of the present invention and it is modified and change.
Claims (3)
1. an asynchronous gradually-appoximant analog-digital converter, comprise: sampling network, main capacitance array, attached capacitor array, comparator and logic control circuit; It is characterized in that: the sampling network of main capacitance array is connected respectively to normal phase input end and the reverse input end of difference analogue input signal by two bootstrap type switches; The sampling network of attached capacitor array is connected to the common mode reference voltage of analog input signal by two cmos switches;
An end of the top crown of all electric capacity and the aforementioned bootstrap type switch input comparator that links together in described main capacitance array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of twice, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;
An end of the top crown of all electric capacity and the aforementioned cmos switch input comparator that links together in described attached capacitor array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of four times, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;
Comparator is by comparing the voltage of main capacitance array and attached capacitor array top crown, the signal of exporting comparative result and relatively completing;
Logic control circuit receives from the comparative result of comparator and compares settling signal, correspondingly alternately switch respectively main capacitance array and attached capacitor array until complete all comparisons of once sampling, and then all bottom crown control signals are reset to initial value start to sample next time.
2. asynchronous gradually-appoximant analog-digital converter according to claim 1 is characterized in that: described difference analogue input reference signal at+Vref between-Vref.
3. the asynchronous D conversion method that successively approaches based on asynchronous gradually-appoximant analog-digital converter claimed in claim 1 is characterized in that comprising following several step:
Step 1: the bottom crown control signal of resetting all is initial value;
Step 2: switch one group of control signal that electric capacity is corresponding maximum in attached capacitor array according to comparative result for the first time: if comparative result for just by its output switching is+1/2Vref; If comparative result, for negative, by its output switching is-1/2Vref;
Step 3: after completing steps 2 again according to one group of maximum control signal that electric capacity is corresponding in the comparative result of new round switching main capacitance array: if step 2 comparative result is for just: if this comparative result for just, the operation of switched-3/4Vref; If this comparative result is negative, the operation of switched-1/4Vref; If step 2 comparative result is for negative: if this comparative result for just, the operation of switched+1/4Vref; If this comparative result is negative, the operation of switched+3/4Vref;
Step 4: by that analogy, repetitive cycling step 2 and step 3 until be switched to the main capacitance array and attached capacitor array in one group of minimum electric capacity, then export the binary code relatively obtained and convert signal, finishing this sample conversion process, waiting for and entering next time.
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| CN106656190A (en) * | 2015-11-04 | 2017-05-10 | 瑞昱半导体股份有限公司 | Continuous approximation type analog-to-digital conversion circuit and method therefor |
| CN106656190B (en) * | 2015-11-04 | 2020-02-14 | 瑞昱半导体股份有限公司 | Successive approximation type analog-digital conversion circuit and method thereof |
| CN106656192A (en) * | 2016-10-10 | 2017-05-10 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | ADC chip circuit based on gate voltage bootstrap circuit and segmented full capacitor array |
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