CN102386923B - Asynchronous successive approximation analog-to-digital converter and conversion method - Google Patents

Abstract

The invention discloses an asynchronous successive approximation analog-to-digital converter and a conversion method. The asynchronous successive approximation analog-to-digital converter comprises: a sampling network, a main capacitor array, an auxiliary capacitor array, a comparator and a logic control circuit. The sampling network of the main capacitor array uses a bootstrap switch. The sampling network of the auxiliary capacitor array uses a CMOS switch. Each two same capacitors in the main capacitor array are in a group. A capacitance value size is reduced as two times relationship. Top crowns of all the capacitors and the bootstrap switch are connected and output to the comparator. The each two same capacitors in the auxiliary capacitor array are in one group. The capacitance value size is reduced as four times relationship. The top crowns of all the capacitors and the CMOS switch are connected and output to the comparator. The comparator comprises a preamplifier and a latch and compares the size of an output voltage of the main capacitor array and the auxiliary capacitor array. The logic control circuit uses an asynchronous sequential control capacitor array to successively complete switching. A power consumption efficiency of the analog-to-digital converter can be effectively raised. And demands of capacitor coupling and a peripheral circuit can be reduced. The method is suitable for a deep-submicron low voltage design.

Description

Asynchronous successive approximation analog-to-digital converter and conversion method

technical field

The present invention relates to an asynchronous successive approximation analog-to-digital converter and a conversion method, in particular to an asynchronous successive approximation converter which improves power consumption efficiency, reduces capacitance matching and peripheral circuit requirements by improving the retrieval method, and is suitable for deep submicron low power supply voltage. approximation to the analog-to-digital converter.

technical background

The successive approximation analog-to-digital converter is a type used in medium precision and medium sampling rate. Compared with other types of analog-to-digital converters such as flash type and pipeline type, it has the highest power consumption efficiency. It is widely used in medical and portable equipment. Applications.

The traditional synchronous successive approximation analog-to-digital converter requires a high-speed system clock (sampling frequency times the number of converter resolution digits), whether it is generated internally or directly input from off-chip will increase the extra power consumption of the chip, so that the successive approximation The high power consumption efficiency is greatly reduced.

Since the successive approximation ADC requires the use of capacitor arrays in increments of two, the matching between the smallest and largest capacitors limits the overall accuracy of the ADC. The use of unit capacitance and centrosymmetric layout can reduce the impact of this limitation, but it cannot fundamentally solve this problem. Many designs use digital correction to improve the accuracy of capacitance matching.

The successive approximation analog-to-digital converter successively approximates the final result by switching the reference voltage connected to the lower plate of the capacitor. The charge consumed in the switched capacitor is the main source of power consumption of this type of analog-to-digital converter. Use a more efficient switching method It has also become one of the main research directions to further improve power consumption efficiency.

Contents of the invention

The object of the present invention is to improve the power consumption efficiency of the successive approximation analog-to-digital converter by providing an asynchronous successive approximation analog-to-digital converter and conversion method, improving the approximation search algorithm and using asynchronous timing control, and reducing the capacitance matching and peripheral circuit requirements, And suitable for deep submicron low supply voltage.

The present invention is realized by adopting the following technical means:

An asynchronous successive approximation analog-to-digital converter includes: a sampling network, a main capacitor array, an auxiliary capacitor array, a comparator and a logic control circuit.

The sampling network of the main capacitor array is connected to the positive phase input terminal and the negative input terminal of the differential analog input signal by two bootstrap switches; the sampling network of the attached capacitor array is connected to the common mode of the analog input signal by two CMOS switches reference voltage.

The upper plates of all capacitors in the main capacitor array and one end of the aforementioned bootstrap switch are connected together and input into the comparator; every two identical capacitors form a group, and the lower plate is controlled by the output of the logic control circuit through the inverter , the capacitance value decreases one by one according to the relationship of twice, the bottom plate of the last capacitor is grounded, and the remaining capacitance value required for the correct switching of the capacitor array is completed.

The upper plates of all the capacitors in the attached capacitor array and one end of the aforementioned CMOS switch are connected together to input the comparator; wherein every two identical capacitors form a group, and the lower plate is controlled by the output of the logic control circuit through an inverter, and the capacitor The value decreases one by one according to the relationship of four times, and the bottom plate of the last capacitor is grounded, and the remaining capacitance required for the correct switching of the capacitor array is completed.

The comparator compares the voltages of the plates on the main capacitor array and the auxiliary capacitor array, and outputs a comparison result and a comparison completion signal.

The logic control circuit receives the comparison result and the comparison completion signal from the comparator, alternately switches the main capacitor array and the auxiliary capacitor array respectively until all the comparisons of one sampling are completed, and then resets all the control signals of the lower plate to the initial value Start the next sampling.

An asynchronous successive approximation analog-to-digital conversion method, comprising the following steps:

Step 1: Reset all lower plate control signals to initial values.

Step 2: Switch the control signal corresponding to the largest group of capacitors in the attached capacitor array according to the first comparison result: if the comparison result is positive, switch its output to +1/2Vref (the differential analog input signal range is from +Vref to -Vref); if the comparison is negative, its output is switched to -1/2Vref.

Step 3: After completing step 2, switch the control signal corresponding to the largest group of capacitors in the main capacitor array again according to the new round of comparison results: 1. If the comparison result in step 2 is positive: If the comparison result is positive this time, switch Complete the operation of -3/4Vref; if the result of this comparison is negative, switch to complete the operation of -1/4Vref. 2. If the comparison result in step 2 is negative: if the comparison result is positive, then switch to complete the +1/4Vref operation; if the current comparison result is negative, then switch to complete the +3/4Vref operation.

Step 4: By analogy, repeat step 2 and step 3 until switching to the smallest group of capacitors in the main capacitor array and the auxiliary capacitor array, and then output the binary code obtained by comparison and the conversion completion signal to end the sampling conversion process. Waiting to enter next time.

Every two capacitors in the main capacitor array and the auxiliary capacitor array form a group, one plays the role of adding the reference voltage, and the other plays the role of subtracting the reference voltage, changing the initial value of its control signal during the sampling process can Done.

Compared with the prior art, the present invention has the following obvious advantages and beneficial effects:

The invention uses a successive approximation analog-to-digital converter controlled by asynchronous sequence, works at a low voltage (less than 1 volt), and saves the link of peripheral circuits providing high-speed system clocks. Through the improved approximation search algorithm, the matching requirement of capacitors in traditional analog-to-digital converters of the same type is relaxed to 4 times before, and the power consumption in the process of capacitor switching is reduced. Since the power supply voltage and ground are used for comparing reference voltages, CMOS switches whose on-resistance varies with the signal amplitude and buffers provided in peripheral circuits are no longer required.

In summary, the present invention realizes a low-voltage and low-power asynchronous successive approximation analog-to-digital converter, improves power consumption efficiency, and reduces capacitance matching and peripheral circuit requirements.

Description of drawings

Fig. 1 is a structural block diagram of an asynchronous successive approximation analog-to-digital converter;

Fig. 2 is a circuit diagram of an asynchronous successive approximation analog-to-digital converter in an embodiment of the present invention;

Fig. 3 is the circuit diagram of comparator in the embodiment of the present invention;

4 is a structural diagram of a logic control circuit in an embodiment of the present invention;

FIG. 5 is a circuit diagram of the logic control circuit unit 1 in an embodiment of the present invention;

6 is a circuit diagram of the logic control circuit unit 2 in an embodiment of the present invention;

FIG. 7 is a schematic timing diagram of a comparator in an embodiment of the present invention;

8 is a schematic diagram of simulation results output by the main capacitor array and the auxiliary capacitor array in an embodiment of the present invention;

FIG. 9 is a schematic diagram of a fast Fourier transform simulation result output by an analog-to-digital converter in an embodiment of the present invention.

Symbol Description:

201: main capacitor array; 202: additional capacitor array; 203: bootstrap sampling switch; 204: comparator; 205: logic control circuit;

801: analog input signal; 802: main capacitor array output signal; 803: auxiliary capacitor array output signal.

Specific implementation method

Specific embodiments of the present invention are described below in conjunction with the accompanying drawings:

As shown in FIG. 1 , a structural block diagram of an asynchronous successive approximation analog-to-digital converter of the present invention includes: a sampling network, a main capacitor array, an auxiliary capacitor array, a comparator and a logic control circuit. What is realized in the embodiment of the present invention is an 8-bit successive approximation analog-to-digital converter with a sampling rate of 50 MHz.

Since the input signal of the main capacitor array is an analog signal that changes with time, a bootstrap sampling switch is used; the input signal of the auxiliary capacitor array is a common-mode reference voltage that does not change with time, so a CMOS sampling switch is used.

Figure 2 shows the circuit diagram of the main capacitor array and the additional capacitor array. The main capacitor array consists of 13 capacitors with upper plates connected together, of which the lower plate of one capacitor is grounded, and the size of the capacitor is C*262/3 (C is a unit capacitor), and the other 12 capacitors are a group of two , the lower plate is controlled by the output of the logic control circuit through the inverter, the largest group is 32*C, and the smallest group is 1*C; the attached capacitor array contains 9 capacitors connected together on the upper plate, of which The lower plate of one capacitor is grounded, and the size of the capacitor is C*770/3. The other eight capacitors form a group of two. The lower plate is controlled by the output of the logic control circuit through the inverter. The largest group is 64 *C, the smallest group is 1*C.

Figure 3 shows the circuit diagram of the comparator. The input uses two differential pairs, where IP and IN are the outputs of the main capacitor array, and REF1 and REF2 are the outputs of the additional capacitor array. The left side of Figure 3 is a pre-amplifier, which expands the gap between the voltages to be compared; the right side is a latch (latch), which further widens the gap between the voltages to the power supply voltage and ground. In order to simplify the peripheral circuit, the pre-amplifier does not use a reference current source as bias, but introduces a clock signal to bias through a voltage-controlled current source, so that the amplifier can be turned off to reduce power consumption when amplification is not needed. Likewise, the clock signal turns off the latch when the comparator is not active. The comparison completion signal is obtained by passing the output of the latch through a NOR gate.

Figure 4 shows the structure diagram of the logic control circuit, which is mainly composed of unit 1 and unit 2, in which all unit 1 are cascaded together to give the enable signal of 8 comparisons after one sampling, and unit 2 completes the unit 1 A part of the post-processing function of the output signal. The final combinatorial logic converts the output of unit 2 into the control signals required by the main and auxiliary capacitor arrays. Figure 5 shows the circuit diagram of unit 1, where set and set_next are the interfaces between the current level and the previous level and the next level, rdy is the comparison completion signal, and cmp is the comparator enable signal; Figure 6 shows the unit 2 Circuit diagram, cmp_out is the comparison result of the comparator, rst is the reset signal, which will be valid once before each sampling, set is the output of the OR gate in Figure 4, rdy is the comparison completion signal, and bit is the number to be output by the analog-to-digital converter code. Figure 7 shows the timing diagram of the comparator. The cmp enable signal is active low. After a period of time, the comparator outputs the comparison result cmp_out, and outputs the comparison completion signal rdy after the comparison result is stable.

Figure 8 shows the change of the output signal when the main capacitor array and the auxiliary capacitor array switch the voltage in the case of sinusoidal analog signal input. Power consumption efficiency is improved compared to conventional methods. Fig. 9 is the fast Fourier transform simulation result output by the analog-to-digital converter.

The key to implementing the present invention is to design an asynchronous sequential circuit. Due to the influence of load and parasitic on-line and between-line, there will be different degrees of delay and increase of rise and fall time between each control signal. On the one hand, this problem will affect the asynchronous The realization of the control function, on the other hand, will reduce the sampling rate of the analog-to-digital converter. To solve this problem, it is necessary to increase the device size of key nodes to reduce the rise and fall time, and to delay the rdy signal enough to ensure that the output is ready when rdy is valid under the condition of process deviation.

In summary, the present invention achieves the design purpose through this embodiment, and implements an asynchronous successive approximation analog-to-digital converter, which has the characteristics of high power consumption efficiency and low requirements on capacitance matching and peripheral circuits. The present invention is not limited to the above-described embodiments, and modifications and changes can be made thereto without departing from the scope and spirit of the present invention.

Claims (3)

1. an asynchronous gradually-appoximant analog-digital converter, comprise: sampling network, main capacitance array, attached capacitor array, comparator and logic control circuit; It is characterized in that: the sampling network of main capacitance array is connected respectively to normal phase input end and the reverse input end of difference analogue input signal by two bootstrap type switches; The sampling network of attached capacitor array is connected to the common mode reference voltage of analog input signal by two cmos switches;

An end of the top crown of all electric capacity and the aforementioned bootstrap type switch input comparator that links together in described main capacitance array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of twice, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;

An end of the top crown of all electric capacity and the aforementioned cmos switch input comparator that links together in described attached capacitor array; Wherein every two identical electric capacity are one group, bottom crown passes through inverter controlling by the output of logic control circuit, the capacitance size is successively decreased one by one according to the relation of four times, last electric capacity bottom crown ground connection, the required remaining appearance value of the correct switching of polishing capacitor array;

Comparator is by comparing the voltage of main capacitance array and attached capacitor array top crown, the signal of exporting comparative result and relatively completing;

Logic control circuit receives from the comparative result of comparator and compares settling signal, correspondingly alternately switch respectively main capacitance array and attached capacitor array until complete all comparisons of once sampling, and then all bottom crown control signals are reset to initial value start to sample next time.

2. asynchronous gradually-appoximant analog-digital converter according to claim 1 is characterized in that: described difference analogue input reference signal at+Vref between-Vref.

3. the asynchronous D conversion method that successively approaches based on asynchronous gradually-appoximant analog-digital converter claimed in claim 1 is characterized in that comprising following several step:

Step 1: the bottom crown control signal of resetting all is initial value;

Step 2: switch one group of control signal that electric capacity is corresponding maximum in attached capacitor array according to comparative result for the first time: if comparative result for just by its output switching is+1/2Vref; If comparative result, for negative, by its output switching is-1/2Vref;

Step 3: after completing steps 2 again according to one group of maximum control signal that electric capacity is corresponding in the comparative result of new round switching main capacitance array: if step 2 comparative result is for just: if this comparative result for just, the operation of switched-3/4Vref; If this comparative result is negative, the operation of switched-1/4Vref; If step 2 comparative result is for negative: if this comparative result for just, the operation of switched+1/4Vref; If this comparative result is negative, the operation of switched+3/4Vref;

Step 4: by that analogy, repetitive cycling step 2 and step 3 until be switched to the main capacitance array and attached capacitor array in one group of minimum electric capacity, then export the binary code relatively obtained and convert signal, finishing this sample conversion process, waiting for and entering next time.

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