CN107528592A - The self-built clock circuit of disparate step with delay unit - Google Patents
The self-built clock circuit of disparate step with delay unit Download PDFInfo
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- CN107528592A CN107528592A CN201610456956.1A CN201610456956A CN107528592A CN 107528592 A CN107528592 A CN 107528592A CN 201610456956 A CN201610456956 A CN 201610456956A CN 107528592 A CN107528592 A CN 107528592A
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- comparator
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- 230000000052 comparative effect Effects 0.000 claims abstract description 4
- 238000005070 sampling Methods 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention discloses a kind of self-built clock circuit of disparate step with delay unit, including comparator, the OR gate being connected with the comparator, the nor gate being connected with the OR gate and the delay unit being connected with the nor gate and the comparator, after the comparator is gradually compared the analog signal of input and changed, output digit signals, and the comparative result of each signal is produced to the nor gate by the output end of the OR gate, the delay unit is connected between the nor gate and the comparator, line delay is entered to the signal of nor gate output and produces clock signal to the comparator.The present invention only need to be according to application demand, there is provided sampled signal, can not only save the trouble for providing high-frequency clock, and can realize maximally effective clock distribution, realize high-speed transitions, have a clear superiority in high speed applications.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of self-built clock circuit of disparate step with delay unit.
Background technology
With the high speed development of current electronics technology, the structure of existing integrated circuit is extremely complex, integrated high and function also very
Variation, in face of the growing demand of electronic information technology, whole IC industry is developed rapidly.
In the design of existing chip, Approach by inchmeal (SAR) type analog-to-digital converter is indispensable module in numerous systems,
In gradual approaching A/D converter, it is desirable to provide clock signal of system, control circuit successive appraximation and conversion.Should in high speed
In, this clock frequency can reach GHz, system-level to realize that difficulty is larger, and the clock frequency of fixed cycle can cause to turn
Change waste of time.
The optimal method of high-speed transitions is realized, is to be believed according to the difference for establishing and comparing the time by turn, self-built one of circuit with sampling
The clock signal of the variable period of number disparate step.So system only need to be according to application demand, there is provided sampled signal, can not only save
The trouble of offer high-frequency clock is provided, and maximally effective clock distribution can be realized, realizes high-speed transitions.
Therefore, it is necessary to provide a kind of analog-digital converter high-speed transitions are realized with the self-built clock circuit of disparate step of delay unit
When efficient clock distribution.
The content of the invention
It is an object of the invention to overcome the deficiencies of the prior art and provide a kind of self-built clock circuit of disparate step with delay unit.
The purpose of the present invention is achieved through the following technical solutions：A kind of self-built clock circuit of disparate step with delay unit,
The OR gate that is connected including comparator, with the comparator, the nor gate being connected with the OR gate and with the nor gate and the ratio
The delay unit being connected compared with device, after the comparator is gradually compared the analog signal of input and changed, output digit signals,
And comparative result to the nor gate, the delay unit that each signal is produced by the output end of the OR gate is connected to institute
State between nor gate and the comparator, line delay is entered to the signal of nor gate output and produces clock signal to the comparison
Device.
The comparator includes two inputs and two output ends, the simulation letter that the comparator inputs to described two inputs
Number gradually compared with after conversion, passing through described two output end output digit signals.
The nor gate has the control signal end for the work for being used to control the comparator, in sampling period, the control signal
End is in high level, and at the end of sampling, the control signal end is in low level.
When the control signal end is in high level, the comparator does not work, and the delay unit does not produce clock signal.
When the control signal end is in low level, the comparator is started working, the simulation to the input of described two inputs
Signal is gradually compared with after conversion, passing through described two output end output digit signals.
The beneficial effects of the invention are as follows：Only need to be according to application demand, there is provided sampled signal, can not only save offer high-frequency clock
Trouble, and maximally effective clock distribution can be realized, realize high-speed transitions, have a clear superiority in high speed applications.
Brief description of the drawings
Fig. 1 is the circuit structure diagram for the self-built clock circuit of disparate step that the present invention has delay unit.
Fig. 2 is the signal waveforms for the self-built clock circuit of disparate step that the present invention has delay unit.
Embodiment
Technical scheme is described in further detail below in conjunction with the accompanying drawings, but protection scope of the present invention is not limited to following institute
State.
As shown in figure 1, Fig. 1 is the circuit structure diagram for the self-built clock circuit of disparate step that the present invention has delay unit, it includes
The delay unit that comparator, the OR gate being connected with comparator, the nor gate being connected with OR gate and AND OR NOT gate and comparator are connected,
Wherein, comparator includes two inputs ip, in and two output ends op, on, and nor gate has the work for being used for controlling comparator
The control signal end over of work.
Comparator two inputs ip, in analog signal inputted are gradually compared with conversion after, by two output end op,
On output digit signals, and the comparative result of each signal is produced to nor gate, delay unit by the output end up of OR gate
It is connected between nor gate and comparator, line delay is entered to the signal of nor gate output and produces clock signal ckc to comparator.
The present invention has the concrete operating principle of the self-built clock circuit of disparate step of delay unit as follows：
In sampling period, control signal end over is in high level, i.e. over=" 1 ", by delay unit, clock signal ckc
For low level signal, i.e., self-built clock signal ckc=" 0 ", comparator does not work, and two output ends op, on of comparator are equal
In low level, i.e. op=" 0 ", on=" 0 ", and the output end up of OR gate are in low level, i.e. up=" 0 ", now,
Clock signal ckc is not produced.
At the end of sampling, control signal end over is in low level, i.e. over=" 0 ", the high electricity of output end output of nor gate
Ordinary mail number, that is, " 1 " is exported, by delay unit, clock signal ckc is high level signal, i.e., self-built clock signal ckc=" 1 ",
Comparator is started working, defeated by two after the analog signal of two input ip, in inputs is gradually compared and changed
Go out to hold op, on to export the position digital signal.
The output end up of subsequent OR gate is in high level, i.e. up=" 1 ", the output end of nor gate exports low level signal, i.e., defeated
Go out " 0 ", by delay unit, clock signal ckc is low level signal, i.e., self-built clock signal ckc=" 0 ", comparator is temporary
Stop work and make, two output ends op, on of comparator are in low level, i.e. output recovers op=" 0 ", on=" 0 ".
The output end up of OR gate is in low level, i.e. up=" 0 ", the output end output high level signal of nor gate, that is, exports " 1 ",
By delay unit, clock signal ckc is high level signal, i.e., self-built clock ckc=" 1 ", a new compares cycle are opened again
Begin, two output ends op, on of comparator export the position digital signal.
Circulated with this, carry out comparison conversion by turn, until minimum bit comparison is completed, control signal end over is in high level,
That is over=" 1 ", by delay unit, clock signal ckc is low level signal, i.e., self-built clock signal ckc=" 0 ", than
It is stopped compared with device, two output ends op, on of comparator are in low level, i.e. op=" 0 ", on=" 0 ", and OR gate
Output end up be in low level, i.e. up=" 0 ", wait next sampling period to terminate.
Referring to Fig. 2, Fig. 2 is the signal waveforms for the self-built clock circuit of disparate step that the present invention has delay unit.
Wherein, td is the delay of delay unit, and effect is for the settling time of matching capacitance array, can be established according to different positions
Time difference other actual conditions, carry out configuration delay td.trecovFor comparator break-off, the delay of recovery is exported.tlatchFor
The delay of comparator work, the delay difference of different interdigits is larger, when the simulation letter that two inputs ip, in of comparator are inputted
When number difference is larger, two output ends op, on of comparator output digit signals quickly, tlatch1Very little, the time under saving is just
Following clock cycle can be contributed to, will not cause to waste；When the analog signal that two inputs ip, in of comparator are inputted is poor
When value is smaller, two slower output digit signals of output end op, on of comparator, tlatch2Very big, system will not use fixed clock
Cycle goes to constrain it, comparator can be waited to complete to compare, then start the comparison of next bit.
In summary, the present invention has the self-built clock circuit of disparate step of delay unit only need to be according to application demand, there is provided sampling letter
Number, the trouble that high-frequency clock is provided can be not only saved, and maximally effective clock distribution can be realized, high-speed transitions are realized,
Have a clear superiority in high speed applications.
Claims (5)
- A kind of 1. self-built clock circuit of disparate step with delay unit, it is characterised in that：The disparate step with delay unit Self-built clock circuit includes comparator, the OR gate being connected with the comparator, the nor gate that is connected with the OR gate and with it is described or The delay unit that NOT gate and the comparator are connected, after the comparator is gradually compared the analog signal of input and changed, Output digit signals, and the comparative result of each signal is produced to the nor gate by the output end of the OR gate, it is described to prolong Shi Danyuan is connected between the nor gate and the comparator, is entered line delay to the signal of nor gate output and is produced clock Signal is to the comparator.
- 2. the disparate step self-built clock circuit according to claim 1 with delay unit, it is characterised in that：The comparison Device includes two inputs and two output ends, and the analog signal that the comparator inputs to described two inputs is gradually compared Compared with after conversion, passing through described two output end output digit signals.
- 3. the disparate step self-built clock circuit according to claim 2 with delay unit, it is characterised in that：It is described or non- Door has the control signal end for the work for being used to control the comparator, and in sampling period, the control signal end is in high level, At the end of sampling, the control signal end is in low level.
- 4. the disparate step self-built clock circuit according to claim 3 with delay unit, it is characterised in that：When the control When signal end processed is in high level, the comparator does not work, and the delay unit does not produce clock signal.
- 5. the disparate step self-built clock circuit according to claim 4 with delay unit, it is characterised in that：When the control When signal end processed is in low level, the comparator is started working, and the analog signal of described two inputs input is carried out gradually Compare with after conversion, passing through described two output end output digit signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610456956.1A CN107528592A (en) | 2016-06-22 | 2016-06-22 | The self-built clock circuit of disparate step with delay unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610456956.1A CN107528592A (en) | 2016-06-22 | 2016-06-22 | The self-built clock circuit of disparate step with delay unit |
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| CN107528592A true CN107528592A (en) | 2017-12-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110535470A (en) * | 2019-08-26 | 2019-12-03 | 中国电子科技集团公司第二十四研究所 | A kind of comparator clock generation circuit and high speed gradual approaching A/D converter |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386923A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Asynchronous successive approximation analog-to-digital converter and conversion method |
| CN103684465A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Multiphase clock generating circuit for asynchronous successive approximation analog/digital converter |
| US20150042500A1 (en) * | 2013-08-07 | 2015-02-12 | Renesas Electronics Corporation | Semiconductor device |
| CN205754284U (en) * | 2016-06-22 | 2016-11-30 | 成都锐成芯微科技有限责任公司 | There is the self-built clock circuit of disparate step of delay unit |
-
2016
- 2016-06-22 CN CN201610456956.1A patent/CN107528592A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102386923A (en) * | 2011-09-21 | 2012-03-21 | 北京工业大学 | Asynchronous successive approximation analog-to-digital converter and conversion method |
| US20150042500A1 (en) * | 2013-08-07 | 2015-02-12 | Renesas Electronics Corporation | Semiconductor device |
| CN103684465A (en) * | 2013-12-20 | 2014-03-26 | 清华大学 | Multiphase clock generating circuit for asynchronous successive approximation analog/digital converter |
| CN205754284U (en) * | 2016-06-22 | 2016-11-30 | 成都锐成芯微科技有限责任公司 | There is the self-built clock circuit of disparate step of delay unit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110535470A (en) * | 2019-08-26 | 2019-12-03 | 中国电子科技集团公司第二十四研究所 | A kind of comparator clock generation circuit and high speed gradual approaching A/D converter |
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