CN205754284U

CN205754284U - There is the self-built clock circuit of disparate step of delay unit

Info

Publication number: CN205754284U
Application number: CN201620620666.1U
Authority: CN
Inventors: 连颖
Original assignee: CHENGDU RUICHENG XINWEI TECHNOLOGY Co Ltd
Current assignee: Chengdu Rui core micro Polytron Technologies Inc
Priority date: 2016-06-22
Filing date: 2016-06-22
Publication date: 2016-11-30
Anticipated expiration: 2026-06-22

Abstract

The utility model discloses a kind of self-built clock circuit of disparate step with delay unit, including comparator, that be connected with described comparator or door, the nor gate being connected with described or door and the delay unit being connected with described nor gate and described comparator, the analogue signal of input is gradually compared and after conversion by described comparator, output digit signals, and produce the comparative result of each signal to described nor gate by described or door outfan, described delay unit is connected between described nor gate and described comparator, the signal exporting described nor gate carries out time delay and produces clock signal to described comparator.This utility model only need to be according to application demand, it is provided that sampled signal, is possible not only to save the trouble providing high-frequency clock, and can realize maximally effective clock distribution, it is achieved high-speed transitions, has a clear superiority in high speed applications.

Description

There is the self-built clock circuit of disparate step of delay unit

Technical field

This utility model relates to integrated circuit fields, particularly relates to a kind of self-built clock of disparate step with delay unit Circuit.

Background technology

Along with the high speed development of current electronics technology, the structure of existing integrated circuit height extremely complex, integrated and merit Can be the most diversified, in the face of the growing demand of electronic information technology, whole IC industry is developed rapidly.

In existing chip designs, Approach by inchmeal (SAR) pattern number converter is indispensable mould in numerous system Block, in gradual approaching A/D converter, it is desirable to provide clock signal of system, control circuit successive appraximation and conversion.At height In speed application, this clock frequency can reach GHz, and system-level to realize difficulty relatively big, and the clock frequency of fixed cycle can be made Become conversion waste of time.

Realize the method that high-speed transitions is optimal, be according to the difference setting up and comparing the time by turn, circuit self-built one with The clock signal of the variable period of the disparate step of sampled signal.So system only need to be according to application demand, it is provided that sampled signal, not only The trouble that high-frequency clock is provided can be saved, and maximally effective clock distribution can be realized, it is achieved high-speed transitions.

Therefore, it is necessary to provide a kind of there is the self-built clock circuit of disparate step of delay unit to realize analog-digital converter height Efficient clock distribution during speed conversion.

Utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, it is provided that a kind of have the disparate step of delay unit certainly Build clock circuit.

The purpose of this utility model is achieved through the following technical solutions: a kind of have the disparate step of delay unit certainly Build clock circuit, including comparator, be connected with described comparator or door, the nor gate being connected with described or door and with described or The delay unit that not gate and described comparator are connected, the analogue signal of input is gradually compared and conversion by described comparator After, output digit signals, and produce the comparative result of each signal to described nor gate, institute by described or door outfan Stating delay unit to be connected between described nor gate and described comparator, the signal exporting described nor gate carries out time delay and produces Generating clock signal is to described comparator.

Described comparator includes two inputs and two outfans, and said two input is inputted by described comparator Analogue signal gradually compares and after conversion, by said two outfan output digit signals.

Described nor gate has the control signal end of the work for controlling described comparator, in sampling period, described control Signal end processed is in high level, and at the end of sampling, described control signal end is in low level.

When described control signal end is in high level, described comparator does not works, and described delay unit does not produce clock Signal.

When described control signal end is in low level, described comparator is started working, and inputs said two input Analogue signal gradually compare with conversion after, by said two outfan output digit signals.

The beneficial effects of the utility model are: only need to be according to application demand, it is provided that sampled signal, are possible not only to save offer The trouble of high-frequency clock, and maximally effective clock distribution can be realized, it is achieved high-speed transitions, have the most excellent in high speed applications Gesture.

Accompanying drawing explanation

Fig. 1 is the circuit structure diagram that this utility model has the self-built clock circuit of disparate step of delay unit.

Fig. 2 is the signal waveforms that this utility model has the self-built clock circuit of disparate step of delay unit.

Detailed description of the invention

The technical solution of the utility model is described in further detail below in conjunction with the accompanying drawings, but protection domain of the present utility model It is not limited to the following stated.

As it is shown in figure 1, Fig. 1 is this utility model, there is the circuit structure of the self-built clock circuit of disparate step of delay unit Figure, it include comparator, be connected with comparator or door, with or the nor gate that is connected of door and AND OR NOT gate and comparator connected Delay unit, wherein, comparator includes two inputs ip, in and two outfans op, on, and nor gate has for controlling ratio The control signal end over of the work of relatively device.

The analogue signal that two inputs ip, in input gradually is compared and after conversion by comparator, defeated by two Go out to hold op, on output digit signals, and by or the outfan up of door produce the comparative result of each signal to nor gate, prolong Shi Danyuan is connected between nor gate and comparator, carries out the signal of nor gate output time delay and produces clock signal ckc extremely Comparator.

The specific works principle of the self-built clock circuit of disparate step that this utility model has delay unit is as follows:

In sampling period, control signal end over is in high level, i.e. over=" 1 ", through delay unit, clock signal Ckc is low level signal, the most self-built clock signal ckc=" 0 ", and comparator does not works, and two outfans op, on of comparator are equal Be in low level, i.e. op=" 0 ", on=" 0 ", and or the outfan up of door be in low level, i.e. up=" 0 ", now, do not produce Clock signal ckc.

At the end of sampling, control signal end over is in low level, i.e. over=" 0 ", the outfan output of nor gate High level signal, i.e. output " 1 ", through delay unit, clock signal ckc is high level signal, the most self-built clock signal ckc= " 1 ", comparator is started working, and gradually compares the analogue signal of two input ip, in inputs and after conversion, by two Individual outfan op, on export this position digital signal.

Subsequently or the outfan up of door is in high level, i.e. up=" 1 ", the outfan output low level signal of nor gate, I.e. output " 0 ", through delay unit, clock signal ckc is low level signal, the most self-built clock signal ckc=" 0 ", comparator Break-off, two outfans op, on of comparator are in low level, i.e. export and recover op=" 0 ", on=" 0 ".

Or the outfan up of door is in low level, i.e. up=" 0 ", the outfan output high level signal of nor gate, the most defeated Going out " 1 ", through delay unit, clock signal ckc is high level signal, the most self-built clock ckc=" 1 ", and new one is compared In the cycle, two outfans op, on of comparator export this position digital signal.

Circulating with this, carry out comparison conversion by turn, until lowest order has compared, control signal end over is in high electricity Flat, i.e. over=" 1 ", through delay unit, clock signal ckc is low level signal, the most self-built clock signal ckc=" 0 ", than Relatively device quits work, and two outfans op, on of comparator are in low level, i.e. op=" 0 ", on=" 0 ", and or door defeated Go out and hold up to be in low level, i.e. up=" 0 ", wait that next sampling period terminates.

Referring to Fig. 2, Fig. 2 is the signal waveform that this utility model has the self-built clock circuit of disparate step of delay unit Figure.

Wherein, td is the time delay of delay unit, and effect is to set up the time for matching capacitance array, can be according to not coordination Set up the other practical situation of time difference, carry out configuring time delay td.t_recovFor comparator break-off, the time delay that output recovers. t_latchFor the time delay of comparator work, the time delay difference of different interdigits is relatively big, when two input ip, in inputs of comparator When analogue signal difference is bigger, two outfan op, on quickly output digit signals of comparator, t_latch1The least, under saving Time just can contribute to following clock cycle, does not results in waste；Simulation when two input ip, in inputs of comparator When signal difference is less, two slower output digit signals of outfan op, on of comparator, t_latch2Very big, system will not be with solid Clock cycle goes to retrain it, can wait that comparator completes to compare, then start the comparison of next bit.

In sum, this utility model have the self-built clock circuit of disparate step of delay unit only need to according to application demand, Sampled signal is provided, is possible not only to save the trouble that high-frequency clock is provided, and maximally effective clock distribution can be realized, it is achieved High-speed transitions, has a clear superiority in high speed applications.

Claims

1. the self-built clock circuit of disparate step with delay unit, it is characterised in that there is described in: the disparate of delay unit Walk self-built clock circuit include comparator, be connected with described comparator or door, the nor gate being connected with described or door and with institute Stating the delay unit that nor gate and described comparator are connected, the analogue signal of input is gradually compared and turns by described comparator After changing, output digit signals, and the comparative result extremely described nor gate of each signal is produced by described or door outfan, Described delay unit is connected between described nor gate and described comparator, and the signal exporting described nor gate carries out time delay also Produce clock signal to described comparator.

The self-built clock circuit of disparate step with delay unit the most according to claim 1, it is characterised in that: described comparison Device includes two inputs and two outfans, and the analogue signal that said two input is inputted by described comparator is carried out gradually Relatively with conversion after, by said two outfan output digit signals.

The self-built clock circuit of disparate step with delay unit the most according to claim 2, it is characterised in that: described or non- Door has the control signal end of the work for controlling described comparator, and in sampling period, described control signal end is in high electricity Flat, at the end of sampling, described control signal end is in low level.

The self-built clock circuit of disparate step with delay unit the most according to claim 3, it is characterised in that: when described control When signal end processed is in high level, described comparator does not works, and described delay unit does not produce clock signal.

The self-built clock circuit of disparate step with delay unit the most according to claim 4, it is characterised in that: when described control When signal end processed is in low level, described comparator is started working, to said two input input analogue signal carry out by Secondary compare with conversion after, by said two outfan output digit signals.