CN101350612B - Circuit for preventing gating clock bur - Google Patents

Circuit for preventing gating clock bur Download PDF

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Publication number
CN101350612B
CN101350612B CN2007101191190A CN200710119119A CN101350612B CN 101350612 B CN101350612 B CN 101350612B CN 2007101191190 A CN2007101191190 A CN 2007101191190A CN 200710119119 A CN200710119119 A CN 200710119119A CN 101350612 B CN101350612 B CN 101350612B
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China
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clock
signal
gate
circuit
input
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CN2007101191190A
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CN101350612A (en
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郑晓光
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Beijing CEC Huada Electronic Design Co Ltd
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Beijing CEC Huada Electronic Design Co Ltd
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Abstract

The present invention provides a circuit, which is used for preventing clock-gating glitches in the processing circuit of no-working clock in the design of low power consumption. The circuit adopts different clock edges to realize the clock switching control, effectively eliminates the potential competition in the clock switching process, and thus achieves the purpose of preventing the clock from generating the glitches in the gating process. No-working clock is generally applied in the design of low power consumption; the glitches appear in the switching process between the no-working clock and the novel provision of the clock; the circuit can be used for preventing the glitches in the switching process of clocks, and improving the stability and reliability of the circuit.

Description

A kind of circuit that prevents gating clock bur
Technical field
When the present invention is mainly used in low power dissipation design, need carry out in the circuit of stopping time clock processing clock.Can be used for that the control chip used in IC card chip, the portable consumer electron-like etc. is various to be had in the integrated circuit (IC) design that low-power consumption requires, also can be used for avoiding the chip of high speed operation to produce excessive temperature, thereby improve product reliability.
Background technology
Along with the application of portable consumer electronic product is increasingly extensive, power problems is more and more outstanding.For the pursuit of satisfying the user demand of new experience more, increasing function is integrated in the portable product, to the performance requirement of product also than high many in the past.The lifting of these functions and performance all can consume more energy.In battery powered portable product, except function and performance, also be the factor that will consider emphatically the service time of battery.Simultaneously, the restriction of system cost also makes the designer more and more pay close attention to low power dissipation design.At integrated circuit card, especially in the application of non-contact card, the energy that card-reading apparatus can provide is limited, in order to guarantee integrated circuit card energy operate as normal, also requires IC card chip to reduce power consumption.
In some high-end product fields, even without the restriction of battery service time and the extraneous energy that can provide, power problems also needs careful processing.Higher power consumption can cause the obvious increase of chip cooling design difficulty and heat radiation and packaging cost, and chip reliability also obviously descends.Too high temperature can cause the drift of electrical quantity, the inefficacy of device and the fault of relevant encapsulation.
Along with the puzzlement of variety of problems such as electronic product environmental pollution, energy resource consumption excessive velocities, the whole world reaches unprecedented height to environmental protection and energy-conservation concern.National governments also launch respectively policy, formulate " green " rules of oneself.Low power dissipation design is for saving social resources, and cutting down the consumption of energy also has realistic meaning.
In electronic product, integrated circuit (IC) chip is important part, and the power consumption of chip has determined the power consumption of entire product to a great extent.So in chip design, low power dissipation design has become a particular study field.
Low power dissipation design need be considered in different design phases such as system structure design, circuit design, layout design, technological designs.General low power dissipation design of carrying out in the system structure design stage is to saving the contribution maximum of power consumption.Gated clock is one and very effectively also is to use maximum Low-power Technology.In a certain period, with not needing the module of work to carry out Clock gating during this period of time, neither influence function, can save power consumption to greatest extent again.
Increase along with design scale, the method for designing of current trend, it generally is Synchronization Design, promptly generate one or several main work clock and asynchronous reset signal by the clock and the administration module that resets, the trigger groundwork of all modules is under these several clocks and reset signal, rather than each trigger all has oneself clock and asynchronous reset signal.In Synchronization Design, fairly simple feasible because most trigger all is operated under the identical clock for the gate of main work clock, and save the effect highly significant of power consumption.
Summary of the invention
Content of the present invention has been to realize a kind of circuit that prevents gating clock bur.In low power design technique, gated clock is effective design means.In entire circuit, comprised a plurality of functional modules, the dynamic power consumption that the transistor upset produces is its main power consumption, accounts for 80%.But be not that each functional module all needs to work always, in a certain period, possible some module does not need work, and in the period, has other modules not need work at another section again.This just need or not the module clock of work to carry out gate certain period according to the condition of work of each module.Clock behind the gate no longer overturns, and keeps a fixed level, and this clock-driven module just can not produce dynamic power consumption.
In the Synchronization Design, the flip-flop operation of the overwhelming majority is under the same clock edge of same clock.As shown in Figure 1, general gating circuit is two-way gate of design between original clock (Clock) and fixed level (high level, low level all can, Fig. 1 is example with the high level).When the gate condition satisfied, the gated clock of output (ClockGated) was a fixed level.Because gate enable signal (GateEnable) is same along driving by clock, as having competition between the original clock of one of input and the gate-control signal.This competition and then may produce burr.Fig. 2 is the timing waveform of circuit shown in Figure 1.Trailing edge (as shown in phantom in Figure 2 constantly) at the gate enable signal, because the delay of clock signal transmission, the rising edge of original clock might be than taking place behind the gate enable signal trailing edge, and this will cause " burr " on the gated clock shown in Fig. 2.Burr on the clock can allow the stability of entire circuit work and reliability reduce greatly.
Main thought of the present invention is the competition of importing between original clock and the gate-control signal by eliminating, thereby eliminates the burr on the gated clock of exporting.Because the gate enable signal has rising edge (entering low-power consumption mode) and trailing edge (withdrawing from low-power consumption mode),, then can't eliminate two of gate enable signals certainly simultaneously along last competition if the gate enable signal is generated by the same edge of clock.The circuit of the present invention design can generate such gate enable signal: the gate enable signal uprises level at the rising edge of clock by low level, at the trailing edge of clock by high level step-down level.The rising edge of gate enable signal and trailing edge all are consistent with the original clock of importing like this, have eliminated the competition in the combinational logic circuit, also just burr can not occur again on the gate-control signal of output.
Burr can appear on the gated clock that general gating circuit generates.Burr on the clock can make circuit some error conditions occur, greatly influences the stability and the reliability of entire circuit work.Utilize circuit provided by the invention to carry out the design of gated clock, then can eliminate the burr on the gated clock, improve the stability and the reliability of circuit working.
Description of drawings
The gating circuit that Fig. 1 is general
The waveform of the general gating circuit of Fig. 2
Fig. 3 prevents the circuit of gating clock bur
Fig. 4 prevents the waveform of gating clock bur circuit
Fig. 5 prevents the low level gating circuit of burr
Embodiment
Fig. 3 is a circuit structure diagram of the present invention.Circuit of the present invention mainly is in order to produce a door controling clock signal that can not produce burr.
At synchronization, if the input signal of a combinational logic gate has two or more generation state changes simultaneously, because these input signals are to produce through different paths, make that their states change the time be carved with tiny time order and function difference, this difference may cause some of short duration intermediatenesses on the output result signal, forms burr.These burrs may produce some results that do not expect, and propagate backward through circuit, cause the mistake on the entire circuit function.The present invention is by the sequential of design gate enable signal, competition between two input signals of original clock of elimination gate enable signal and input, avoid taking place at the same instant the upset on the both direction, which takes place earlier regardless of the upset on two input signals, also can not cause exporting occurring burr on the gated clock.
In fact, during Clock gating, can allow gated clock remain on high level, also can allow gated clock remain on low level.Here remaining on high level with gated clock during the gate is example, and the embodiment of circuit of the present invention is described.Circuit is out of shape a little, can realizes allowing that gated clock remains on low level during the gate.
Gated clock will remain on high level during the gate, must make the gate enable signal effective by the invalid level that uprises of low level at the original clock rising edge of input, enters low-power consumption mode; Original clock trailing edge in input makes the gate enable signal invalid by the effective step-down level of high level, withdraws from low-power consumption mode.
The present invention has designed circuit as shown in Figure 3, and Fig. 4 is the timing waveform of circuit shown in Figure 3.Designed the d type flip flop 1 and 3 of two cascades in the circuit.Trigger 1 is driven by the rising edge of clock Clock signal.After the gate condition satisfied, it is effective that Input becomes high level, and trigger 1 latchs the Input signal at the rising edge of clock Clock signal, produces signal a.The Clock signal through inverter 2 carry out anti-phase after, as the clock of trigger 3.Trigger 3 latchs a signal at the trailing edge of clock Clock signal, produces signal b.Signal a and signal b carry out OR operation through logic sum gate 4, generate gate enable signal GateEnable.
Because a signal changes in different moment point with the b signal, there is not competition, so the GateEnable signal can not produce burr certainly.As shown in Figure 4, the GateEnable signal becomes effectively at the rising edge of Clock, neutralizes at the trailing edge of Clock.
The GateEnable signal is as the gating control end of two-way selector 5, and two-way selector 5 is output as the clock signal C lockGated behind the gate.When GateEnable was 0, gating Clock signal was as output; When GateEnable was 1, expression need be carried out gate to clock, gating fixedly high level as output.
The moment that constantly can produce burr shown in the dotted line among Fig. 4 for general gating circuit.As seen from the figure, through after the processing of circuit shown in Figure 3, no matter which arrives earlier for the trailing edge of Clock and GateEnable signal, burr can not appear on the gate-control signal that all guarantees to export.
The front has been introduced and has been allowed gated clock remain on the embodiment of the circuit of high level during gate.Circuit among Fig. 3 is out of shape a little, forms circuit as shown in Figure 5, allow gated clock remain on low level during can be implemented in gate.
The present invention can effectively prevent to occur on the gated clock burr, improves the stability and the reliability of circuit.

Claims (3)

1. a circuit that prevents gating clock bur is characterized in that utilizing different clock edges to carry out the clock switching controls, effectively prevents from burr to occur in stopping time clock and the handoff procedure of supplying with clock again, comprising:
A clock is just along the d type flip flop that triggers, and clock signal is as the clock input of this trigger, and the gate input signal connects the D input of this trigger, on the just edge of clock signal, utilizes this d type flip flop that the gate input signal is latched, and generates signal a;
The d type flip flop that the clock negative edge triggers, clock signal is as the clock input of this trigger, and signal a imports the D input of this trigger, in the negative edge of clock signal, utilizes this d type flip flop that signal a is latched, and generates signal b;
A logic sum gate, signal a and signal b carry out OR operation through logic sum gate, generate the gate enable signal;
A two-way selector, the gate enable signal is as the gating control end of two-way selector, and the two-way selector is output as the clock signal behind the gate.
2. the circuit that prevents gating clock bur according to claim 1, it is characterized in that when the gate input signal changes, signal a just changes on the edge in clock signal, signal b changes in the clock signal negative edge, the gate enable signal that signal a and signal b generate through logic sum gate, just effective in clock signal along uprising, negative edge step-down in clock signal is invalid, when gate enable signal and clock signal change, eliminated the competition of logic sum gate two-way input, thereby made the output of logic sum gate can not produce burr.
3. the circuit that prevents gating clock bur as claimed in claim 1 is characterized in that when the gate enable signal was 0, the gated clock signal was as output; When the gate enable signal is 1, clock is carried out gate, gating fixedly high level as output.
CN2007101191190A 2007-07-16 2007-07-16 Circuit for preventing gating clock bur Expired - Fee Related CN101350612B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2007101191190A CN101350612B (en) 2007-07-16 2007-07-16 Circuit for preventing gating clock bur

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Application Number Priority Date Filing Date Title
CN2007101191190A CN101350612B (en) 2007-07-16 2007-07-16 Circuit for preventing gating clock bur

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CN101350612A CN101350612A (en) 2009-01-21
CN101350612B true CN101350612B (en) 2010-08-04

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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102111127B (en) * 2009-12-23 2013-05-15 北京中电华大电子设计有限责任公司 Signal count delay method and circuit in chip electrifying process
CN102857198B (en) * 2012-08-30 2015-09-30 锐迪科科技有限公司 For the clock gating circuit of dual-edge trigger
CN104852712A (en) * 2015-05-19 2015-08-19 中国电子科技集团公司第四十七研究所 Low-power-consumption gated clock circuit structure based on data variation
CN105141286B (en) * 2015-10-16 2018-08-03 成都默一科技有限公司 Filter out the digital filter of one clock period pulse and burr
CN107632958B (en) * 2017-09-26 2021-01-26 北京融通高科微电子科技有限公司 Signal processing device and system
CN107947767A (en) * 2017-11-16 2018-04-20 湖南工业大学 Pulse signal circuit disturbing pulse sampling type filtering method
CN110690886A (en) * 2019-09-25 2020-01-14 华大半导体有限公司 1-out-of-n circuit and pin multiplexer with same
CN114417760B (en) * 2022-01-28 2022-11-08 杭州士兰微电子股份有限公司 Trigger unit comprising clock gating circuit

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Address after: 102209 Beijing, Beiqijia, the future of science and technology in the south area of China electronic network security and information technology industry base C building,

Patentee after: Beijing CEC Huada Electronic Design Co., Ltd.

Address before: 100102 Beijing City, Chaoyang District Lize two Road No. 2, Wangjing science and Technology Park A block five layer

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Granted publication date: 20100804

Termination date: 20200716