CN104917517B

CN104917517B - For realize low-power consumption, Wide measuring range time-to-digit converter energy-saving circuit

Info

Publication number: CN104917517B
Application number: CN201510360954.8A
Authority: CN
Inventors: 张雪皎; 郑立荣
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2015-06-26
Filing date: 2015-06-26
Publication date: 2018-04-03
Anticipated expiration: 2035-06-26
Also published as: CN104917517A

Abstract

It is specially a kind of to be used to realize low-power consumption, the energy-saving circuit of Wide measuring range time-to-digit converter the invention belongs to technical field of integrated circuits.The circuit is made up of time window generation circuit and enabled circuit；Time window generation circuit includes two triggers, a phase inverter and one and door, it by detect simultaneously digital controlled oscillator output CKV rise and fall along producing corresponding enable signal, and then drive the corresponding data-signal entry time digital quantizer of enabled circuit generation.The energy-saving circuit can not only greatly reduce the power consumption of rear class delay chain time-to-digit converter, and can avoid limitation of the legacy windows energy-saving circuit to TDC incoming frequencies, it is realized Wide measuring range.

Description

For realize low-power consumption, Wide measuring range time-to-digit converter energy-saving circuit

Technical field

The invention belongs to technical field of integrated circuits, and in particular to one kind is used to realize low-power consumption, Wide measuring range time The energy-saving circuit of digital quantizer.

Background technology

The reduction of evolution and technology feature size recently as integrated technique technology, the signal transacting in conventional voltage domain Mode is greatly challenged, and the time resolution of circuit improves constantly.Time-domain process circuit and mixing domain system can be abundant The advantage of Advanced CMOS Process is played, has attracted the concern of more and more researchers, all-digital phase-locked loop（All Digital Phase Locked Loop, ADPLL）It is one of typical case.With the development of CMOS technology, all-digital phase-locked loop Performance can be compared favourably with traditional analog phase-locked look, can be very easily simultaneously because the characteristic of its digital circuit Other digital assistant circuits are added, but how further to realize that low-power consumption and broadband remain the emphasis of research.Time number Word converter（Time-to-digital Converter）As one of key modules, its power consumption determines digital The total power consumption of phaselocked loop, especially delay chain time-to-digit converter in, delay unit high frequency input drive under not Disconnected upset, consumes extra power consumption.In order to improve power consumption, time window energy-saving circuit can be used.

Traditional time window energy-saving circuit is only made up of two simple gates.However, because time window enables The width of signal is determined by total delay of time delay chain, and ADPLL output frequency can similarly be limited.In addition, using one It is individual with door as enabled circuit there may be wrong rising edge, cause the mistake of quantized result.

The content of the invention

It is an object of the invention to provide it is a kind of be used for realize low-power consumption, Wide measuring range time-to-digit converter electricity-saving Road.

Provided by the present invention for realize low-power consumption, Wide measuring range time-to-digit converter energy-saving circuit, by the time Window generation circuit and enabled circuit are formed.Wherein, time window generation circuit by detecting digital controlled oscillator simultaneously（DCO）'s CKV rise and fall are exported along producing corresponding enable signal, and then drives enabled circuit to produce corresponding data-signal and enters Angle of incidence digital quantizer.

Time window generation circuit includes two-stage trigger, a phase inverter and one and door.Reference clock REF conducts The data terminal of first order trigger, the clock end of DCO output CKV as first order trigger；The positive of first order trigger The data terminal as second level trigger is exported, DCO output CKV is used as second level trigger by the signal after phase inverter Clock end；The reversed-phase output of REF and second level trigger is as the input with door；Output with door is that time window produces The output enable signal of circuit.

The principle that time window generation circuit produces enable signal is as follows：First order trigger is adopted by CKV rising edge Sample REF obtains the rising edge of first CKV after REF rising edges；Then it is anti-phase to CKV, second level trigger CKV trailing edge The positive of sampling first order trigger exports to obtain first trailing edge after first rising edge of CKV；Touch the final second level The reversed-phase output of hair device is with REF phases with obtaining final enable signal EN.Because the width of this enable signal is by CKV ripples What shape determined, be no longer fixed value, therefore no matter CKV frequency size, enable signal all at least can allow the CKV of a cycle to lead to Cross.

Obtained enable signal is further used as the input of enabled circuit.Enabled circuit is by a trigger and one and door Form：Data terminals of the enable signal EN as trigger, clock ends of the CKV as trigger；The positive output of trigger and CKV As the input with door；Output with door is the final output of energy-saving circuit.Its operation principle is：CKV is adopted by trigger Sample EN, then it can obtain the CKV rising edges in time window signal；Then, trigger is exported with CKV in itself mutually with finally giving The CKV ' of CKV rising edges and cycle information is carried, the input as time-to-digit converter measurement.

Energy-saving circuit of the present invention can not only greatly reduce the power consumption of rear class delay chain time-to-digit converter, Er Qieke To avoid limitation of the legacy windows energy-saving circuit to TDC incoming frequencies, it is set to realize Wide measuring range.

Brief description of the drawings

Time window energy-saving circuit figure traditional Fig. 1.

Time window energy-saving circuit figure in Fig. 2 present invention.

The time waveform figure of Fig. 3 energy-saving circuits.Wherein,（a）Time window enable signal produces principle,（b）Only with door As the final output of enabled circuit,（c）Using the final output of trigger+and door as enabled circuit.

The simulation waveform of Fig. 4 energy-saving circuit modules.

The relation curve of Fig. 5 time-to-digit converter overall power vs frequencies.

Embodiment

Illustrate below in conjunction with the accompanying drawings：

As shown in figure 1, traditional time window energy-saving circuit is to utilize reference clock and its signal after total delay Build a time window, rising edge cycle in time window can be by, and the invalid signals outside window can not enter Enter time delay chain, so as to effectively reduce the dynamic power consumption of time delay chain.It is only made up of two doors, and XOR gate is used for generation time window As the Enable Pin with door.However, because the width of time window is determined by total delay of time delay chain, ADPLL output Frequency can similarly be limited.In addition, using one with door as enabled device there may be mistake rising edge, cause to quantify As a result mistake.

As shown in Fig. 2 be the time window energy-saving circuit in the present invention, the rising of the output CKV by detecting DCO simultaneously Trailing edge produces corresponding enable signal.It is made up of a time window generation circuit and enabled circuit.Time window produces Raw circuit includes two triggers, a phase inverter and one and door, its operation principle：After the arrival of REF rising edges, First trailing edge after first rising edge of CKV is detected, so as to by with REF phases and obtaining final enable signal EN. The width of this enable signal is determined by CKV waveforms, is no longer fixed value, therefore no matter CKV frequency size, enable signal All at least the CKV of half period can be allowed to pass through.On the other hand, no longer merely use with door as enabled circuit, but add Trigger, avoids the generation of wrong rising edge.

Fig. 3 shows the time waveform figure of energy-saving circuit.Because EN signals can be changed into CKV falling edge from high level Low level, so the CKV in an only effective period enters in quantizer below.When REF rising edges arrive, EN signals It is changed into high level, TDC proceeds by measurement；When EN signals are changed into low level, TDC just no longer works.From Fig. 3（b）In may be used also To find out, only with door when, a wrong rising edge can be produced, cause the error of quantized result.And in Fig. 3（c）Middle addition After one trigger, CKV sampling enable signals EN is utilized, it is possible to obtain accurate CKV rising edges；Effect with door is production Raw CKV cycle, to ensure that final fractional frequency division ratio can be obtained.By using such energy-saving circuit, bag is finally given The gating signal CKV_P of information containing rising time and CKV cycle informations.

It is applied to time-to-digit converter in 1.2GHz ~ 1.8GHz broadband A/Ds PLL using one below and observes section as example The function and performance of energy circuit.

Fig. 4 is the functional simulation to energy-saving circuit, it can be found that time window energy-saving circuit is by unnecessary CKV from figure Cycle filters out, and a cycle signal for needing to participate in subsequent quantizatiion is left behind, so as to greatly save power consumption.Also shown in figure CKV adds path delay after have passed through energy-saving circuit, accordingly, same path delay should be also added to REF, basic to keep Unanimously.

Fig. 5 considers the power consumption of whole time-to-digit converter system.In order to embody the effect of window energy-saving circuit, respectively The energy consumption of time-to-digit converter to whetheing there is energy-saving circuit emulates, and finally gives the comparison diagram of two results.On in figure What the broken line of side represented is the power consumption for not adding window energy-saving circuit, and the broken line expression of lower section is to the addition of window electricity-saving The power consumption on road.Power consumption emulation is to have carried out frequency sweep to 1.2-1.8GHz working frequency with 0.05GHz, and the time interval of measurement is all It has chosen 400ps.By Fig. 5 it can be found that the power consumption that top broken line represents increases with the increase of frequency, this is due to not There is addition window energy-saving circuit, all data cycles are all entered in time figure converter, and frequency is higher, then phase inverter turns over The number turned is more, and the total power consumption consumed is bigger.And the lower section broken line of window energy-saving circuit is added, although having slight Ground increases, but the power consumption of different incoming frequencies is essentially identical.Two broken lines are contrasted, window energy-saving circuit is added and make it that power consumption is big Reduce greatly, and as frequency is higher, Save power consumption must be more, when input is 1.8GHz, power consumption almost drops to original 50%。

Claims

1. a kind of be used to realize low-power consumption, the energy-saving circuit of Wide measuring range time-to-digit converter, it is characterised in that by the time Window generation circuit and enabled circuit are formed；Wherein, time window generation circuit is by detecting the output of digital controlled oscillator simultaneously CKV rise and fall along producing corresponding enable signal, and then drive enabled circuit produce corresponding data-signal enter it is fashionable Between digital quantizer；

The time window generation circuit includes two-stage trigger, a phase inverter and one and door；Reference clock REF conducts The data terminal of first order trigger, the clock end of the output CKV of digital controlled oscillator as first order trigger；First order trigger Positive export data terminal as second level trigger, the output CKV of digital controlled oscillator is used as by the signal after phase inverter The clock end of second level trigger；The reversed-phase output of reference clock REF and second level trigger is as the input with door；With door Output be time window generation circuit output enable signal；

The enabled circuit is made up of a trigger and one with door；Data terminals of the enable signal EN as trigger, numerical control Clock ends of the output CKV of oscillator as trigger；Trigger positive output and digital controlled oscillator output CKV as with The input of door；Output with door is the final output of energy-saving circuit.

2. energy-saving circuit according to claim 1, it is characterised in that：

The process that time window generation circuit produces enable signal is as follows：First order trigger samples REF by CKV rising edge Obtain the rising edge of first CKV after REF rising edges；Then anti-phase to CKV, second level trigger is sampled with CKV trailing edge The positive of first order trigger exports to obtain first trailing edge after first rising edge of CKV；Final second level trigger Reversed-phase output and REF phases and obtain final enable signal EN；

Obtained enable signal is further used as being the input for enabling circuit：CKV samples EN by trigger, obtains time window CKV rising edges in signal；Then, trigger is exported with CKV in itself mutually with finally giving and carrying CKV rising edges and cycle letter The CKV ' of breath, the input as time-to-digit converter measurement.