CN204906337U

CN204906337U - Device of adjustment clock duty cycle

Info

Publication number: CN204906337U
Application number: CN201520664030.2U
Authority: CN
Inventors: 廖浩勤; 严伟
Original assignee: Xi'an Qiwei Dieyi Semiconductor Technology Co Ltd
Current assignee: XI'AN AEROSEMI TECHNOLOGY Co.,Ltd.
Priority date: 2015-08-28
Filing date: 2015-08-28
Publication date: 2015-12-23
Anticipated expiration: 2025-08-28

Abstract

The utility model discloses a device of adjustment clock duty cycle, including the time delay chain circuit, time delay chain circuit transmission signal gives pulse generation ware a, and pulse generation ware an and pulse generation ware b transmission signal give the pulse combiner, and pulse combiner output signal gives the duty cycle detector, and the duty cycle signal is still received to the duty cycle detector, and duty cycle detector transmission signal gives the time delay chain circuit. Realized can be under the prerequisite that does not increase the clock signal noise to the clock signal duty cycle adjustment of input.

Description

A kind of device adjusting clock duty cycle

Technical field

The utility model belongs to semiconductor integrated circuit technical field, is specifically related to a kind of device adjusting clock duty cycle.

Background technology

In the past few decades, integrated circuit technique obtains swift and violent development.Electronic system particularly headed by communication, the direction towards two-forty, high-performance, high integration, low cost constantly advances.This just has higher requirement to the modules in system.As analog to digital converter, while system requirements improves the requirement such as sampling rate, quantified precision of analog to digital converter, also wish the conversion efficiency improving analog to digital converter, reduce its power consumption.

Along with the raising of sampling rate and frequency input signal, the quality requirement of analog to digital converter to clock signal is more and more higher.Such as in production line analog-digital converter, except requiring that clock circuit has except low-noise characteristic, also require that outside input clock undesirable for duty ratio is adjusted to the internal clocking of specifying duty ratio by it.The tradition duty ratio adjustment technology adjustment clock that utilizes adjusts duty ratio along the mode of slope more.But the adjusting range of the way of the tuned slope to duty ratio is limited, and a large amount of noises can be introduced.

Utility model content

The purpose of this utility model is to provide a kind of device adjusting clock duty cycle, achieves and can adjust the clock signal duty cycle of input under the prerequisite not increasing clock signal noise.

The technical scheme that the utility model adopts is, a kind of device adjusting clock duty cycle, comprise time delay chain circuit, time delay chain circuit transmissioning signal is to pulse generator a, pulse generator a and pulse generator b signal transmission are to pulse combiner, pulse combiner outputs signal to duty cycle detector, and duty cycle detector also receives duty cycle signals, and duty cycle detector signal transmission is to time delay chain circuit.

Feature of the present utility model is also,

Wherein time delay chain circuit comprises the controlled inverter of even number time delay.

Wherein pulse generator a and pulse generator b is and forms by Digital Logic gate circuit.

Wherein pulse combiner includes gate circuit and transistor.

Wherein duty cycle detector is a low-pass filter circuit.

The beneficial effects of the utility model are, a time delay chain circuit, two pulse generators, a pulse synthesizer and duty detection circuits.Input clock has two propagation paths: one, and successively through time delay chain circuit and pulse generator, this path produces the pulse signal that and input clock exist certain phase difference; Its two, be directly inputted to pulse generator, these two pulse signals have identical frequency, different phase places.Pulse combiner exports the clock signal that has particular duty cycle after these two pulses being merged.Duty detection circuit is for detecting the duty ratio of output clock.By arranging its parameter, the amount of delay of FEEDBACK CONTROL time delay chain, realizes the control of output clock duty ratio.Circuit of the present invention utilizes a hopping edge of clock signal, produces two hopping edges that new clock needs.So just expand the input duty cycle scope of circuit permission and controlled output duty cycle scope.And, in the process of adjustment duty ratio, reduce the noise introduced one of them hopping edge of clock signal as much as possible.This hopping edge can be used as the sampling edge of sample circuit.

Accompanying drawing explanation

Fig. 1 is a kind of structural representation adjusting the device of clock duty cycle of the utility model;

Fig. 2 is a kind of circuit connection diagram adjusting time delay chain circuit in the device of clock duty cycle of the utility model;

Fig. 3 is a kind of circuit connection diagram adjusting pulse generator in the device of clock duty cycle of the utility model;

Fig. 4 is a kind of circuit connection diagram adjusting pulse synthesizer in the device of clock duty cycle of the utility model;

Fig. 5 is a kind of circuit connection diagram adjusting duty cycle detector in the device of clock duty cycle of the utility model.

In figure, 1. time delay chain circuit, 2. pulse generator a, 3. pulse generator b, 4. pulse combiner, 5. duty cycle detector.

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in detail.

The utility model provides a kind of device adjusting clock duty cycle, as shown in Figure 1, comprise input clock signal CLKin and be connected to the input of time delay chain circuit 1 and the input of pulse generator b3, the output signal of time delay chain circuit 1 is CLKd, CLKd becomes narrow pulse signal PULSEd after pulse generator a2, and the output signal of pulse generator 2 is narrow pulse signal PULSEd0; The output signal of pulse generator a2 and pulse generator b3 passes to pulse combiner 4, and the output signal of pulse combiner 4 is CLKout; The output of pulse combiner 4 is connected to the input of duty cycle detector 5, and output signal DCC is fed back to time delay chain circuit by duty cycle detector 5, as the control signal controlling amount of delay;

Wherein the circuit connecting relation of time delay chain circuit 1 as shown in Figure 2, comprises even number of inverters, and the charging current of each inverter is controlled; The same-phase clock that clock signal clk in is delayed after even number of inverters, by regulating the charging ability of inverter, namely can adjust the amount of delay of time delay chain output clock.

Wherein the circuit connecting relation of pulse generator a2 and pulse generator b3 as shown in Figure 3, comprises one and form with door and odd number inverter; The rising edge of input clock signal Ci through with behind the door, become the rising edge of output clock P0; The rising edge of clock Ci after the time delay of odd number inverter, then is input to and door, becomes the trailing edge of clock P0; In the utility model, input clock CLKin and time delay chain output clock CLKd is the input of pulse generator.The rising edge of pulse generator 1, pulse generator 2 output clock PULSE0, PULSEd and trailing edge are all produced by the rising edge of input clock CLKin; And the gate circuit of the rising edge process of PULSE0 is minimum, amount of delay is minimum, and the noise of introducing is minimum;

Wherein the circuit connecting relation of pulse synthesizer 4 as shown in Figure 4, comprises transistor NM2, and transistor NM2 is responsible for the rising edge rising edge of pulse signal PULSE0 being converted into output clock CLKout; Transistor PM3 is responsible for the trailing edge rising edge of pulse signal PULSEd being converted into output clock CLKout, and inverter INV3, INV4 constitute a latch, when clock PULSE0, PULSEd are low level, this latch can the drain terminal voltage of stable transistor MP3, NM2;

Wherein the circuit connecting relation of duty cycle detector 5 as shown in Figure 5, comprises resistor voltage divider circuit, duty cycle detector be input as CLKout and Duty, export as duty cycle control signal DCC; Signal CLKout is the output clock of the utility model circuit; Signal Duty is duty cycle control signal; Signal DCC is for controlling the amount of delay of time delay chain circuit.

In the utility model, input clock signal CLKin have passed through two signal paths becomes output clock CLKout.Wherein one is be directly inputted to pulse generator 2, creates pulse signal PULSE0.After signal PULSE0 is input to driving pulse combiner, the rising edge of pulse combiner output clock CLKout.Gate circuit on this path is minimum, and the noise that circuit is introduced is minimum, can ensure the noise characteristic on clock edge.And on another path, clock CLKin have passed through time delay chain and is just input to pulse generator 1, then arrive pulse synthesizer.This path is mainly in order to realize the adjustment of duty ratio.The ratio rising edge of the trailing edge of the output signal CLKout that this signal path produces is large, does not advise that the sampling edge as sample circuit uses.

Claims

1. one kind adjusts the device of clock duty cycle, it is characterized in that, comprise time delay chain circuit (1), time delay chain circuit (1) signal transmission is to pulse generator a (2), pulse generator a (2) and pulse generator b (3) signal transmission are to pulse combiner (4), pulse combiner (4) outputs signal to duty cycle detector (5), duty cycle detector (5) also receives duty cycle signals, and duty cycle detector (5) signal transmission is to time delay chain circuit (1).

2. a kind of device adjusting clock duty cycle according to claim 1, is characterized in that, described time delay chain circuit (1) comprises the controlled inverter of even number time delay.

3. a kind of device adjusting clock duty cycle according to claim 1, is characterized in that, described pulse generator a (2) and pulse generator b (3) are and form by Digital Logic gate circuit.

4. a kind of device adjusting clock duty cycle according to claim 1, is characterized in that, described pulse combiner (4) includes gate circuit and transistor.

5. a kind of device adjusting clock duty cycle according to claim 1, is characterized in that, described duty cycle detector (5) is a low-pass filter circuit.