CN110545090B - Duty cycle adjusting circuit and noise immunity method thereof - Google Patents
Duty cycle adjusting circuit and noise immunity method thereof Download PDFInfo
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- CN110545090B CN110545090B CN201810530936.3A CN201810530936A CN110545090B CN 110545090 B CN110545090 B CN 110545090B CN 201810530936 A CN201810530936 A CN 201810530936A CN 110545090 B CN110545090 B CN 110545090B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/013—Modifications of generator to prevent operation by noise or interference
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
Abstract
The embodiment of the invention provides a duty ratio adjusting circuit and an anti-noise method thereof, and relates to the technical field of electronics. The duty cycle adjustment circuit includes: the noise introducing branch circuit is connected with the control branch circuit; the noise introducing branch circuit is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal with a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch circuit; and the control branch is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal. According to the embodiment of the invention, the noise of the power supply signal and the ground signal is counteracted by introducing the noise in the voltage signal, so that the influence of the noise is reduced.
Description
Technical Field
The present invention relates to the field of electronic technology, and in particular, to a duty cycle adjusting circuit and an anti-noise method for the duty cycle adjusting circuit.
Background
With the rapid development of computer technology, duty cycle adjustment circuits (Duty Cycle Corrector, DCC) are increasingly being used.
For example, in the case of high-speed systems employing Double Data Rate (DDR) techniques, these systems require the duty cycle of the clock signal to be accurately maintained at 50% so that the rising and falling edges have equally symmetric phase margins for sampling the Data. However, due to process, voltage and temperature (Process Voltage Temperature, PVT) effects, the input clock signal is distorted after transmission, which can deviate significantly from the 50% duty cycle value. Therefore, these systems require dedicated duty cycle adjustment circuits to correct the duty cycle of the clock signal, ensuring a 50% duty cycle.
Currently, the duty cycle adjustment circuit may implement the duty cycle adjustment by summing in an all-digital manner. Specifically, the duty Cycle adjusting circuit of the all-digital mode generally adopts waveform generation (PG), half-Cycle Delay Line (HCDL), and phase frequency detector (Phase Frequency Detect, PFD) to realize the function of adjusting the duty Cycle, so as to effectively resist the influence of noise fluctuation on the circuit. However, such duty cycle adjustment circuits require the use of HCDL to reconstruct waveforms, resulting in relatively large circuit areas, which are difficult to integrate in systems with stringent area requirements, such as Systems On Chip (SOC) systems with tight area requirements.
Disclosure of Invention
In view of the above, embodiments of the present invention are presented to provide a duty cycle adjustment circuit and an anti-noise method of a corresponding duty cycle adjustment circuit that overcomes or at least partially solves the above-described problems.
In order to solve the above problems, an embodiment of the present invention discloses a duty cycle adjustment circuit, including: the noise introducing branch circuit is connected with the control branch circuit; the noise introducing branch circuit is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal with a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch circuit; and the control branch is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal.
Optionally, the noise introducing branch comprises at least one noise introducing sub-branch, the noise introducing sub-branch comprising a first transistor and a second transistor; the first end of the second transistor is connected with the control branch circuit; the first transistor is used for introducing the voltage noise signal of the duty ratio adjusting circuit to the second transistor through the first end of the second transistor; the second transistor is configured to receive a control signal of the duty cycle adjustment circuit, synthesize the control signal with the voltage noise signal to form a new control signal, and provide the new control signal to the control branch.
Optionally, the control branch includes a third transistor, and the third transistor is used for connecting a ground signal of the duty ratio adjustment circuit; the noise introducing sub-branch comprises a ground noise introducing sub-branch, and the ground noise introducing sub-branch comprises a first transistor and a second transistor; a first transistor in the ground noise introducing sub-branch for connecting the ground signal and introducing a ground noise signal in the ground signal to a first terminal of a second transistor in the ground noise introducing sub-branch; the first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that a ground noise signal carried in the new control signal and a ground noise signal in the ground signal cancel each other to stabilize the working state of the third transistor.
Optionally, the control branch comprises a fourth transistor for connecting a power supply signal of the duty cycle adjustment circuit; the noise introducing sub-branch further comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor; a first transistor in the power supply noise introducing sub-branch for connecting the power supply signal and introducing a source noise signal in the power supply signal to a first end of a second transistor in the power supply noise introducing sub-branch; the first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that the source noise signal carried in the new control signal and the source noise signal in the power supply signal cancel each other to stabilize the working state of the fourth transistor.
Optionally, the first transistor is a field effect transistor or a triode, and the second transistor is a field effect transistor or a triode.
Optionally, the duty cycle adjustment circuit further includes: a buffer module and a detection module; one end of the buffer module is connected with the control branch, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch.
The embodiment of the invention also discloses an anti-noise method of the duty ratio adjusting circuit, which comprises the following steps:
introducing a voltage noise signal of the duty cycle adjusting circuit through a noise introducing branch of the duty cycle adjusting circuit;
synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit;
and providing the new control signal to a control branch of the duty cycle adjustment circuit, wherein the control branch is used for adjusting the duty cycle of the output clock signal of the duty cycle adjustment circuit according to the new control signal.
Optionally, the noise introducing branch of the duty cycle adjusting circuit introduces a voltage noise signal of the duty cycle adjusting circuit, including: introducing a ground noise signal in the ground signal of the duty cycle adjustment circuit through a ground noise introducing sub-branch;
The synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit comprises the following steps: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and a control signal of the duty ratio adjusting circuit.
Optionally, the noise introducing branch of the duty cycle adjusting circuit introduces a voltage noise signal of the duty cycle adjusting circuit, including: introducing a source noise signal in a power signal of the duty ratio adjusting circuit through a power noise introducing sub-branch;
the synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit comprises the following steps: and synthesizing a new control source signal by adopting a source noise signal in the power source signal and a control signal of the duty ratio adjusting circuit.
Optionally, the method further comprises: and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal.
The embodiment of the invention has the following advantages:
the duty ratio adjusting circuit in the embodiment of the invention has the advantages of small area, low power consumption, high noise immunity and the like, namely, the performance indexes of high performance, low area, low power consumption and high noise immunity can be considered, and the defect that the conventional analog DCC and digital DCC cannot be considered in terms of area and noise immunity is overcome.
Drawings
FIG. 1 is a schematic diagram of a duty cycle adjustment circuit according to the present invention;
FIG. 2 is a schematic diagram of the connection of a noise introducing sub-branch to a control branch in accordance with an alternative embodiment of the present invention;
FIG. 3 is a flow chart of steps of an anti-noise method embodiment of a duty cycle adjustment circuit of the present invention;
FIG. 4 is a schematic diagram of the connection of a ground noise inducing sub-branch to a control branch in one example of the invention;
FIG. 5 is a schematic diagram of the connection of a power supply noise introducing sub-branch to a control branch in one example of the invention;
fig. 6 is a schematic diagram of a duty cycle adjustment circuit in one example of the invention.
Detailed Description
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Along with the continuous enhancement of the data processing capability of an electronic system, for efficient data transmission, the duty ratio of a clock signal needs to be strictly controlled to be about 50%, so that the rising edge and the falling edge have equal and symmetrical phase margins to sample the data, thereby ensuring the accuracy of the data. However, even if the clock signal is guaranteed to be input to the electronic system in a 50% duty cycle state, factors such as mismatch, signal coupling, and process drift may distort the transmitted clock signal, which is severely deviated from the 50% duty cycle state. Therefore, the electronic system needs a special circuit, namely a duty cycle adjusting circuit, to adjust the duty cycle of the clock signal, so that the clock signal is ensured to be in a 50% duty cycle state. In addition, as the area of electronic systems continues to decrease, stringent requirements are placed on the area of the duty cycle adjustment circuit.
At present, a digital duty ratio adjusting circuit realized by adopting a digital method can keep performance and simultaneously has the functions of resisting power supply and ground noise, but occupies a large area, and is difficult to integrate in a system with strict area requirements. The existing analog duty cycle adjusting circuit realized by adopting an analog method can keep the performance and can also have smaller area, but the application of the analog duty cycle adjusting circuit is severely limited by the high sensitivity of the analog duty cycle adjusting circuit to the noise of the power signal and the ground signal. For example, in a system where the circuit environment is complex and a mixed signal exists, that is, in a case where the power signal and the ground signal cannot be guaranteed to be very clean, the existing analog duty ratio adjustment circuit cannot be applied. Therefore, how to overcome noise of power and ground signals in a system becomes a particularly critical problem under the condition of ensuring that DCC area is small.
One of the core ideas of the embodiments of the present invention is to provide a new duty cycle adjusting circuit, which can cancel noise of a power signal and a ground signal by introducing noise in a voltage signal, and mitigate the influence of the noise.
Referring to fig. 1, a schematic diagram of a duty cycle adjustment circuit of the present invention is shown.
In an embodiment of the present invention, the duty cycle adjustment circuit may include: a noise introducing branch 110 and a control branch 120, and the noise introducing branch 110 is connected to the control branch 120. The noise introducing branch 110 is configured to introduce a voltage noise signal of the duty cycle adjusting circuit, synthesize the voltage noise signal with a control signal Vctrl of the duty cycle adjusting circuit to form a new control signal, and transmit the new control signal to the control branch 120. The control branch 120 is configured to adjust the duty ratio of the output clock signal of the duty ratio adjustment circuit according to the new control signal.
The voltage noise signal may be used to characterize noise in the voltage signal of the duty cycle adjustment circuit, and may include a source noise signal in the power supply signal, a ground noise signal in the ground signal, and so on. Wherein the source noise signal may be used to characterize source noise in the power supply signal and the ground noise signal may be used to characterize ground noise in the ground signal. The control signal Vctrl of the duty cycle adjustment circuit may be used to control the duty cycle state of the clock signal, so as to ensure that the clock signal is in a preset duty cycle state.
In the embodiment of the present invention, the new control signal carries the voltage noise signal introduced through the noise introducing branch 110. In the process that the control branch 120 controls the input clock signal according to the new control signal, the voltage noise signal carried in the new control signal can be offset with the voltage noise signal in the voltage signal connected with the control branch 120, so as to achieve the purpose of noise offset, and the control branch is not affected by the voltage noise signal, so that the working state of the control stage is stabilized.
In an alternative embodiment of the present invention, the noise introducing branch 110 may include at least one noise introducing sub-branch, that is, may include one or more noise introducing sub-branches, and the number of noise introducing sub-branches is not specifically limited in the embodiment of the present invention.
Referring to fig. 2, a schematic diagram of the connection of a noise introducing sub-branch to a control branch is shown in an alternative embodiment of the invention.
In an embodiment of the present invention, the noise introducing sub-branch 210 may include a first transistor 211 and a second transistor 212. Wherein the first transistor 211 is connected to the first terminal of the second transistor 212, and the first terminal of the second transistor 212 may be connected to the control branch 220. The first transistor 211 may be configured to introduce a voltage noise signal of the duty cycle adjustment circuit to the second transistor 212 through a first terminal of the second transistor 212; the second transistor 212 may be configured to receive the control signal Vctrl of the duty cycle adjustment circuit, synthesize the control signal with the voltage noise signal to form a new control signal, and provide the new control signal to the control branch 220, so that the control branch 220 may control the input clock signal of the duty cycle adjustment circuit according to the new control signal, so as to ensure that the clock signal is in a preset duty cycle state, for example, ensure that the clock signal is in a 50% duty cycle state.
In a specific implementation, the first transistor may be a field effect transistor or a triode; the second transistor may also be a field effect transistor or a triode, which is not particularly limited in the embodiment of the present invention. For example, when the second transistor is a field effect transistor, the first terminal of the second transistor may be a source terminal of the field effect transistor. For another example, where the second transistor is a triode, the first terminal of the second transistor may be the emitter of the triode, and so on.
As an example of the present invention, when the first transistor and the second transistor employ field effect transistors, a source terminal of the first transistor may be connected to a source terminal of the second transistor, and the second transistor may be connected to a control branch of the duty ratio adjustment circuit. The first transistor may be used to introduce the voltage noise signal of the duty cycle adjustment circuit to the source terminal of the second transistor, i.e. the first transistor may be connected to the voltage signal of the duty cycle adjustment circuit to introduce the voltage noise signal of the voltage signal to the source terminal of the second transistor. The second transistor may be configured to transmit the control signal Vctrl of the duty cycle adjustment circuit to a source terminal of the second transistor, so that the control signal and the voltage noise signal synthesize a new control signal, and the new control signal may be provided to the control branch. Specifically, the gate end of the second transistor may be connected to the control signal of the duty cycle adjusting circuit, so that the control signal may be introduced to the source end of the second transistor, so that the control signal may be overlapped with the voltage noise signal to synthesize a new control signal, and then the new control signal may be provided to the control branch for use, so that the control branch may control the input clock signal of the duty cycle adjusting circuit according to the new control signal, and the duty cycle of the clock signal is ensured to be 50%.
Referring to fig. 3, a flowchart illustrating steps of an anti-noise method embodiment of a duty cycle adjustment circuit of the present invention may specifically include the following steps:
step 301, introducing a voltage noise signal of a duty cycle adjustment circuit through a noise introducing branch of the duty cycle adjustment circuit.
And step 302, synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit.
Step 303 provides the new control signal to the control branch of the duty cycle adjustment circuit.
The control branch is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal.
In summary, the duty cycle adjusting circuit in the embodiment of the invention can introduce voltage signal noise through the noise introducing branch, so that the introduced voltage signal noise and the control signal of the duty cycle adjusting circuit can be adopted to synthesize to obtain a new control signal, then the new control signal can be improved and supplied to the control branch, and the new control signal carries the introduced voltage noise signal, and further, the voltage noise signal carried in the new control signal and the noise signal in the voltage signal connected with the control branch can be adopted to cancel, thereby achieving the purpose of noise cancellation, enabling the control branch not to be influenced by the noise in the connected voltage signal, and solving the problem of noise rejection of the duty cycle adjusting circuit in the prior art.
In a specific implementation, the duty cycle adjusting circuit provided by the embodiment of the invention can be implemented by adopting an analog method to reduce the area of the duty cycle adjusting circuit, so that the duty cycle adjusting circuit can be integrated in a system with strict area requirements, such as an SOC system. Optionally, the noise introducing branch of the duty cycle adjustment circuit may comprise one or more noise introducing sub-branches. The noise introducing sub-branch may be divided into a ground noise introducing sub-branch and a power supply noise introducing sub-branch. The ground noise introducing sub-branch can be used for introducing ground noise in the ground signal, so that the control branch can adopt the introduced ground noise to counteract noise in the ground signal connected with the control branch, and the purpose of counteracting the ground noise is achieved. The power supply noise introducing sub-branch can be used for introducing source noise in a power supply signal, so that the control branch can adopt the introduced source noise to counteract the source noise in the power supply signal connected with the control branch, and the purpose of counteracting the source noise is achieved.
In an optional embodiment of the invention, the introducing the voltage noise signal of the duty cycle adjusting circuit through the noise introducing branch of the duty cycle adjusting circuit may include: and introducing a ground noise signal in the ground signal of the duty ratio adjustment circuit through a ground noise introducing sub-branch. The synthesizing a new control signal using the voltage noise signal and the control signal of the duty cycle adjustment circuit may include: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and a control signal of the duty ratio adjusting circuit. Therefore, the control branch circuit can offset the ground noise signal carried in the new control ground signal from the ground noise signal in the ground signal, so that the ground noise is offset. In the embodiment of the invention, the new control signal is the new control ground signal.
In a specific implementation, the control branch may include a third transistor, where the third transistor is configured to be connected to a ground signal of the duty cycle adjustment circuit, so that the duty cycle adjustment circuit may be connected to the ground signal through the third transistor of the control branch, so as to control the input clock signal according to a control voltage generated by the connected ground signal, and implement adjustment of the duty cycle of the clock signal.
In the embodiment of the invention, the noise introducing sub-branch may include a ground noise introducing sub-branch, where the ground noise introducing sub-branch includes a first transistor and a second transistor. The first transistor in the ground noise introduction sub-branch is used for connecting the ground signal and introducing the ground noise signal in the ground signal to the first end of the second transistor in the ground noise introduction sub-branch; the first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that a ground noise signal carried in the new control signal and a ground noise signal in the ground signal voltage cancel each other to stabilize the working state of the third transistor.
For example, when the first transistor, the second transistor, and the third transistor in the control branch are all field effect transistors, the first transistor and the second transistor in the ground noise introducing sub-branch may be connected in a manner as shown in fig. 4, the drain terminal of the first transistor 411 of the ground noise introducing sub-branch 410 may be directly connected to the ground signal Vss of the duty ratio adjusting circuit, and the gate terminal of the first transistor 411 may be connected to the ground signal Vss through a resistor R, so that the ground noise signal in the ground signal Vss may be introduced to the source terminal of the second transistor 412 of the ground noise introducing sub-branch 410. The gate terminal of the second transistor 412 of the ground noise introducing sub-branch 410 may be connected to the control signal Vctrl of the duty cycle adjusting circuit, so that the control signal Vctrl may be introduced to the source terminal of the second transistor 412 of the ground noise introducing sub-branch 410, so that the control signal Vctrl may be synthesized with the ground noise signal introduced by the first transistor 411 to obtain a new control ground signal, and then transmitted to the gate terminal of the third transistor 421 of the control branch 420, so as to implement noise cancellation on the third transistor 421 and the gate source voltage, that is, implement cancellation of the ground noise, so that the gate source voltage Vgs of the third transistor 421 is not affected by the ground noise, and achieve the purpose of stabilizing the control stage working state of the control branch 420. It should be noted that the control branch 420 may control the input clock signal Ckin according to the new control ground signal. The drain terminal of the second transistor 412 may be connected to a high level signal, such as a high level signal of a dc current, or may be connected to a power signal of a duty ratio adjusting circuit, so that the second transistor 412 may be turned on when the control signal Vctrl is a low level signal, and further the control signal Vctrl may be transmitted to the source terminal of the second transistor 412 to be synthesized with a ground noise signal introduced by the first transistor 411.
The ground noise introducing sub-branch 410 may or may not have a resistor R, and whether the resistor R is specifically set may be determined by the characteristics of the first transistor 411; that is, when the first transistor 411 is a transistor capable of directly connecting a ground signal, the ground signal may be directly connected to the gate terminal of the first transistor 411, and when the first transistor 411 is a transistor incapable of directly connecting a power supply signal, a resistor R needs to be provided between the ground signal and the gate terminal of the first transistor 411.
In an alternative embodiment, the first transistor in the ground noise introducing sub-branch may be a P-channel Metal Oxide Semiconductor (Positive Channel Metal Oxide Semiconductor, PMOS) transistor, and the third transistor and the second transistor in the ground noise introducing sub-branch may each be an N-Metal-Oxide-Semiconductor (NMOS) transistor. Of course, the first transistor, the second transistor in the ground noise introducing sub-branch or the third transistor in the control branch may also be a transistor; in addition, the first transistor, the second transistor or the third transistor in the control branch may be junction field effect transistors, which are not particularly limited in the embodiment of the present invention.
In an embodiment of the present invention, optionally, the introducing, by the noise introducing branch of the duty cycle adjusting circuit, the voltage noise signal of the duty cycle adjusting circuit may include: and introducing source noise signals in the power supply signals of the duty ratio adjusting circuit through a power supply noise introducing sub-branch. The synthesizing a new control signal using the voltage noise signal and the control signal of the duty cycle adjustment circuit may include: and synthesizing a new control source signal by adopting a source noise signal in the power source signal and a control signal of the duty ratio adjusting circuit. Therefore, the control instruction can offset the source noise signal carried in the new control source signal and the source noise signal in the power supply signal, so that the offset of the source noise is realized. In the embodiment of the invention, the new control signal is the new control source signal.
In a specific implementation, the control branch may include a fourth transistor, where the fourth transistor is configured to be connected to a power signal of the duty cycle adjustment circuit, so that the duty cycle adjustment circuit may be connected to the power signal through the fourth transistor of the control branch, so as to control an input clock signal according to a control voltage generated by the connected power signal, and implement adjustment of a duty cycle of the clock signal.
The noise introducing branch comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor; the first transistor in the power supply noise introducing sub-branch is used for connecting the power supply signal and introducing the source noise signal in the power supply signal to the first end of the second transistor in the power supply noise introducing sub-branch. The first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that a source noise signal carried in a new control source signal and a source noise signal in the power supply signal cancel each other to stabilize the working state of the fourth transistor.
For example, when the fourth transistor and the first transistor and the second transistor of the power noise introducing sub-branch are all transistors, the first transistor and the second transistor of the power noise introducing sub-branch may be connected as shown in fig. 5, the collector of the first transistor 511 of the power noise introducing sub-branch 510 may be directly connected to the power signal Vdd of the duty ratio adjusting circuit, and the base of the first transistor 511 may be connected to the power signal Vdd through a resistor R1, so that the source noise signal in the power signal Vdd may be introduced to the emitter of the second transistor 512 of the power noise introducing sub-branch 510. The base of the second transistor 512 of the power noise introducing sub-branch 510 may be connected to the control signal Vctrl of the duty cycle adjusting circuit, so that the control signal Vctrl may be introduced into the emitter of the second transistor 512 of the power noise introducing sub-branch 510, so that the control signal Vctrl may be synthesized with the source noise signal introduced by the first transistor 512 to obtain a new control source signal, and then transmitted to the base of the fourth transistor 521 of the control branch 520, so as to implement cancellation of the source noise on the fourth transistor 521, so that the fourth transistor 521 is not affected by the source noise, and achieve the purpose of stabilizing the control stage working state of the control branch 520. It should be noted that, the control branch 520 may control the input clock signal Ckin according to the new control source signal. The collector of the second transistor 512 may be connected to a low level signal, such as a low level signal of a dc current, or may be connected to a ground signal of the air ratio adjusting circuit, so that the second transistor 512 may be turned on when the control signal Vctrl is a high level signal, and further the control signal Vctrl may be transmitted to the emitter of the second transistor 512 to be synthesized with the source noise signal introduced by the first transistor 511.
The power noise introducing sub-branch 510 may be provided with a resistor R1, or may not be provided with the resistor R1, and whether the resistor R1 is provided is determined by the characteristics of the first transistor 511; that is, when the first transistor 511 is a transistor capable of being directly connected to a power supply signal, the power supply may be directly connected to the base of the first transistor 511, and when the first transistor 511 is a transistor incapable of being directly connected to a power supply signal, it is necessary to provide a resistor R1 between the power supply and the base of the first transistor 511.
In an alternative embodiment of the present invention, the fourth transistor, the first transistor in the power noise introducing sub-branch, and the second transistor may be field effect transistors, for example, the first transistor in the power noise introducing sub-branch may be NMOS transistors, and the third transistor and the second transistor in the ground noise introducing sub-branch may be PMOS transistors; in addition, the first transistor, the second transistor or the third transistor in the control branch may be junction field effect transistors, which are not particularly limited in the embodiment of the present invention.
In an embodiment of the present invention, optionally, the duty cycle adjustment circuit may further include: a buffer module and a detection module. One end of the buffer module is connected with the control branch, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch.
For a better understanding of embodiments of the present invention, those skilled in the art will now be described, by way of example, with reference to the following examples:
as an example of the present invention, the duty cycle adjustment circuit may include a power noise introducing sub-branch 610, a ground noise introducing sub-branch 620, a control branch 630, a buffer module 640, and a detection module 650, as shown in fig. 6. The Buffer module 640 may include one or more buffers, for example, a Buffer Chain (Buffer Chain) formed by sequentially connecting three buffers.
In this example, the noise of the power supply signal may be introduced by the first transistor M1 and the second transistor M2 of the power supply noise introduction sub-branch 610, while the noise of the ground signal may be introduced by the first transistor M7 and the second transistor M8 of the ground noise introduction sub-branch 620, for the purpose of canceling the noise.
Specifically, the drain terminal of the first transistor M1 in the power noise introducing sub-branch 610 may be connected to the power signal Vdd, and the gate terminal of the first transistor M1 may be connected to the power signal Vdd through the resistor R1, so that the first transistor M1 may introduce the source noise signal to the source terminal of the second transistor M2 in the power noise introducing sub-branch 610. The second transistor M2 may introduce the control signal Vctrl output by the detection module 650 to the source end of the second transistor M2, so that the control signal Vctrl and the introduced source noise signal may be synthesized into a new control source signal, and transmitted to the gate end of the fourth transistor M4 of the control branch 630, so as to implement cancellation of the source noise signal and noise on the gate source voltage on the fourth transistor M4, that is, cancel the source noise, so that the gate source voltage Vgs of the fourth transistor M4 is not affected by the power noise, and achieve the purpose of stable operating state.
Similarly, the drain terminal of the first transistor M7 in the ground noise introducing sub-branch 620 may be connected to the ground signal Vss, and the gate terminal of the first transistor M7 may be connected to the ground signal Vss through the resistor R2, so that the first transistor M7 may introduce the ground noise signal to the source terminal of the second transistor M8 in the ground noise introducing sub-branch 620. The second transistor M8 may introduce the control signal Vctrl output by the detection module 650 to the source terminal of the second transistor M8, so that the control signal Vctrl and the introduced ground noise signal are synthesized into a new control ground signal, and transmitted to the gate terminal of the third transistor M3 of the control branch 630, so as to implement cancellation of the ground noise signal and the noise on the gate source voltage on the third transistor M3, that is, cancel the ground noise, and make the gate source voltage Vgs of the third transistor M3 not affected by the ground noise, thereby achieving the purpose of stable operating state.
Therefore, the noise introducing branch composed of the field effect transistors can be added, the control voltage Vctrl is introduced, and the source noise and/or the ground noise are introduced at the same time, so that the purpose of counteracting the source noise and/or the ground noise is achieved, and the problems that the existing simulation DCC is small in area and poor in noise resistance are solved.
In a specific implementation, the duty cycle adjustment circuit may be used to process the interface clock signal such that the interface clock signal maintains a 50% duty cycle. Of course, the duty cycle adjustment circuit may also be used to generate an interface clock signal, etc., as embodiments of the invention are not limited in this respect.
For example, in the case where the duty cycle adjustment circuit is used to process the interface clock signal, the duty cycle adjustment circuit may control the input clock signal in accordance with the control voltage, that is, adjust the duty cycle of the output clock signal of the duty cycle adjustment circuit to correct the duty cycle of the output clock signal to be 50%.
In an alternative embodiment of the present invention, the anti-noise method of the duty cycle adjustment circuit may further include: and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal. For example, in connection with the above example, as shown in fig. 6, the control branch 630 may control the input clock signal Ckin according to a new control voltage to control the charge and discharge rates of the fifth transistor M5 and the sixth transistor M6, that is, adjust the duty cycle of the output clock signal according to the new control signal, so that the rising/falling time of the output waveform relative to the input waveform changes, so as to achieve the purpose of adjusting the duty cycle of the output clock signal. The output waveform may be a waveform of the output clock signal, and the input waveform may be a waveform of the input clock signal. Alternatively, the fifth transistor M5 may be a PMOS transistor, and the sixth transistor M6 may be an NMOS transistor.
In the embodiment of the present invention, the duty cycle adjustment circuit may be as follows: 1, introducing source noise and ground noise into the gate end of a device directly contacting the source noise and the ground noise, namely introducing a ground noise signal into the gate end of a third transistor under the condition of keeping the original value of the ground noise, and introducing a source noise signal into the gate end of a fourth transistor under the condition of keeping the original value of the source noise, so that cancellation noise at the gate source end of the device contacting the noise is realized, the gate source voltage Vgs of the device is not influenced by the noise, and the purpose of stabilizing the working state of the device is achieved. In addition, the duty ratio adjusting circuit can simultaneously complete the reasonable superposition of the source noise signal to be counteracted, the ground noise signal and the control signal, and generate a new control signal, so that the new control signal carries a noise control device to be counteracted, and meanwhile, the noise counteracting is completed on the device, thereby enabling the device to work in a stable working state, and simultaneously, the original control capability of the control signal can be maintained. Therefore, the embodiment of the invention solves the problem of sensitivity of power supply and ground noise in the existing high-performance simulation DCC, and achieves the purpose of inhibiting the influence of the power supply and ground noise on the duty ratio adjustment result.
In summary, the duty ratio adjusting circuit provided by the embodiment of the invention has the advantages of small area, low power consumption and high noise immunity, namely, the performance indexes of high performance, low area, low power consumption and high noise immunity can be considered, and the defect that the existing analog DCC and digital DCC cannot be considered in terms of area and noise immunity is overcome.
It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.
The duty cycle adjusting circuit and the anti-noise method of the duty cycle adjusting circuit provided by the invention are described in detail, and specific examples are applied to illustrate the principles and the implementation modes of the invention, and the description of the above examples is only used for helping to understand the method and the core idea of the invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Claims (9)
1. A duty cycle adjustment circuit, comprising: the noise introducing branch circuit is connected with the control branch circuit;
the noise introducing branch circuit is used for introducing a voltage noise signal of the duty ratio adjusting circuit, synthesizing the voltage noise signal with a control signal of the duty ratio adjusting circuit to form a new control signal, and transmitting the new control signal to the control branch circuit;
the control branch is used for adjusting the duty ratio of the output clock signal of the duty ratio adjusting circuit according to the new control signal;
The noise introducing branch comprises at least one noise introducing sub-branch, and the noise introducing sub-branch comprises a first transistor and a second transistor;
the first end of the second transistor is connected with the control branch circuit;
the first transistor is used for introducing the voltage noise signal of the duty ratio adjusting circuit to the second transistor through the first end of the second transistor;
the second transistor is configured to receive a control signal of the duty cycle adjustment circuit, synthesize the control signal with the voltage noise signal to form a new control signal, and provide the new control signal to the control branch.
2. The circuit of claim 1, wherein the control branch comprises a third transistor for coupling to a ground signal of the duty cycle adjustment circuit;
the noise introducing sub-branch comprises a ground noise introducing sub-branch, and the ground noise introducing sub-branch comprises a first transistor and a second transistor;
a first transistor in the ground noise introducing sub-branch for connecting the ground signal and introducing a ground noise signal in the ground signal to a first terminal of a second transistor in the ground noise introducing sub-branch;
The first end of the second transistor in the ground noise introducing sub-branch is connected with the third transistor, so that a ground noise signal carried in the new control signal and a ground noise signal in the ground signal cancel each other to stabilize the working state of the third transistor.
3. A circuit according to claim 1 or 2, wherein the control branch comprises a fourth transistor for connecting a power supply signal of the duty cycle adjustment circuit;
the noise introducing sub-branch further comprises a power supply noise introducing sub-branch, and the power supply noise introducing sub-branch comprises a first transistor and a second transistor;
a first transistor in the power supply noise introducing sub-branch for connecting the power supply signal and introducing a source noise signal in the power supply signal to a first end of a second transistor in the power supply noise introducing sub-branch;
the first end of the second transistor in the power supply noise introducing sub-branch is connected with the fourth transistor, so that the source noise signal carried in the new control signal and the source noise signal in the power supply signal cancel each other to stabilize the working state of the fourth transistor.
4. The circuit of claim 1, wherein the first transistor is a field effect transistor or a triode and the second transistor is a field effect transistor or a triode.
5. The circuit of claim 1, further comprising: a buffer module and a detection module;
one end of the buffer module is connected with the control branch, and the other end of the buffer module is connected with the detection module, so that the detection module generates a control signal of the duty ratio adjusting circuit according to an output clock signal of the control branch.
6. An anti-noise method of a duty cycle adjustment circuit, comprising:
introducing a voltage noise signal of the duty cycle adjusting circuit through a noise introducing branch of the duty cycle adjusting circuit;
synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit;
providing the new control signal to a control branch of the duty cycle adjustment circuit, wherein the control branch is used for adjusting the duty cycle of an output clock signal of the duty cycle adjustment circuit according to the new control signal;
the noise introducing branch comprises at least one noise introducing sub-branch, and the noise introducing sub-branch comprises a first transistor and a second transistor;
The first end of the second transistor is connected with the control branch circuit;
the first transistor is used for introducing the voltage noise signal of the duty ratio adjusting circuit to the second transistor through the first end of the second transistor;
the second transistor is configured to receive a control signal of the duty cycle adjustment circuit, synthesize the control signal with the voltage noise signal to form a new control signal, and provide the new control signal to the control branch.
7. The method of claim 6, wherein the step of providing the first layer comprises,
the noise introducing branch circuit for introducing the voltage noise signal of the duty ratio adjusting circuit comprises: introducing a ground noise signal in the ground signal of the duty cycle adjustment circuit through a ground noise introducing sub-branch;
the synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit comprises the following steps: and synthesizing a new control ground signal by adopting a ground noise signal in the ground signal and a control signal of the duty ratio adjusting circuit.
8. The method of claim 6, wherein the step of providing the first layer comprises,
the noise introducing branch circuit for introducing the voltage noise signal of the duty ratio adjusting circuit comprises: introducing a source noise signal in a power signal of the duty ratio adjusting circuit through a power noise introducing sub-branch;
the synthesizing a new control signal by adopting the voltage noise signal and the control signal of the duty ratio adjusting circuit comprises the following steps: and synthesizing a new control source signal by adopting a source noise signal in the power source signal and a control signal of the duty ratio adjusting circuit.
9. The method according to any one of claims 6 to 8, further comprising:
and adjusting the duty ratio of the output clock signal according to the new control signal through the control branch circuit to obtain an adjusted output clock signal.
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