CN106026982A - Monostable trigger - Google Patents

Monostable trigger Download PDF

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Publication number
CN106026982A
CN106026982A CN201610540981.8A CN201610540981A CN106026982A CN 106026982 A CN106026982 A CN 106026982A CN 201610540981 A CN201610540981 A CN 201610540981A CN 106026982 A CN106026982 A CN 106026982A
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monostable
time
trigger
signal
delay
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CN106026982B (en
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万美琳
顾豪爽
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Hubei University
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Hubei University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023—Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0232—Monostable circuits

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  • Pulse Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention discloses a monostable trigger. The monostable trigger is a monostable trigger circuit based on inverter delay chains; the monostable trigger comprises a basic monostable triggering module and a delay reset module; the basic monostable triggering module is the monostable trigger circuit having adjustable pulse width current; the basic monostable triggering module is combined with the delay reset module; therefore, the monostable trigger circuit having adjustable pulse width current and capable of being triggered repetitively is formed; the basic monostable triggering module comprises a trigger DFF1, a delay chain 1, a delay chain 2, a NAND gate and an inverter; the delay reset module comprises a trigger DFF2, a delay chain 3 and a digital logic gate; and all the triggers are D triggers having a reset function. The circuit disclosed by the invention is only composed of the delay chains composed of the inverter, the triggers and the digital logic gate, and does not have a resistor, a capacitor, an amplifier and a comparator; furthermore, a standard digital process and a design process are compatible; controllable and repetitive triggering of monostable pulse width current are easily realized; and thus, compared with the existing monostable trigger, the monostable trigger disclosed by the invention has the advantages of being low cost and power consumption, high in compatibility and universality and the like.

Description

A kind of monostable flipflop
Technical field
The present invention relates to a kind of monostable flipflop, be specifically related to a kind of adjustable pulse width based on time delay chain and repeatable The monostable flipflop circuit triggered, can be widely applied in shaping pulse, time delay and timing circuit, belongs to IC design skill Art field.
Background technology
Monostable flipflop or triggering intervalometer are for providing pulse letter that triggered, that pulsewidth is fixing by input clock Number, it is mainly used in the fields such as shaping pulse, time delay and timing, in communication system, digital display circuit and signal processing system Extensive application, is that modern integrated circuits designs indispensable circuit module.
Traditional monostable flipflop is based on electric capacity, resistance timing circuit, when applying input and triggering signal, uses by fixed Time resistance determine charging current timing capacitor is charged, when the voltage at timing capacitor two ends reaches threshold value, comparator Output change, and then trigger digital trigger or switch and make its state change, export positive or negative arteries and veins Rush signal.Tradition monostable flipflop includes the devices such as passive resistance, electric capacity, active comparator, the arteries and veins of its output single steady signal Rush width directly to be determined by the RC time constant of timing resistor, electric capacity.
Accompanying drawing 1 show traditional based on resistance, the monostable flipflop schematic diagram of electric capacity timing, in Fig. 1, when input is touched SignalCLK_INWhen triggering pulse without input, circuit is in the lock state,AFor logic high,BFor logic low,MFor logic low,N For logic high, export single steady signalCLK_OUTRemain low.Work as input signalCLK_INAfter uprising namely occurring triggering pulse, ComparatorComp 2OutputBBecome logic low,MPoint becomes logic high, so thatNBecome logic low,CLK_OUTStrain mutually High；Meanwhile, due toNFor logic low, switchS 1Will be switched off, power vd D passes through timing resistorRTo timing capacitorCFill Electricity, works as electric capacityCBoth end voltageKIt is more thanV REF1Time, comparatorComp 1OutputAStep-down, if nowCLK_INReturn to logic low, thenB Also it is logic high, thusMPoint step-down,NPoint uprises, outputCLK_OUTLogic low is returned to from newly,NAfter point uprises, switchS 1Lead It is logical,KPoint is pulled to logic low, so thatABecome logic high, so,AWithBBeing all logic high, latch is in latch shape State, outputCLK_OUTRemain low.It can be seen that tradition based onRCThe monostable flipflop output pulse width of intervalometer is:
From above formula: after choosing bigger resistance R and electric capacity C, tradition monostable flipflop can provide monostable pulsewidth relatively Wide output pulse, on the contrary then output pulse width narrows.But the main table of weak point that this kind of traditional monostable flipflop exists It is present: the passive resistance 1. used and capacitor element area are relatively big, and need to use active comparator or operational amplifier, And reference voltageV REF1Needing to be provided by single voltage generating module, circuit is complicated, and power consumption is higher；2. due to monostable pulsewidth by RC determines, but in circuit, R, C value cannot be by regulation current adjustment effect, and the most traditional monostable flipflop cannot realize list The function of steady pulsewidth current adjustment；3. need to use device or the modules such as comparator, resistance, electric capacity, it is impossible to real by digital circuit Existing, therefore can not the digital design flow of completely compatible chip.
In sum, a kind of avoid using resistance and the bigger passive device of electric capacity homalographic, and comparator or put The active circuit module that the power consumptions such as big device are higher, realizes exporting the current adjustment of monostable pulsewidth and repeatable triggering simultaneously, and holds concurrently The monostable flipflop holding Design of Digital Circuit flow process becomes required.
Summary of the invention
The present invention is directed to background technology and propose problem, a kind of monostable flipflop of design, based on phase inverter time delay chain Monostable flipflop circuit, it only includes time delay chain, trigger and the corresponding digital logic gate being made up of phase inverter, it is not necessary to Resistance, electric capacity, amplifier and comparator, and compatibility standard digital technology and design cycle, easily realize monostable pulsewidth controlled current flow With repeatable triggering, compare existing monostable flipflop, there is the advantages such as low cost, low-power consumption, compatible strong and highly versatile.
In order to achieve the above object, the present invention uses below scheme:
A kind of monostable flipflop, it is characterised in that: including: the most monostable trigger module, time-delay reset module；
The most monostable described trigger module is pulsewidth current adjustment monostable trigger circuit based on time delay chain；Described the most monostable Trigger module and time-delay reset block combiner, constitute the monostable triggering of pulsewidth current adjustment based on time delay chain and repeatable triggering Device circuit；
The most monostable described trigger module includes: trigger DFF1, time delay chain 1 and time delay chain 2, NAND gate, phase inverter；
Described time-delay reset module includes: trigger DFF2, time delay chain 3 and digital logic gate；Described trigger DFF1 and triggering Device DFF2 is the d type flip flop of band reset function；
In the most monostable described trigger module, the time delay chain 1 output letter to being triggered the trigger DFF1 that signal TR triggers by input Number Q carries out td1Time delay, obtains time delayed signal Qd1；Described time delay chain 2 is to Qd1Carry out td2Time delay, obtains time delayed signal Qd2；When by Input triggers signal TR and causes the change of Q to be transferred to Qd1Time, trigger DFF1 is resetted, before making Q be reset to trigger State, further, when the change being triggered the Q that signal TR causes by input is transferred to Qd2Time, discharge reset signal, thus obtain Monostable pulsewidth is td1, triggering recovery time be td2Output single steady signal；Described reset signal is by Qd2Inversion signal and Qd1Enter Row NAND operation obtains；
In described time-delay reset module, input triggers signal TR and is connected to the triggering clock end of trigger DFF2, trigger DFF2 Output signal QRSObtaining exporting reset signal RST after anti-phase, described reset signal RST is after the time delay of time delay chain 3 Obtaining total delay time is td3Time delayed signal；Described time delayed signal carries out "AND" with described trigger DFF1 output signal Q again Computing, as the low effective reset signal RS_RT of trigger DFF2.
A kind of monostable flipflop, it is characterised in that: described time delay chain 1 or time delay chain 2 include at least two Concatenation delay unit, single delay unit includes the two-stage phase inverter of cascade；By changing total number or single of delay unit The delay value of delay unit, obtains the total delay time of different time delay chains, and then obtains different monostable pulsewidths and trigger recovery Time.
A kind of monostable flipflop, it is characterised in that: by the biasing of phase inverter in described delay unit Electric currentI CTRL It is adjusted, it is achieved the current adjustment of phase inverter time delay, and then realizes the current adjustment of output single steady signal pulsewidth.
A kind of monostable flipflop, it is characterised in that: within the current monostable cycle, input triggers signal TR again When secondary generation triggers, by obtaining Qd1Time delay chain 1 in all delay unit input signals reset, it is achieved monostable The repeatable triggering of trigger；
The described reset signal for resetting delay unit input signals all in time delay chain 1 produces process: will be multiple The original input signal of each delay unit in position signal RST and time delay chain 1 carries out AND operation, then will obtain after computing Signal is connected to each delay unit input in time delay chain 1.
The invention has the beneficial effects as follows:
The monostable flipflop circuit based on time delay chain that the present invention proposes only includes the time delay chain being made up of phase inverter with corresponding Digital logic gate, it is not necessary to resistance, electric capacity, amplifier and comparator, compatibility standard digital technology and design cycle.Easily realize Monostable pulsewidth current adjustment and repeatable triggering, only need to be adjusted just can realizing to the bias current of time delay chain monostable pulsewidth Current adjustment, only need to carrying out the input signal of each delay unit resets just can realize repeatable triggering.Compared to existing Method there is the advantages such as low cost, low-power consumption, compatible strong, pulsewidth current adjustment and repeatable triggering.
Accompanying drawing explanation
Fig. 1 is tradition monostable flipflop schematic diagram based on RC timing circuit；
Fig. 2 is present invention pulsewidth based on time delay chain current adjustment monostable flipflop circuit theory diagrams；
Fig. 3 is one monostable flipflop oscillogram of the present invention；
Fig. 4 is basic phase inverter schematic diagram；
Fig. 5 is current-steering phase inverter schematic diagram；
Fig. 6 is present invention pulsewidth based on time delay chain current adjustment and repeatable triggering monostable flipflop circuit theory diagrams.
Detailed description of the invention
Below in conjunction with accompanying drawing, one monostable flipflop specific embodiment of the present invention is described further:
One monostable flipflop of the present invention includes: the most monostable trigger module, time-delay reset module；The most monostable described triggering Module is pulsewidth current adjustment monostable trigger circuit based on time delay chain；The most monostable described trigger module and time-delay reset mould Block combines, and constitutes the monostable trigger circuit of pulsewidth current adjustment based on time delay chain and repeatable triggering.Also may be interpreted as: adopt By technical solution of the present invention, both may make up a kind of pulsewidth current adjustment monostable flipflop based on time delay chain, on the other hand, logical Cross the most monostable trigger module and time-delay reset block combiner, it is possible to constitute pulsewidth current adjustment based on time delay chain and repeatable The monostable flipflop triggered.Two embodiments are below divided to be described separately:
Embodiment one: pulsewidth current adjustment monostable flipflop based on time delay chain
Seeing accompanying drawing 2, the pulsewidth current adjustment monostable flipflop based on time delay chain that the present invention proposes, is the most monostable triggering Module, including: the d type flip flop DFF1 of a band reset function, a NAND gate, a phase inverter and two are based on anti-phase The time delay chain (time delay chain 1 and time delay chain 2) of device, does not include any resistance, electric capacity, amplifier and comparator.With tradition monostable Trigger utilizes RC charge timing different, and the ultimate principle of this novel monostable flipflop is to utilize two time delay chains to trigger D Output signal Q of device DFF1 carries out td1(td1+td2) time delay, respectively obtain two time delayed signal Qd1And Qd2, then by Qd1 And Qd2Carrying out logical operations and obtain reset signal RS of d type flip flop DFF1, d type flip flop DFF1 will be carried out multiple by RS reset signal Position, thus obtaining pulsewidth is Qd1And time delay between Q (namely td1) output monostable pulses.
Shown in Fig. 2, the concrete principle of pulsewidth current adjustment monostable flipflop based on time delay chain is as follows:
D type flip flop and whole monostable flipflop are triggered by inputting the rising edge (or trailing edge) triggering signal TR.In order to Obtain the reset signal of d type flip flop, the time delay chain 1 output Q time delay t to d type flip flopd1Obtain Qd1Signal, time delay chain 2 is to Qd1Prolong Time td2Obtain Qd2Signal.Then, to Qd2Carry out anti-phase obtaining, Qd1WithCarry out NAND operation further and obtain reset Signal RS.Fig. 3 is in circuit described in Fig. 2, corresponding to TR signal waveform, and other each point Q, Qd1、Qd2, the oscillogram of RS, by Fig. 3 Can be seen that, when d type flip flop is rising edge triggering, after triggering signal TR uprises, Q uprises immediately, and Qd1Through td1Rear just change Height, then through td2After, Qd2Uprising, now, the output RS step-down of NAND gate, so that d type flip flop resets and makes Q step-down.RS holds Continuing for the low time is td2, subsequently, RS uprises, if TR rising edge arrives again, and circuit repeat the above steps.Therefore can see Going out, the width of this numeral monostable flipflop output pulse is td1, current triggering is terminated and crosses td2After time, circuit can weigh Newly trigger, namely recovery time is td2, ICTRLIt it is bias current.
In Fig. 2, time delay chain 1 or time delay chain 2 include at least two concatenation delay units, and single delay unit includes cascade Two-stage phase inverter, the schematic diagram of phase inverter is as shown in Figure 4.The adjustment of whole time delay chain delay time can be by changing time delay list The number of unit or change the transmission delay value (that is transmission delay value of phase inverter) of each delay unit and realize.If passing through The transmission delay of phase inverter is carried out electric current adjustment, i.e. uses current-steering phase inverter as shown in Figure 5, this current-steering The monostable flipflop of phase inverter, can realize the output monostable pulsewidth current adjustment of trigger, export monostable pulsewidth and biased electrical Stream ICTRLRelation be:
(1)
In formula 1,KFor being proportional toCThe constant of VDD,CFor phase inverter output nodeOUTAll of parasitic capacitance,t d0For base This phase inverter (namely ICTRLDuring for infinity) time delay,N 1Number by the comprised delay unit of time delay chain 1.
Embodiment two: pulsewidth current adjustment based on time delay chain and the monostable flipflop of repeatable triggering
See accompanying drawing 2 and accompanying drawing 6, by the input signal of delay unit each in time delay chain in Fig. 21 is resetted, will Fig. 2 and time-delay reset block combiner, the present invention proposes technical scheme and is exactly: pulsewidth current adjustment based on time delay chain and repeatable The monostable flipflop triggered.In Fig. 6, for produce the time-delay reset module of negative pulse delayed reset signal RST still only by The digital logic gates such as d type flip flop DFF2, phase inverter and the door of band reset and time delay chain 3 are constituted, in normal condition namely without repeating During triggering, trigger DFF2 output signal QRSSignal is reset to low, and output RST signal is high, does not affect monostable flipflop electricity Road；And when the current monostable cycle not yet terminates and once more occurs that input triggers, namely when repeated trigger occurs, QRSBecome immediately For height, output RST signal is low.Through td3After, RS_RT also becomes low, thus by QRSBeing reset to low, output RST becomes again Height, thus can get the negative pulse persistent period is td3Delayed reset signal RST.
In conjunction with the embodiments one and accompanying drawing 6, the monostable of pulsewidth current adjustment based on time delay chain and repeatable triggering is touched The principle sending out device is described as follows:
When within the existing monostable cycle input trigger signal again occur trigger signal along time, time-delay reset module will produce pulsewidth For time delay chain 3 time delay td3Negative pulse reset signal RST, this undersuing RST and each delay unit be originally inputted letter Number phase "AND", the signal obtained is re-used as the new input signal of delay unit.Reset signal RST will be removed previous triggering and produce Time delay so that beginning from repeated trigger, still need to through td1The rising edge of time period Q just can transmit to Qd1, therefore, Export the interval time between twice triggering of monostable pulse extension, it is achieved that repeatable triggering.
It can be seen that compared with prior art, the monostable flipflop circuit based on time delay chain that the present invention proposes only wraps Include the time delay chain being made up of phase inverter and corresponding digital logic gate, it is not necessary to resistance, electric capacity, amplifier and comparator, compatible Standard digital technique and design cycle.And easily realize monostable pulsewidth current adjustment and repeatable triggering, only need to inclined to time delay chain Put electric current to be controlled just realizing monostable pulsewidth current adjustment, only the input signal of each delay unit need to be resetted Just can realize repeatable triggering.Compared to existing method, the monostable trigger utensil based on time delay chain that the present invention proposes There are the advantages such as low cost, low-power consumption, compatible strong, pulsewidth current adjustment and repeatable triggering.
These are only embodiments of the invention, but be not limited to the present invention, all the spirit and principles in the present invention it Interior done any amendment, equivalent or improvement etc., within should be included in scope of the presently claimed invention.

Claims (4)

1. a monostable flipflop, it is characterised in that: including: the most monostable trigger module, time-delay reset module；
The most monostable described trigger module is pulsewidth current adjustment monostable trigger circuit based on time delay chain；Described the most monostable Trigger module and time-delay reset block combiner, constitute the monostable triggering of pulsewidth current adjustment based on time delay chain and repeatable triggering Device circuit；
The most monostable described trigger module includes: trigger DFF1, time delay chain 1 and time delay chain 2, NAND gate, phase inverter；
Described time-delay reset module includes: trigger DFF2, time delay chain 3 and digital logic gate；Described trigger DFF1 and triggering Device DFF2 is the d type flip flop of band reset function；
In the most monostable described trigger module, the time delay chain 1 output letter to being triggered the trigger DFF1 that signal TR triggers by input Number Q carries out td1Time delay, obtains time delayed signal Qd1；Described time delay chain 2 is to Qd1Carry out td2Time delay, obtains time delayed signal Qd2；When by Input triggers signal TR and causes the change of Q to be transferred to Qd1Time, trigger DFF1 is resetted, before making Q be reset to trigger State, further, when the change being triggered the Q that signal TR causes by input is transferred to Qd2Time, discharge reset signal, thus obtain Monostable pulsewidth is td1, triggering recovery time be td2Output single steady signal；Described reset signal is by Qd2Inversion signalWith Qd1Carry out NAND operation to obtain；
In described time-delay reset module, input triggers signal TR and is connected to the triggering clock end of trigger DFF2, trigger DFF2 Output signal QRSObtaining exporting reset signal RST after anti-phase, described reset signal RST is after the time delay of time delay chain 3 Obtaining total delay time is td3Time delayed signal；Described time delayed signal carries out "AND" with described trigger DFF1 output signal Q again Computing, as the low effective reset signal RS_RT of trigger DFF2.
2. a kind of monostable flipflop, it is characterised in that: described time delay chain 1 or time delay chain 2 include at least Two concatenation delay units, single delay unit includes the two-stage phase inverter of cascade；By change delay unit total number or The delay value of single delay unit, obtains the total delay time of different time delay chains, and then obtains different monostable pulsewidths and triggering Recovery time.
3. a kind of monostable flipflop, it is characterised in that: by phase inverter in described delay unit Bias currentI CTRL It is adjusted, it is achieved the current adjustment of phase inverter time delay, and then realizes the electric current of output single steady signal pulsewidth Adjustable.
4. a kind of monostable flipflop, it is characterised in that: within the current monostable cycle, input triggers signal When TR occurs to trigger again, by obtaining Qd1Time delay chain 1 in all delay unit input signals reset, it is achieved single The repeatable triggering of steady state trigger；
The described reset signal for resetting delay unit input signals all in time delay chain 1 produces process: will be multiple The original input signal of each delay unit in position signal RST and time delay chain 1 carries out AND operation, then will obtain after computing Signal is connected to each delay unit input in time delay chain 1.
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110143178A (en) * 2019-04-04 2019-08-20 扬州工业职业技术学院 It is a kind of for traffic and the digital pulse signal identification device of vehicle arrangement
CN111338414A (en) * 2020-03-09 2020-06-26 厦门润积集成电路技术有限公司 Low-power consumption monostable circuit capable of being triggered repeatedly
CN111600581A (en) * 2020-05-14 2020-08-28 南京信息职业技术学院 Digital control monostable trigger and control method thereof

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Publication number Priority date Publication date Assignee Title
US3304437A (en) * 1963-08-20 1967-02-14 Paul K Dano Single-shot multivibrator pulse width controlled by repetition rate
US6710622B1 (en) * 2002-04-12 2004-03-23 National Semiconductor Corp Programmable digital one-shot
CN102394640A (en) * 2011-09-16 2012-03-28 无锡东集电子有限责任公司 Delay lock-loop circuit and quick lock-in algorithm
CN202550983U (en) * 2012-02-29 2012-11-21 成都智利达科技有限公司 Monostable trigger capable of long-time delay

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3304437A (en) * 1963-08-20 1967-02-14 Paul K Dano Single-shot multivibrator pulse width controlled by repetition rate
US6710622B1 (en) * 2002-04-12 2004-03-23 National Semiconductor Corp Programmable digital one-shot
CN102394640A (en) * 2011-09-16 2012-03-28 无锡东集电子有限责任公司 Delay lock-loop circuit and quick lock-in algorithm
CN202550983U (en) * 2012-02-29 2012-11-21 成都智利达科技有限公司 Monostable trigger capable of long-time delay

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110143178A (en) * 2019-04-04 2019-08-20 扬州工业职业技术学院 It is a kind of for traffic and the digital pulse signal identification device of vehicle arrangement
CN111338414A (en) * 2020-03-09 2020-06-26 厦门润积集成电路技术有限公司 Low-power consumption monostable circuit capable of being triggered repeatedly
CN111600581A (en) * 2020-05-14 2020-08-28 南京信息职业技术学院 Digital control monostable trigger and control method thereof
CN111600581B (en) * 2020-05-14 2023-07-25 南京信息职业技术学院 Digitally controlled monostable trigger and control method thereof

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