CN105070318A - High-speed shift register applied to successive approximation type analog-to-digital converter - Google Patents
High-speed shift register applied to successive approximation type analog-to-digital converter Download PDFInfo
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Abstract
The present invention discloses a high-speed shift register applied to a successive approximation type analog-to-digital converter. The high-speed shift register comprises a first D flip-flop (DFF) unit, a second DFF unit and switch arrays K1, K2, ... , KN; wherein the first DFF unit comprises 1 DFF0 and N-1 DFF1s, a reset terminal of the DFF0 and the reset terminal of each DFF1 are connected with sampling control signals, clock terminals of all DFFs are connected with enable signals of a comparator, an input terminal of the DFF0 is grounded, an output signal Q1 is connected with an input terminal of the first DFF1 and is used for controlling a switch K1, and an output signal Q2 of the first DFF1 is connected with an input terminal of the second DFF1 and is used for controlling a switch K2, and so on; and the second DFF unit comprises N DFF1s, the reset terminal of each DFF1 is connected with the sampling control signals, the clock terminal of each DFF1 is separately connected with NAND gate output signals by virtue of the switches K1 to KN, and the input terminal of each DFF1 is separately connected with output signals of a comparator output driving circuit by virtue of the switches K1 to KN. By adopting the high-speed shift register applied to the successive approximation type analog-to-digital converter, the problem of relatively long delay time caused by a conventional structure is effectively solved.
Description
Technical field
The invention belongs to simulation or hybrid digital-analog integrated circuit technical field, be specifically related to the high speed shift register that one is applied to gradual approaching A/D converter (SARADC).
Background technology
In recent years, along with the further raising of performance of analog-to-digital convertor index, particularly along with the development of integrated circuit processing technique, also more and more deep to the research of high-speed asynchronous gradual approaching A/D converter.
The loop principle figure of traditional asynchronous gradual approaching A/D converter as shown in Figure 1, wherein the S end of d type flip flop DFF1 is reset terminal, when the voltage of S end is high level, output terminal Q is low level, when S terminal voltage is low level, the level transmissions that D holds at clock end CP rising edge by d type flip flop DFF1 is held to Q.When the enable signal EN_COMP of comparer COMP is low level time, comparer COMP is in running order, and when enable signal EN_COMP is high level time, comparer COMP is in reset mode, now, output terminal OUTP and OUTN of comparer COMP is all high level.
First introduce the principle of work of whole loop, the working timing figure of conventional asynchronous gradual approaching A/D converter as shown in Figure 2, wherein, T
samplefor the time of sampling, T
approximationfor the time of Approach by inchmeal.Particularly, when sampled signal CLKS is high level, sampling switch SW conducting, two capacitor array DAC_P and DAC_N start to sample to input signal VINP and VINN, and now the S end of d type flip flop DFF1 is high level, so the CLKi be connected with d type flip flop DFF1 output terminal (i=2, N-1, N) be low level, in like manner, Di (i=2,, N-1, N) and be low level.Because sampled signal CLKS is high level, comparer COMP is in reset mode, and Sheffer stroke gate output signal Valid is low level.When sampled signal CLKS becomes after low level from high level, sampling terminates, and meanwhile, d type flip flop DFF1 exits reset mode, now or two of door OR inputs be all low level, so EN_COMP becomes low level, comparer COMP starts to compare for the first time.After comparing end for the first time, control signal Valid becomes high level from low level, and CLK1 becomes high level from low level, and CLK2 to CLKN still keeps low level, the value of D1 is refreshed the Output rusults D for comparer COMP by the rising edge of CLK1, and D2 to DN still remains low level.After this, control signal Valid becomes low level.Due to the existence of circuit delay, after control signal Valid becomes high level, comparer COMP will remain on reset mode a period of time, meanwhile, the voltage V+ of capacitor array DAC_P and DAC_N and V-suspension control signal Di (i=2,, N-1, N) control, start to set up, after V+ and V-has set up, enable signal EN_COMP has become low level through delay after a while, and comparer COMP starts second time and compares.By this rule carry out N time relatively after, the value of D1 to DN is successively all refreshed and only refreshes once, and keep refresh after value, this Approach by inchmeal process completes.Until the next sampling period, sampled signal CLKS becomes high level from low level again, simultaneously by CLKi (i=2 ..., N-1, N) be reset to low level, and simultaneously by Di (i=2 ..., N-1, N) and be reset to low level.
Analyze now the time delay situation in single compare cycle, if for t between the time delay that in d type flip flop DFF1, signal is transferred to Q end from D end
dFF1if the time delay that the CP terminal voltage of a d type flip flop DFF1 rises to high level from low level is t
dLY1, as the above analysis, t time delay of conventional shift register each work period in Fig. 2
d1be made up of two parts, specifically can be expressed as follows:
t
D1＝t
d1+t
d2(1)
As shown in Figure 1, during due to the work of each shift register, from Sheffer stroke gate output signal Valid be input to digital signal Di (i=1,2 ..., N-1, N) and export the delay will experiencing two d type flip flops; On the other hand, Sheffer stroke gate output signal Valid wants a driving N d type flip flop DFF1 simultaneously at every turn, so, can obtain:
t
d1＝2t
DFF1(2)
t
d2＝Nt
DLY1(3)
By the description to conventional asynchronous gradually-appoximant analog-digital converter principle of work and the concrete quantification to two time delays, present inventor analyzes and draws, following three problems are had to should be noted that: first, as shown in Figure 1, due to the tandem working principle of d type flip flop DFF1, can there is a 2t in each work period of shift register
dFF1delay.Second, as shown in Figure 1, during d type flip flop DFF1 in control signal Valid flip-flop shift, the CP end of a driving N d type flip flop DFF1 simultaneously can input stray capacitance, in each work period of shift register, the time delay of the CP end of a driving N d type flip flop DFF1 is Nt
dLY1, and each driven d type flip flop DFF1 of actual needs has and only has one.3rd, based on above-mentioned 2 points, the total delay of each work period of shift register is 2t
dFF1+ Nt
dLY1, suppose that N position gradual approaching A/D converter has N number of compare cycle, so, the shift register total delay time caused by above-mentioned delay is N (2t
dFF1+ Nt
dLY1).
On the basis of Such analysis, present inventor studies discovery, and traditional asynchronous Approach by inchmeal shift register structure is fairly simple, under higher frequency of operation, due to d type flip flop DFF1 tandem working, can cause the time delay that larger; Meanwhile, the input capacitance sum of all d type flip flop DFF1 can become the load capacitance of the trigger pip that comparer exports, and in each work period, in fact the real load capacitance needing to drive is one of them.Therefore, above-mentioned two shortcomings can greatly reduce the Time Created of capacitor array DAC, affect the overall performance of analog to digital converter, cause the work requirements under traditional not competent more high frequency of asynchronous Approach by inchmeal shift register.
Summary of the invention
The technical matters that the time delay brought for Approach by inchmeal shift register structure asynchronous in prior art is longer, the invention provides a kind of high speed shift register being applied to gradual approaching A/D converter.
To achieve these goals, the present invention adopts following technical scheme:
Be applied to a high speed shift register for gradual approaching A/D converter, comprise the first d type flip flop unit, the second d type flip flop unit and switch arrays K1, K2 ..., KN; Wherein,
Described first d type flip flop unit comprises 1 d type flip flop DFF0 and N-1 d type flip flop DFF1, the reset terminal L of d type flip flop DFF0 and the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, the clock end of all d type flip flops is connected with the enable signal EN_COMP of comparer in gradual approaching A/D converter, the input end D ground connection of d type flip flop DFF0, output signal Q1 meets the input end D of first d type flip flop DFF1 and gauge tap K1, the output signal Q2 of first d type flip flop DFF1 meets the input end D of second d type flip flop DFF1 and gauge tap K2, by that analogy,
Described second d type flip flop unit comprises N number of d type flip flop DFF1, the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, first clock end to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal Valid of Sheffer stroke gate in gradual approaching A/D converter, first input end D to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal D of comparer output driving circuit in gradual approaching A/D converter, the output terminal Q of each d type flip flop DFF1 is respectively as the output terminal output digit signals D1 of gradual approaching A/D converter, D2, DN.
The high speed shift register being applied to gradual approaching A/D converter provided by the invention, when every task, input signal D is directly from the D end input of d type flip flop, and numerical code exports, so the propagation delay time of d type flip flop is t from the Q end of d type flip flop
dFF1; Meanwhile, the control signal Valid that comparer exports only drives the CP of a d type flip flop to hold stray capacitance, so the time delay that the CP terminal voltage of d type flip flop DFF1 rises to high level from low level is t
dLY1; On this basis, suppose that N position gradual approaching A/D converter has N number of compare cycle, adopt high speed shift register provided by the invention, its total time delay is N (t
dFF1+ t
dLY1), compare with conventional shift register architecture, what the present invention was total saves time as N (t
dFF1+ (N-1) t
dLY1).
Further, described d type flip flop DFF0 comprises or door OR1, transmission gate S1 and S2, PMOS P0, phase inverter INV1, INV2, INV3 and INV4; Wherein, the signal inputted from described d type flip flop DFF0 input end D is connected with phase inverter INV1 by transmission gate S1, the output of phase inverter INV1 is connected with the drain electrode of PMOS P0 with transmission gate S2, and the source electrode of PMOS P0 meets power vd D, and the output of transmission gate S2 outputs to Q end by phase inverter INV2; Input end that is described or door OR1 connects clock signal C P and reset signal L, or the output signal C of door OR1 produces control signal CN by phase inverter INV3, signal C and CN is as the control signal of transmission gate S1 and S2, the base stage that reset signal L produces control signal LN, control signal LN and PMOS P0 by phase inverter INV4 is connected.
Further, described d type flip flop DFF1 comprises or door OR2, transmission gate S3 and S4, NMOS tube N0, phase inverter INV5, INV6 and INV7; Wherein, the signal inputted from described d type flip flop DFF1 input end D is connected with phase inverter INV5 by transmission gate S3, the output of phase inverter INV5 is connected with the drain electrode of NMOS tube N0 with transmission gate S4, the source ground of NMOS tube N0, and the output of transmission gate S4 outputs to Q end by phase inverter INV6; Input end that is described or door OR2 connects clock signal C P and reset signal S, or the output signal C of door OR2 produces control signal CN by phase inverter INV7, signal C and CN is as the control signal of transmission gate S3 and S4, and reset signal S is connected with the base stage of NMOS tube N0.
Further, described switch arrays K1, K2, the transmission gate that each switch in KN comprises phase inverter INV and is made up of NMOS tube NM and PMOS PM, the input end of described phase inverter INV connects the output signal Qi of d type flip flop in described first d type flip flop unit, the output terminal correspondence of described phase inverter INV produces control signal QiN, described output signal Qi is connected with the base stage of NMOS tube NM, described control signal QiN is connected with the base stage of PMOS PM, the source electrode of described NMOS tube NM is connected with the source electrode of PMOS PM and as the input end of transmission gate, the drain electrode of described NMOS tube NM is connected with the drain electrode of PMOS PM and as the output terminal of transmission gate, wherein, the i=1 in described signal Qi and QiN, 2 ..., N-1, N.
Accompanying drawing explanation
Fig. 1 is the loop principle structural representation of the asynchronous shift register that prior art provides.
Fig. 2 is the overall time diagram of the asynchronous shift register in Fig. 1.
Fig. 3 is the loop principle structural representation being applied to the high-speed asynchronous shift register of gradual approaching A/D converter provided by the invention.
Fig. 4 is the overall time diagram of the high-speed asynchronous shift register being applied to gradual approaching A/D converter in Fig. 3.
Fig. 5 is the theory structure schematic diagram of d type flip flop DFF0.
Fig. 6 is the theory structure schematic diagram of d type flip flop DFF1.
Fig. 7 is the theory structure schematic diagram of switch.
Fig. 8 is the theory structure schematic diagram of comparer output driving circuit DRIVER.
Embodiment
The technological means realized to make the present invention, creation characteristic, reaching object and effect is easy to understand, below in conjunction with concrete diagram, setting forth the present invention further.
Please refer to shown in Fig. 3, the invention provides a kind of high speed shift register being applied to gradual approaching A/D converter, comprise the first d type flip flop unit, the second d type flip flop unit and switch arrays K1, K2 ..., KN; Wherein,
Described first d type flip flop unit comprises 1 d type flip flop DFF0 and N-1 d type flip flop DFF1, the reset terminal L of d type flip flop DFF0 and the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, the clock end of all d type flip flops is connected with the enable signal EN_COMP of comparer in gradual approaching A/D converter, the input end D ground connection of d type flip flop DFF0, output signal Q1 meets the input end D of first d type flip flop DFF1 and gauge tap K1, the output signal Q2 of first d type flip flop DFF1 meets the input end D of second d type flip flop DFF1 and gauge tap K2, by that analogy,
Described second d type flip flop unit comprises N number of d type flip flop DFF1, the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, first clock end to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal Valid of Sheffer stroke gate in gradual approaching A/D converter, first input end D to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal D of comparer output driving circuit in gradual approaching A/D converter, the output terminal Q of each d type flip flop DFF1 is respectively as the output terminal output digit signals D1 of gradual approaching A/D converter, D2, DN.
The high speed shift register being applied to gradual approaching A/D converter provided by the invention, when every task, input signal D is directly from the D end input of d type flip flop, and numerical code exports, so the propagation delay time of d type flip flop is t from the Q end of d type flip flop
dFF1; Meanwhile, the control signal Valid that comparer exports only drives the CP of a d type flip flop to hold stray capacitance, so the time delay that the CP terminal voltage of d type flip flop DFF1 rises to high level from low level is t
dLY1; On this basis, suppose that N position gradual approaching A/D converter has N number of compare cycle, adopt high speed shift register provided by the invention, its total time delay is N (t
dFF1+ t
dLY1), compare with conventional shift register architecture, what the present invention was total saves time as N (t
dFF1+ (N-1) t
dLY1).
As specific embodiment, regulation when d type flip flop output signal Q1, Q2 ..., QN is when being high level, its corresponding K switch 1 controlled, K2 ..., KN conducting, otherwise then disconnect.For d type flip flop DFF0, when reset terminal L is high level time, output terminal Q is reset to high level, and for d type flip flop DFF1, when reset terminal S is high level time, output terminal Q is reset to low level.When the enable signal EN_COMP of comparer COMP is low level time, COMP is in running order; When enable signal EN_COMP is high level time, COMP is in reset mode, and now, output terminal OUTP and OUTN is all high level.
Please refer to shown in Fig. 3 and Fig. 4, when gradual approaching A/D converter is in sample states, sampled signal CLKS is high level, from describing above, now, the output signal Q1 of d type flip flop DFF0 is high level, the output signal Q2 of d type flip flop DFF1, Q3 ..., Q (N-1), QN be low level, thus make switch arrays K1, K2 ..., in KN, only has K switch 1 conducting, and K switch 2, K3 ..., K (N-1), KN disconnect, meanwhile, output digit signals D1, D2 ..., D (N-1), DN be low level.After sampling terminates, sampled signal CLKS becomes low level, d type flip flop DFF0 and DFF1 exits reset mode, comparer COMP enable signal EN_COMP becomes low level, comparer COMP starts to compare for the first time, after comparing end for the first time, the output signal Valid of Sheffer stroke gate NAND becomes high level from low level, now, switch arrays K1, K2, in KN, only has K switch 1 conducting, K switch 2, K3, K (N-1), KN disconnects, so, in described second d type flip flop unit, the input data D of the d type flip flop that connect corresponding to K switch 1 is transferred to D1, and output digit signals D2, D (N-1), DN then keeps low level, simultaneously, comparer COMP enable signal EN_COMP becomes high level from low level, thus, from the principle of d type flip flop, the value of d type flip flop DFF0 output terminal Q1 is refreshed the voltage into now d type flip flop DFF0 input end D, i.e. low level, so the change of output terminal Q1 becomes low level from high level, the value of d type flip flop DFF1 output terminal Q2 is refreshed the voltage into now DFF2 input end D, i.e. high level, so the change of output terminal Q2 becomes high level from low level, output signal Q3, Q4, Q (N-1), QN still remains low level, comparer enters reset mode, complete a compare cycle thus.As shown in Figure 4, can be expressed as the time delay of high speed shift register each work period of the present invention's proposition:
t
D2＝t
DFF1+t
DLY1(4)
According to foregoing description, in whole Approach by inchmeal process, each compare cycle conducting and only actuating switch array K1, K2 ..., a switch in KN, the present invention by successively actuating switch array K1, K2 ..., K1 in KN, K2 ..., the switch such as K (N-1), KN, make in each compare cycle, the output signal Valid of Sheffer stroke gate NAND only drives the stray capacitance of a d type flip flop DFF1 clock end CP; Meanwhile, comparer COMP output driving circuit DRIVER also only needs the stray capacitance of a driving d type flip flop DFF1 input end D, so just greatly reduces the load capacitance of Sheffer stroke gate NAND and the load capacitance of comparer COMP output driving circuit DRIVER.Compare with traditional structure, the size of its load capacitance is the 1/N of traditional structure, the operating rate of shift register can be significantly improved, thus significantly improve the operating rate of gradual approaching A/D converter, suppose that N position gradual approaching A/D converter has N number of compare cycle, so as the above analysis, the shift register total delay time being postponed to cause by the present invention is N (t
dFF1+ t
dLY1).
As specific embodiment, please refer to shown in Fig. 5, described d type flip flop DFF0 comprises or door OR1, transmission gate S1 and S2, PMOS P0, phase inverter INV1, INV2, INV3 and INV4; Wherein, the signal inputted from described d type flip flop DFF0 input end D is connected with phase inverter INV1 by transmission gate S1, the output of phase inverter INV1 is connected with the drain electrode of PMOS P0 with transmission gate S2, and the source electrode of PMOS P0 meets power vd D, and the output of transmission gate S2 outputs to Q end by phase inverter INV2; Input end that is described or door OR1 connects clock signal C P and reset signal L, or the output signal C of door OR1 produces control signal CN by phase inverter INV3, signal C and CN is as the control signal of transmission gate S1 and S2, the base stage that reset signal L produces control signal LN, control signal LN and PMOS P0 by phase inverter INV4 is connected.In the course of work, when reset signal L is high level, output signal C is high level, control signal CN is low level, and control signal LN is low level, and now transmission gate S1 disconnects, A point voltage is pulled upward to high level by PMOS P0, transmission gate S2 conducting, and output terminal Q is high level; When reset signal L is low level, if clock signal C P is also low level, then outputing signal C is low level, control signal CN is high level, and control signal LN is high level, now transmission gate S1 conducting, PMOS P0 disconnects, the input signal of D end is delivered to A point, and transmission gate S2 disconnects, and output terminal Q keeps the value of Last status; When reset signal L is low level, if clock signal C P is high level, then outputing signal C is high level, control signal CN is low level, control signal LN is high level, and now transmission gate S1 disconnects, and PMOS P0 disconnects, transmission gate S2 conducting, the value of output terminal Q is refreshed the value into input end D when transmission gate S1 disconnects.
As specific embodiment, please refer to shown in Fig. 6, described d type flip flop DFF1 comprises or door OR2, transmission gate S3 and S4, NMOS tube N0, phase inverter INV5, INV6 and INV7; Wherein, the signal inputted from described d type flip flop DFF1 input end D is connected with phase inverter INV5 by transmission gate S3, the output of phase inverter INV5 is connected with the drain electrode of NMOS tube N0 with transmission gate S4, the source ground of NMOS tube N0, and the output of transmission gate S4 outputs to Q end by phase inverter INV6; Input end that is described or door OR2 connects clock signal C P and reset signal S, or the output signal C of door OR2 produces control signal CN by phase inverter INV7, signal C and CN is as the control signal of transmission gate S3 and S4, and reset signal S is connected with the base stage of NMOS tube N0.In the course of work, when reset signal S is high level, signal C is high level, and signal CN is low level, and now transmission gate S3 disconnects, and A point voltage is pulled down to low level by NMOS tube N0, transmission gate S4 conducting, and output terminal Q is low level; When reset signal S is low level, if clock signal C P is low level, signal C is low level, signal CN is high level, now transmission gate S3 conducting, and NMOS tube N0 disconnects, the input signal of D end is delivered to A point, and transmission gate S4 disconnects, and output terminal Q keeps the value of Last status; When reset signal S is low level, if clock signal C P is high level, signal C is high level, signal CN is low level, and now transmission gate S3 disconnects, and NMOS tube N0 disconnects, transmission gate S4 conducting, the value of output terminal Q is refreshed the value into input end D when transmission gate S3 disconnects.
As specific embodiment, please refer to shown in Fig. 7, described switch arrays K1, K2, the transmission gate that each switch in KN comprises phase inverter INV and is made up of NMOS tube NM and PMOS PM, the input end of described phase inverter INV connects the output signal Qi of d type flip flop in described first d type flip flop unit, the output terminal correspondence of described phase inverter INV produces control signal QiN, described output signal Qi is connected with the base stage of NMOS tube NM, described control signal QiN is connected with the base stage of PMOS PM, the source electrode of described NMOS tube NM is connected with the source electrode of PMOS PM and as the input end of transmission gate, the drain electrode of described NMOS tube NM is connected with the drain electrode of PMOS PM and as the output terminal of transmission gate, wherein, the i=1 in described signal Qi and QiN, 2 ..., N-1, N.In the course of work, when control signal Qi is high level, control signal QiN is low level, and the transmission gate conducting controlled by control signal Qi and QiN, otherwise then disconnect.
As specific embodiment, please refer to shown in Fig. 8, Fig. 8 is the principle schematic of comparer output driving circuit DRIVER in gradual approaching A/D converter, wherein, the forward output terminal VOUTP of comparer COMP produces signal D by driving circuit BUFFER1, the negative sense output terminal VOUTN of comparer COMP is as the input signal with BUFFER1 same size driving circuit BUFFER2, the output of BUFFER2 is unsettled, the object of such design makes two of comparer COMP output terminal load capacitances equal, thus make comparer COMP realize better coupling.Particularly, because two of comparer COMP output terminal OUTP and OUTN may drive different circuit, the load capacitance causing it to drive is different, here artificially between OUTP, OUTN and its circuit driven, a BUFFER is added, its effect makes two of comparer COMP output terminal OUTP and OUTN be connected to above identical load capacitance, contribute to the imbalance reducing comparer like this, make comparer COMP achieve better coupling.
Known according to the description of aforesaid operating principle, the shift register of traditional structure, the time delay within a work period is t
d1=2t
dFF1+ Nt
dLY1, and the high speed shift register being applied to gradual approaching A/D converter provided by the invention, the time delay within a work period is t
d2=t
dFF1+ t
dLY1, suppose that N position gradual approaching A/D converter has N number of compare cycle, for traditional structure, the time scale that high speed shift register provided by the invention is saved is: (t
d1-t
d2)/t
d1if, hypothesis t
dFF1=t
dLY1, so, the time scale that the present invention saves is N/ (N+2), if get N=10, the time that the present invention saves is 83% of traditional structure, and along with the increase of N value, the present invention saves more obvious relative to the time of traditional structure.
These are only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every equivalent structure utilizing instructions of the present invention and accompanying drawing content to do, is directly or indirectly used in the technical field that other are relevant, all in like manner within scope of patent protection of the present invention.
Claims (4)
1. be applied to a high speed shift register for gradual approaching A/D converter, it is characterized in that, comprise the first d type flip flop unit, the second d type flip flop unit and switch arrays K1, K2 ..., KN; Wherein,
Described first d type flip flop unit comprises 1 d type flip flop DFF0 and N-1 d type flip flop DFF1, the reset terminal L of d type flip flop DFF0 and the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, the clock end of all d type flip flops is connected with the enable signal EN_COMP of comparer in gradual approaching A/D converter, the input end D ground connection of d type flip flop DFF0, output signal Q1 meets the input end D of first d type flip flop DFF1 and gauge tap K1, the output signal Q2 of first d type flip flop DFF1 meets the input end D of second d type flip flop DFF1 and gauge tap K2, by that analogy,
Described second d type flip flop unit comprises N number of d type flip flop DFF1, the reset terminal S of each d type flip flop DFF1 meets sampling control signal CLKS, first clock end to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal Valid of Sheffer stroke gate in gradual approaching A/D converter, first input end D to N number of d type flip flop connects one to one the output terminal of K switch 1 to K switch N, the input end of K switch 1 to K switch N is connected with the output signal D of comparer output driving circuit in gradual approaching A/D converter, the output terminal Q of each d type flip flop DFF1 is respectively as the output terminal output digit signals D1 of gradual approaching A/D converter, D2, DN.
2. the high speed shift register being applied to gradual approaching A/D converter according to claim 1, is characterized in that, described d type flip flop DFF0 comprises or door OR1, transmission gate S1 and S2, PMOS P0, phase inverter INV1, INV2, INV3 and INV4; Wherein, the signal inputted from described d type flip flop DFF0 input end D is connected with phase inverter INV1 by transmission gate S1, the output of phase inverter INV1 is connected with the drain electrode of PMOS P0 with transmission gate S2, and the source electrode of PMOS P0 meets power vd D, and the output of transmission gate S2 outputs to Q end by phase inverter INV2; Input end that is described or door OR1 connects clock signal C P and reset signal L, or the output signal C of door OR1 produces control signal CN by phase inverter INV3, signal C and CN is as the control signal of transmission gate S1 and S2, the base stage that reset signal L produces control signal LN, control signal LN and PMOS P0 by phase inverter INV4 is connected.
3. the high speed shift register being applied to gradual approaching A/D converter according to claim 1, is characterized in that, described d type flip flop DFF1 comprises or door OR2, transmission gate S3 and S4, NMOS tube N0, phase inverter INV5, INV6 and INV7; Wherein, the signal inputted from described d type flip flop DFF1 input end D is connected with phase inverter INV5 by transmission gate S3, the output of phase inverter INV5 is connected with the drain electrode of NMOS tube N0 with transmission gate S4, the source ground of NMOS tube N0, and the output of transmission gate S4 outputs to Q end by phase inverter INV6; Input end that is described or door OR2 connects clock signal C P and reset signal S, or the output signal C of door OR2 produces control signal CN by phase inverter INV7, signal C and CN is as the control signal of transmission gate S3 and S4, and reset signal S is connected with the base stage of NMOS tube N0.
4. the high speed shift register being applied to gradual approaching A/D converter according to claim 1, it is characterized in that, described switch arrays K1, K2, the transmission gate that each switch in KN comprises phase inverter INV and is made up of NMOS tube NM and PMOS PM, the input end of described phase inverter INV connects the output signal Qi of d type flip flop in described first d type flip flop unit, the output terminal correspondence of described phase inverter INV produces control signal QiN, described output signal Qi is connected with the base stage of NMOS tube NM, described control signal QiN is connected with the base stage of PMOS PM, the source electrode of described NMOS tube NM is connected with the source electrode of PMOS PM and as the input end of transmission gate, the drain electrode of described NMOS tube NM is connected with the drain electrode of PMOS PM and as the output terminal of transmission gate, wherein, the i=1 in described signal Qi and QiN, 2 ..., N-1, N.
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| CN106877868A (en) * | 2017-01-16 | 2017-06-20 | 电子科技大学 | A kind of high speed gradual approaching A/D converter |
| CN106941345A (en) * | 2017-03-17 | 2017-07-11 | 中国电子科技集团公司第二十四研究所 | D type flip flop and asynchronous gradual approaching A/D converter |
| CN107017889A (en) * | 2017-02-16 | 2017-08-04 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of successive approximation analog-digital converter |
| CN107947792A (en) * | 2017-12-20 | 2018-04-20 | 中南大学 | A kind of low-power consumption SAR ADC control logic circuits |
| CN110266314A (en) * | 2019-07-25 | 2019-09-20 | 中北大学 | A kind of concentration sequence generator |
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| CN106877868A (en) * | 2017-01-16 | 2017-06-20 | 电子科技大学 | A kind of high speed gradual approaching A/D converter |
| CN106877868B (en) * | 2017-01-16 | 2020-02-14 | 电子科技大学 | High-speed successive approximation type analog-to-digital converter |
| CN107017889A (en) * | 2017-02-16 | 2017-08-04 | 广东顺德中山大学卡内基梅隆大学国际联合研究院 | A kind of successive approximation analog-digital converter |
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| CN106941345B (en) * | 2017-03-17 | 2020-03-10 | 中国电子科技集团公司第二十四研究所 | D trigger and asynchronous successive approximation type analog-to-digital converter |
| CN107947792A (en) * | 2017-12-20 | 2018-04-20 | 中南大学 | A kind of low-power consumption SAR ADC control logic circuits |
| CN107947792B (en) * | 2017-12-20 | 2020-10-13 | 中南大学 | Low-power-consumption SAR ADC control logic circuit |
| CN110266314A (en) * | 2019-07-25 | 2019-09-20 | 中北大学 | A kind of concentration sequence generator |
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