CN104883188B - A kind of Flash ADC of full digital starting - Google Patents

A kind of Flash ADC of full digital starting Download PDF

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CN104883188B
CN104883188B CN201510220289.2A CN201510220289A CN104883188B CN 104883188 B CN104883188 B CN 104883188B CN 201510220289 A CN201510220289 A CN 201510220289A CN 104883188 B CN104883188 B CN 104883188B
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delay chain
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CN104883188A (en
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任俊彦
薛香艳
陈迟晓
冯泽民
许俊
叶凡
李宁
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Fudan University
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Abstract

本发明属于集成电路技术领域,具体为一种全数字实现的闪烁型模数转换器。本发明结构包括:由两组并联三态门和去耦合电容构成的差分信号采样保持阵列,由与非门/非门和去耦合电容构成的具有使用内置参考电压的(2N‑1)个差分延时链对阵列,以及锁存器阵列;差分信号经两个相同的采样保持阵列,每一个DDLP对应一对差分参考电压,差分信号在保持期间控制相应DDLP产生不同延时,延时链的延时由若干个与非门和非门决定,并经过去耦合电容实现微调;再经过锁存器比较,得到DDLP的两个输出上升沿的延时大小,得到温度计码的数字比较输出。本发明可以在较高速度下实现较好的模数转换性能,节省面积、功耗,同时也降低了设计复杂度。

The invention belongs to the technical field of integrated circuits, in particular to an all-digital realization of a blinking analog-to-digital converter. The structure of the present invention includes: a differential signal sampling and holding array composed of two sets of parallel tri-state gates and decoupling capacitors; Differential delay chain pair array, and latch array; the differential signal passes through two identical sample and hold arrays, each DDLP corresponds to a pair of differential reference voltages, and the differential signal controls the corresponding DDLP to generate different delays during the hold period, the delay chain The delay is determined by several NAND gates and NOT gates, and is fine-tuned by decoupling capacitors; and then compared with latches, the delay of the two output rising edges of DDLP is obtained, and the digital comparison output of the thermometer code is obtained. The invention can realize better analog-to-digital conversion performance at higher speed, save area and power consumption, and reduce design complexity at the same time.

Description

一种全数字实现的闪烁型模数转换器An All-Digital Realized Blinking Analog-to-Digital Converter

技术领域technical field

本发明属于集成电路技术领域,具体涉及一种全数字实现的闪烁型模数转换器。The invention belongs to the technical field of integrated circuits, and in particular relates to an all-digital realization of a blinking analog-to-digital converter.

背景技术Background technique

随着工艺的不断进步,由于短沟道效应的影响,模拟电路不能实现有效的按比例缩小,功耗也比较大,同时其强烈依靠设计者的经验,缺少合适的高效自动化设计工具,而传统的模数转换器,无论是逐次比较结构,还是闪烁型结构,流水线结构,都有相当大部分的模拟部分,这降低了模数转换器的设计效率。而数字电路则可弥补上述模拟电路的不足,充分利用工艺先进工艺带来的优势。With the continuous progress of the technology, due to the influence of the short channel effect, the analog circuit cannot be effectively scaled down, and the power consumption is relatively large. At the same time, it strongly relies on the experience of the designer and lacks suitable and efficient automatic design tools. The analog-to-digital converters, whether it is a sequential comparison structure, a blinking structure, or a pipeline structure, have a considerable part of the analog section, which reduces the design efficiency of the analog-to-digital converter. The digital circuit can make up for the shortcomings of the above-mentioned analog circuit and make full use of the advantages brought by the advanced technology.

传统闪烁型模数转换器的结构如图3所示,差分输入信号分别通过四输入差分比较器与经电阻分压的差分参考电压进行比较,得到温度计码比较结果。这里使用较多的电阻,增加了面积,同时使用大量模拟比较器,增加面积的同时也花费大量功耗。The structure of the traditional blinking analog-to-digital converter is shown in Figure 3. The differential input signal is compared with the differential reference voltage divided by the resistor through the four-input differential comparator to obtain the thermometer code comparison result. More resistors are used here, which increases the area, and a large number of analog comparators are used at the same time, which consumes a lot of power consumption while increasing the area.

为解决传统模拟实现的模数转换器在功耗以及面积上的浪费,并提高模数转换器的设计自动化程度及效率,本发明提出了一种全数字搭建实现的闪烁型模数转换器,将传统闪烁型模数转换器中的各模块全部用数字标准单元库中的单元代替,完成模数转换器的全数字实现。采样保持电路使用三态门阵列以及去耦合电容阵列(201)完成,而比较器部分则采用由与非门/非门/去耦合电容组成的DDLP阵列(202),每个DDLP经过锁存器比较产生对应的温度计码输出结果。In order to solve the waste of power consumption and area of the analog-to-digital converter implemented by traditional analog, and improve the design automation and efficiency of the analog-to-digital converter, the present invention proposes a flashing analog-to-digital converter implemented by all-digital construction. All the modules in the traditional blinking analog-to-digital converter are replaced by the units in the digital standard cell library, and the full digital realization of the analog-to-digital converter is completed. The sample and hold circuit is completed using a tri-state gate array and a decoupling capacitor array (201), while the comparator part uses a DDLP array (202) composed of a NAND gate/NOR gate/decoupling capacitor, and each DDLP passes through a latch The comparison produces the corresponding thermometer code output.

发明内容Contents of the invention

本发明的目的在于提供一种面积小、功耗低的全数字实现的闪烁型模数转换器。The object of the present invention is to provide an all-digital flashing analog-to-digital converter with small area and low power consumption.

本发明提出的全数字实现的闪烁型模数转换器,其结构包括:由两组并联三态门和去耦合电容构成的差分信号采样保持阵列(201),由与非门/非门和去耦合电容构成的具有使用内置参考电压的(2N-1)个差分延时链对(Differential Delay Line Pair,以下简称DDLP)阵列(202),以及锁存器阵列;差分信号经两个相同的采样保持阵列,由于每一个DDLP对应一对差分参考电压,差分信号在保持期间控制相应DDLP产生不同延时,延时链的延时是由若干个与非门和非门决定,并经过去耦合电容实现微调;再经过锁存器比较,得到DDLP的两个输出上升沿的延时大小,从而得到温度计码的数字比较输出。The flicker analog-to-digital converter proposed by the present invention has a structure including: a differential signal sampling and holding array (201) composed of two sets of parallel tri-state gates and decoupling capacitors, and a NAND gate/NOR gate and decoupling capacitor (2 N -1) differential delay chain pairs (Differential Delay Line Pair, hereinafter referred to as DDLP) arrays (202) with built-in reference voltages formed by coupling capacitors, and a latch array; the differential signal passes through two identical Sample and hold array, since each DDLP corresponds to a pair of differential reference voltages, the differential signal controls the corresponding DDLP to generate different delays during the hold period, the delay of the delay chain is determined by several NAND gates and NOT gates, and is decoupled The capacitor realizes fine-tuning; and then compares the latch to obtain the delay of the two output rising edges of DDLP, thereby obtaining the digital comparison output of the thermometer code.

本发明中,差分信号采样保持电路(201)主要采用三态门和去耦合电容来实现,如图1所示,主要由12个MOS管M1~M12电路连接组成;其中,NMOS管M1和M2组成反相器,得到输入使能信号OE的反相;NMOS管M3、M4、M5、M6组成或非门,此或非门的输入为OE的反相和输入信号I,或非门的输出作为PMOS管M12的栅极控制信号;由NMOS管M7、M8、M9、M10组成的与非门,使能信号OE和输入信号I输入到由NMOS管M7、M8、M9、M10组成的与非门中,与非门的输出作为PMOS管M11的栅极控制信号;PMOS管M11和M12的共同漏极作为整个三态门的输出;输入I处接高电平,使能端OE处接时钟,而输入待采样信号通过输出端PMOS管,在OE的控制下可实现周期性的采样;整个三态门实现的效果是,OE为低电平时,输出浮空;OE为高电平时,输出跟随输入I。这里三态门用作采样电路的接法和工作原理如下,输入I接高电压VDD,这样中间信号线Mid(图中为红色线)一直为低电平,3个NMOS管M4、M7、M12全部关断,NMOS管M10始终导通;三态门的使能端OE接入时钟,时钟经过反向后加在PMOS管M11的栅极,输入待采样信号vin通过PMOS管M11的源级在OE的控制下被周期性的采样和保持。根据对采样保持电路驱动能力的要求,采用若干个图1结构组成采样阵列,采样阵列后接若干去耦合电容作保持电容。In the present invention, the differential signal sampling and holding circuit (201) is mainly realized by using tri-state gates and decoupling capacitors, as shown in Figure 1, and is mainly composed of 12 MOS transistors M 1 -M 12 circuit connections; wherein, the NMOS transistor M 1 and M 2 form an inverter to obtain the inversion of the input enable signal OE; NMOS transistors M 3 , M 4 , M 5 , and M 6 form a NOR gate, and the input of this NOR gate is the inversion and input of OE The signal I, the output of the NOR gate is used as the gate control signal of the PMOS transistor M12 ; the NAND gate composed of the NMOS transistors M7 , M8 , M9 , M10 , the enable signal OE and the input signal I are input to the In the NAND gate composed of NMOS transistors M 7 , M 8 , M 9 , and M 10 , the output of the NAND gate serves as the gate control signal of the PMOS transistor M 11 ; the common drain of the PMOS transistors M 11 and M 12 serves as the gate control signal of the entire three The output of the state gate; the input I is connected to a high level, the enable terminal OE is connected to the clock, and the input signal to be sampled passes through the output PMOS tube, and periodic sampling can be realized under the control of OE; the entire tri-state gate realizes The effect is that when OE is low, the output floats; when OE is high, the output follows the input I. Here, the connection method and working principle of the tri-state gate used as a sampling circuit are as follows. The input I is connected to the high voltage VDD, so that the intermediate signal line Mid (the red line in the figure) is always low, and the three NMOS tubes M 4 and M 7 , M 12 are all turned off, NMOS tube M 10 is always on; the enable terminal OE of the tri-state gate is connected to the clock, the clock is reversed and then added to the gate of the PMOS tube M 11 , and the input signal vin to be sampled passes through the PMOS tube The source level of M11 is sampled and held periodically under the control of OE. According to the requirements of the driving ability of the sample and hold circuit, several structures in Figure 1 are used to form a sampling array, and a number of decoupling capacitors are connected after the sampling array as holding capacitors.

本发明中,差分信号是先通过DDLP阵列(202)转换为相应的延时信息再进行比较的。DDLP的设计方案是,对于一对指定的差分参考电压vrefp,vrefn,设计两个延时链:延时链A和延时链B,使得输入vip,vin分别为相应的参考电压vrefp,vrefn时,延时链的输出上升沿同时到达。这样,当延时链A的输入大于vrefp(此时延时链B的输入小于vrefn),延时链A的延时就小于延时链B,输出的上升沿较延时链B更早到达,两个输出信号被相应锁存器锁存,得到的比较结果为“1”,反之亦然。对于所有的参考电压对都采用此思路进行设计,即,对N位的闪烁型模数转换器,需要设计(2N-1)个DDLP。但是由于是差分实现,最大的(2N-1-1)个参考电压对与最小的(2N-1-1)各参考电压对是对称的,这样,只要仿真得出最大的2N-1个参考电压对对应的DDLP即可, 剩余的(2N-1-1)个DDLP,只需将对应的输入信号对调即可。In the present invention, the differential signal is first converted into corresponding delay information through the DDLP array (202) and then compared. The design scheme of DDLP is, for a pair of specified differential reference voltages vrefp, vrefn, design two delay chains: delay chain A and delay chain B, so that the input vip, vin are the corresponding reference voltage vrefp, vrefn respectively , the output rising edges of the delay chain arrive at the same time. In this way, when the input of delay chain A is greater than vrefp (at this time, the input of delay chain B is less than vrefn), the delay of delay chain A is less than that of delay chain B, and the rising edge of the output arrives earlier than delay chain B , the two output signals are latched by the corresponding latches, and the result of the comparison is "1", and vice versa. All reference voltage pairs are designed using this idea, that is, for an N-bit blinking analog-to-digital converter, (2 N -1) DDLPs need to be designed. However, due to the differential implementation, the largest (2 N-1 -1) reference voltage pairs and the smallest (2 N-1 -1) reference voltage pairs are symmetrical. In this way, as long as the simulation obtains the largest 2 N- One reference voltage pair is sufficient for the corresponding DDLP, and the remaining (2 N-1 -1) DDLPs only need to swap the corresponding input signals.

本发明中,延时链的延时由两部分组成,如图2所示。每个延时链首先由若干个基本延时单元串联而成,以确定其延时的范围。基本延时单元由与非门和非门依次连接组成,如图2上部所示,与非门中接地的NMOS管N2和其中一个PMOS管P2的栅极都接输入控制信号In,而其余NMOS管N1和PMOS管P1栅极接时钟Clock。输入控制信号In保持在较大的水平,以使PMOS管P2一直关断而NMOS管N2一直导通,这样Clock到输出的延时由NMOS管N2的栅极电压,也就是In控制。假如In增加,过NMOS管N2的电流也增加,输出处Clock的翻转也更迅速。反之亦然。与非门后的非门是为了保证输出与输入同相。若干个这样的基本单元串联时,每个基本单元共用输入控制信号In,而输入Clock为前一个基本单元的输出。这样每个单元延时的叠加即为整个延时链的延时。延时链后面接去耦合电容,可以实现微调延时,以使DDLP精确满足设计要求,能够实现一定精度的比较和锁存。In the present invention, the delay of the delay chain is composed of two parts, as shown in FIG. 2 . Each delay chain is composed of several basic delay units connected in series to determine its delay range. The basic delay unit is composed of NAND gates and NOT gates connected in sequence, as shown in the upper part of Figure 2, the NMOS transistor N2 of the NAND gate and the gate of one of the PMOS transistors P2 are connected to the input control signal In, and Gates of the remaining NMOS transistor N1 and PMOS transistor P1 are connected to the clock Clock. The input control signal In is kept at a relatively large level, so that the PMOS transistor P2 is always turned off and the NMOS transistor N2 is always turned on, so that the delay from Clock to output is controlled by the gate voltage of the NMOS transistor N2 , which is In . If In increases, the current through the NMOS transistor N2 also increases, and the inversion of the Clock at the output is also faster. vice versa. The NOT gate after the NAND gate is to ensure that the output is in phase with the input. When several such basic units are connected in series, each basic unit shares the input control signal In, and the input Clock is the output of the previous basic unit. In this way, the superposition of each unit delay is the delay of the entire delay chain. Decoupling capacitors are connected behind the delay chain, which can realize fine-tuning delay, so that DDLP can accurately meet the design requirements, and can realize comparison and latching with a certain accuracy.

本发明使用三态门单元和去耦合电容构建采样保持电路;差分输入信号分别通过若干个精确仿真的差分延时链对得到不同的延时,再经锁存器比较两个延时大小,完成与相应差分参考电压对的比较,得到对应的温度计码。延时链的延时主要由与非门/非门链决定,并通过去耦合电容进行微调,以满足预设在差分延时链对中的差分参考电压的要求。对于N位的闪烁型模数转换器,根据每对差分参考电压,仿真得到相应的差分延时链对,所以差分延时链对个数为(2N-1)。这种全数字搭建的N 位闪烁型模数转换器无需输入参考电压,其参考电压内置于(2N-1)个差分延时链对中,可以在较高速度下实现较好的模数转换性能,节省面积、功耗,同时也大大降低了设计复杂度。The present invention uses a tri-state gate unit and a decoupling capacitor to build a sample-and-hold circuit; the differential input signal passes through several accurately simulated differential delay chain pairs to obtain different delays, and then compares the two delays through a latch to complete A comparison with the corresponding differential reference voltage pair results in a corresponding thermometer code. The delay of the delay chain is mainly determined by the NAND gate/NOR gate chain, and is fine-tuned by the decoupling capacitor to meet the requirement of the differential reference voltage preset in the differential delay chain pair. For an N-bit blinking analog-to-digital converter, according to each pair of differential reference voltages, the corresponding differential delay chain pair is simulated, so the number of differential delay chain pairs is (2 N -1). This all-digital N-bit blinking analog-to-digital converter does not need to input a reference voltage, and its reference voltage is built into (2 N -1) differential delay chain pairs, which can achieve better analog-to-digital conversion at higher speeds. Conversion performance, saving area and power consumption, and greatly reducing design complexity.

附图说明Description of drawings

图1为实现采样保持电路的三态门的连接方式。Fig. 1 is the connection mode of the tri-state gate realizing the sampling and holding circuit.

图2为DDLP的实现方式。Figure 2 shows the implementation of DDLP.

图3为传统闪烁型模数转换器的实现方式。Figure 3 shows the implementation of a traditional blinking analog-to-digital converter.

图4为本发明总体结构图示。Fig. 4 is a schematic diagram of the overall structure of the present invention.

具体实施方式Detailed ways

下面对本发明中提出的一种全数字实现的闪烁型模数转换器作进一步说明。An all-digital implementation of the blinking analog-to-digital converter proposed in the present invention will be further described below.

本发明提出的全数字实现的闪烁型模数转换器,其特点有三个,分别为:由三态门/去耦合电容阵列构成的采样保持电路(201),由DDLP阵列构成的无参考电压输入的比较器结构(202),由与非门/非门粗调延时,去耦合电容微调延时的延时链实现方式(图2)。The all-digital implementation of the blinking analog-to-digital converter proposed by the present invention has three characteristics, namely: a sample-and-hold circuit (201) composed of a tri-state gate/decoupling capacitor array, and a non-reference voltage input circuit composed of a DDLP array. The comparator structure ( 202 ) is realized by a delay chain with a NAND gate/NOR gate for coarse delay adjustment and a decoupling capacitor for fine adjustment delay delay ( FIG. 2 ).

为解决传统模拟或模数混合模数转换器造成的功耗及面积的浪费,并提高自动化设计效率,本发明提出了一种全数字实现的闪烁型模数转换器。该全数字实现的闪烁型模数转换器与传统闪烁型模数转换器相比,其特征在于所有电路模块都使用标准单元库中的数字单元实现。首先,对于传统模拟实现的采样保持电路,这里取而代之的是三态门。In order to solve the waste of power consumption and area caused by traditional analog or analog-to-digital hybrid analog-to-digital converters, and to improve the efficiency of automatic design, the present invention proposes an all-digital realization of a blinking analog-to-digital converter. Compared with the traditional blinking analog-digital converter, the all-digital realization of the blinking analog-to-digital converter is characterized in that all circuit modules are implemented using digital units in a standard unit library. First of all, for the sample-and-hold circuit implemented by traditional analog, it is replaced by a tri-state gate.

图1是标准单元库中的三态门电路。M1和M2组成反相器,得到输入使能信号OE的反相。M3、M4、M5、M6组成或非门,此或非门的输入为OE的反相和输入信号I。或非门的输出作为M12的栅极控制信号。同时OE和输入信号I输入到由M7、M8、M9、M10组成的与非门中,与非门的输出作为M11的栅极控制信号。M11和M12的共同漏极作为整个三态门的输出。整个三态门实现的效果是,OE为低电平时,输出浮空;OE为高电平时,输出跟随输入I。这里三态门用作采样点路的接法和工作原理如下,输入I接高电压VDD,这样中间信号线Mid(图中为红色线)一直为低电平,3个NMOS管M4、M7、M12全部关断,NMOS管M10始终导通;三态门的使能端OE接入时钟,时钟经过反向后加在PMOS管M11的栅极,输入待采样信号通过PMOS管M11在OE的控制下被周期性的采样和保持。根据对采样保持电路驱动能力的要求,需要采用若干个图1结构组成采样阵列,采样阵列后接若干去耦合电容作保持电容。其次,这里面的比较器采用若干个DDLP实现。每个DDLP对应一个差分参考电压对,包含两个延时链,两个延时链的设计需要满足的条件是,输入信号分别为对应参考电压对时,两个延时链的输出上升沿同时到达。这样,后续电路只需比较DDLP两个输出的延时先后即可间接得到输入差分信号和相应参考电压的比较结果,获得相应的温度计码。DDLP延时链结构如图2。延时链延时的确定采用粗调+微调两个步骤,前者由若干个与非门/非门组成的基本延时单元组成,后者由去耦合电容完成。基本延时单元为中与非门的接法如图2上部所示,接地的NMOS管N2和其中一个PMOS管P2的栅极都接输入控制信号In,而其余管子N1和P1栅极接时钟Clock。输入控制信号In保持在较大的水平,以使P2一直关断而N2一直导通,这样Clock到输出的延时由N2的栅极电压,也就是In控制。假如In增加,过N2的电流也增加,输出处Clock的翻转也更迅速。反之亦然。与非门后接非门是为了保证输出与输入同相。若干个这样的基本单元串联时,每个基本单元共用输入控制信号In,而输入Clock为前一个基本单元的输出。这样每个单元延时的叠加实现整个延时链的延时粗调。这种DDLP比较结构的参考电压预设并内置于两个延时链中,无需外部输入参考电压。Figure 1 is a three-state gate circuit in the standard cell library. M 1 and M 2 form an inverter to obtain the inversion of the input enable signal OE. M 3 , M 4 , M 5 , and M 6 form a NOR gate, and the input of this NOR gate is the inversion of OE and the input signal I. The output of the NOR gate is used as the gate control signal of M12 . At the same time, OE and the input signal I are input to the NAND gate composed of M 7 , M 8 , M 9 , and M 10 , and the output of the NAND gate is used as the gate control signal of M 11 . The common drain of M11 and M12 is used as the output of the whole tri-state gate. The effect achieved by the entire tri-state gate is that when OE is low, the output is floating; when OE is high, the output follows the input I. Here, the connection method and working principle of the tri-state gate used as the sampling point circuit are as follows. The input I is connected to the high voltage VDD, so that the intermediate signal line Mid (the red line in the figure) is always low, and the three NMOS tubes M 4 , M 7. M 12 is all turned off, and NMOS tube M 10 is always on; the enable terminal OE of the tri-state gate is connected to the clock, and the clock is reversed and added to the gate of PMOS tube M 11 , and the input signal to be sampled passes through the PMOS tube M 11 is periodically sampled and held under the control of OE. According to the requirements for the driving ability of the sample and hold circuit, it is necessary to use several structures in Figure 1 to form a sampling array, and a number of decoupling capacitors are connected after the sampling array as holding capacitors. Secondly, the comparators here are implemented using several DDLPs. Each DDLP corresponds to a differential reference voltage pair, including two delay chains. The design of the two delay chains needs to satisfy the condition that when the input signals are the corresponding reference voltage pairs, the output rising edges of the two delay chains are simultaneously arrive. In this way, the subsequent circuit only needs to compare the delay sequence of the two outputs of DDLP to indirectly obtain the comparison result of the input differential signal and the corresponding reference voltage, and obtain the corresponding thermometer code. The structure of the DDLP delay chain is shown in Figure 2. The determination of the delay chain delay adopts two steps of coarse adjustment and fine adjustment. The former is composed of a number of basic delay units composed of NAND gates/NOR gates, and the latter is completed by decoupling capacitors. The basic delay unit is the NAND gate. The connection method is shown in the upper part of Figure 2. The gate of the grounded NMOS transistor N2 and one of the PMOS transistors P2 is connected to the input control signal In, while the other transistors N1 and P1 The gate is connected to the clock Clock. The input control signal In is kept at a relatively large level, so that P2 is always turned off and N2 is always on, so that the delay from Clock to output is controlled by the gate voltage of N2 , that is, In. If In increases, the current through N2 also increases, and the inversion of Clock at the output is also faster. vice versa. The NAND gate is followed by a NOT gate to ensure that the output is in phase with the input. When several such basic units are connected in series, each basic unit shares the input control signal In, and the input Clock is the output of the previous basic unit. In this way, the superposition of the delay of each unit realizes the rough adjustment of the delay of the entire delay chain. The reference voltage of this DDLP comparison structure is preset and built into the two delay chains, no external reference voltage input is required.

本发明采用的DDLP延时链采用的是标准库中的二输入与非门,也可以采用多输入与非门或者高阈值电压(HVT)/低阈值电压(LVT)库中的相应模块实现延时链。The DDLP delay chain used in the present invention uses the two-input NAND gate in the standard library, and can also use the corresponding modules in the multi-input NAND gate or the high threshold voltage (HVT)/low threshold voltage (LVT) library to realize the delay. time chain.

本发明中输入控制信号对延时链延时的控制使负相关的,也可以采用正相关的控制思路,只要保持延时与输入信号的关系单调即可。In the present invention, if the input control signal is negatively correlated to the delay control of the delay chain, a positive correlation control idea can also be adopted, as long as the relationship between the delay time and the input signal is kept monotonous.

本发明使用时钟的上升沿延时作为比较依据,也可以采用下降沿作为延时转换和比较的依据。The present invention uses the rising edge delay of the clock as the basis for comparison, and the falling edge can also be used as the basis for delay conversion and comparison.

Claims (2)

1. a kind of Flash ADC of full digital starting, it is characterised in that structure includes:
The differential signal sampling being made up of two groups of parallel connection triple gates and decoupling capacitance keeps array(201);By NAND gate/NOT gate Have with what decoupling capacitance was formed using built-in reference voltage(2N-1)Individual differential delay chain is to DDLP arrays(202);With And latch arrays;Wherein:
Differential signal keeps array, corresponding a pair of the differential reference voltages of each DDLP, difference letter by two identical samplings Corresponding DDLP number is controlled to produce different delayed time during holding, the delay of time delay chain is determined by several NAND gates and NOT gate, and Realize and finely tune by decoupling capacitance;Compare again by latch, obtain the delay size of DDLP two output rising edges, from And obtain the digital comparison output of thermometer-code;
Described differential signal sampling keeps array(201)Mainly realized using triple gate and decoupling capacitance;Tri-state gate circuit By 12 metal-oxide-semiconductor M1~M12Circuit connection composition;Wherein, metal-oxide-semiconductor M1And M2Phase inverter is formed, obtains inputting enable signal OE's It is anti-phase;Metal-oxide-semiconductor M3、M4、M5、M6Form nor gate, this nor gate input for OE anti-phase and input signal I, nor gate it is defeated Go out as PMOS M12Grid control signal;By metal-oxide-semiconductor M7、M8、M9、M10NAND gate is formed, enable signal OE and input are believed Number I is input to by metal-oxide-semiconductor M7、M8、M9、M10In the NAND gate of composition, the output of NAND gate is as PMOS M11Grid control Signal;Metal-oxide-semiconductor M11And M12Output of the common drain as whole triple gate;High level is connect at input I, is connect at Enable Pin OE Clock, and signal to be sampled is inputted by output end PMOS, periodically sampling can be achieved under OE control;By several Tri-state gate circuit forms sampling array, and sampling array is followed by some decoupling capacitances and makees holding capacitor.
2. the Flash ADC of full digital starting according to claim 1, it is characterised in that in described DDLP, For a pair of differential reference voltage vrefp, vrefn specified, two time delay chains are designed with:Time delay chain A and time delay chain B so that Input vip, vin are respectively corresponding differential reference voltage vrefp, and during vrefn, the output rising edge of time delay chain reaches simultaneously; So, when time delay chain A input is more than vrefp, time delay chain A delay is less than time delay chain B, and the rising edge of output is compared with time delay chain B is reached earlier, and two output signals are latched by respective latch, and obtained comparative result is " 1 ", and vice versa;For all Reference voltage to being all designed using this thinking, i.e. to the Flash ADC of N positions, design(2N-1)Individual DDLP;
Wherein, the delay of time delay chain is made up of two parts;Each time delay chain is in series by several basic delay units first, To determine the scope of its delay;Basic delay unit is sequentially connected the NMOS for forming, being grounded in NAND gate by NAND gate and NOT gate Pipe N2With one of PMOS P2Grid all meet input control signal In, and NMOS tube N1With PMOS P1Grid connects clock Clock;Input control signal In is maintained at larger level, so that PMOS P2Turn off and NMOS tube N always2It is constantly on, this Sample Clock is to the delay exported by NMOS tube N2Grid voltage, that is, In control;Several above-mentioned basic delay unit strings During connection, each basic delay unit shares input control signal In, and it is the defeated of previous basic delay unit to input Clock Go out;The superposition of so each basic delay unit delay is the delay of whole time delay chain;Decoupling capacitance is connect behind time delay chain, To realize fine setting delay.
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