CN104883188B - A kind of Flash ADC of full digital starting - Google Patents
A kind of Flash ADC of full digital starting Download PDFInfo
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- CN104883188B CN104883188B CN201510220289.2A CN201510220289A CN104883188B CN 104883188 B CN104883188 B CN 104883188B CN 201510220289 A CN201510220289 A CN 201510220289A CN 104883188 B CN104883188 B CN 104883188B
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Abstract
The invention belongs to technical field of integrated circuits, specially a kind of Flash ADC of full digital starting.Structure of the present invention includes：The differential signal sampling being made up of two groups of parallel connection triple gates and decoupling capacitance keeps array, is had by what NAND gate/NOT gate and decoupling capacitance were formed using built-in reference voltage（2N‑1）Individual differential delay chain is to array, and latch arrays；Differential signal keeps array through two identical samplings, corresponding a pair of the differential reference voltages of each DDLP, differential signal controls corresponding DDLP to produce different delayed time during holding, and the delay of time delay chain is determined by several NAND gates and NOT gate, and realizes fine setting by decoupling capacitance；Compare again by latch, obtain the delay size of DDLP two output rising edges, obtain the digital comparison output of thermometer-code.The present invention can realize preferable analog-to-digital conversion performance at the higher speeds, save area, power consumption, while also reduce design complexities.
Description
Technical field
The invention belongs to technical field of integrated circuits, and in particular to a kind of Flash ADC of full digital starting.
Background technology
With the continuous progress of technique, due to the influence of short-channel effect, analog circuit can not be realized effectively in proportion
Reducing, power consumption is also bigger, while its strong experience for relying on designer, lacks suitable high-efficient automatic design tool, and
Traditional analog-digital converter, either gradually comparative structure, or flicker type structure, pipeline organization, there is significant fraction
Analog portion, it reduce the design efficiency of analog-digital converter.And digital circuit can then make up the deficiency of above-mentioned analog circuit,
The advantage for making full use of technique advanced technologies to bring.
The structure of conventional Flash type analog-to-digital converter is as shown in figure 3, differential input signal passes through four input difference ratios respectively
Compared with device compared with the differential reference voltage through electric resistance partial pressure, thermometer-code comparative result is obtained.Used here as more electricity
Resistance, area is added, while use a large amount of analog comparators, a large amount of power consumptions are also spent while increasing area.
To solve waste of the analog-digital converter of traditional analog realization in power consumption and area, and improve analog-digital converter
Design automation degree and efficiency, the present invention propose a kind of digital Flash ADC for building realization, will pass
Each module in system Flash ADC is all replaced with the unit in digital standard cell library, completes analog-digital converter
Full digital starting.Sampling hold circuit uses three-state gate array and decoupling capacitance array（201）Complete, and comparator part
Then using the DDLP arrays being made up of NAND gate/NOT gate/decoupling capacitance（202）, each DDLP compares generation by latch
Corresponding thermometer-code output result.
The content of the invention
It is an object of the invention to provide a kind of Flash ADC of small, the low in energy consumption full digital starting of area.
The Flash ADC of full digital starting proposed by the present invention, its structure include：By two groups of parallel connection triple gates
The differential signal sampling formed with decoupling capacitance keeps array（201）, the tool that is made up of NAND gate/NOT gate and decoupling capacitance
Have using built-in reference voltage（2N-1）Individual differential delay chain pair（Differential Delay Line Pair, it is simple below
Claim DDLP）Array（202）, and latch arrays；Differential signal keeps array through two identical samplings, due to each
Corresponding a pair of the differential reference voltages of DDLP, differential signal control corresponding DDLP to produce different delayed time during holding, time delay chain
Delay is determined by several NAND gates and NOT gate, and realizes fine setting by decoupling capacitance；Compare again by latch, obtain
The delay size of DDLP two output rising edges, so as to obtain the digital comparison of thermometer-code output.
In the present invention, differential signal sampling hold circuit（201）Mainly realized using triple gate and decoupling capacitance, such as
Shown in Fig. 1, mainly by 12 metal-oxide-semiconductor M1~M12Circuit connection composition；Wherein, NMOS tube M1And M2Phase inverter is formed, is inputted
Enable signal OE's is anti-phase；NMOS tube M3、M4、M5、M6Nor gate is formed, the input of this nor gate is the anti-phase of OE and input letter
Number I, the output of nor gate is as PMOS M12Grid control signal；By NMOS tube M7、M8、M9、M10The NAND gate of composition, makes
Energy signal OE and input signal I is input to by NMOS tube M7、M8、M9、M10In the NAND gate of composition, the output conduct of NAND gate
PMOS M11Grid control signal；PMOS M11And M12Output of the common drain as whole triple gate；Connect at input I
High level, clock being connect at Enable Pin OE, and inputting signal to be sampled by output end PMOS, week can be achieved under OE control
The sampling of phase property；The effect that whole triple gate is realized is, when OE is low level, exports floating；When OE is high level, output follows
Input I.Here connection and operation principle of the triple gate as sample circuit are as follows, and input I meets high voltage VDD, so middle to believe
Number line Mid（It is red line in figure）It is low level always, 3 NMOS tube M4、M7、M12It is all off, NMOS tube M10All the time turn on；
The Enable Pin OE incoming clocks of triple gate, clock are added in PMOS M after reversely11Grid, input signal vin to be sampled and lead to
Cross PMOS M11Source class periodically sampled and kept under OE control.According to sampling hold circuit driving force
It is required that using several Fig. 1 structure composition sampling arrays, sampling array is followed by some decoupling capacitances and makees holding capacitor.
In the present invention, differential signal is to first pass through DDLP arrays（202）Corresponding delayed data is converted to be compared again
's.DDLP design is, for a pair of differential reference voltage vrefp, vrefn specified, to design two time delay chains：Delay
Chain A and time delay chain B so that input vip, vin are respectively corresponding reference voltage vrefp, during vrefn, in the output of time delay chain
Edge is risen to reach simultaneously.So, when time delay chain A input is more than vrefp（Now time delay chain B input is less than vrefn）, time delay chain
A delay is less than time delay chain B, and the rising edge of output is reached earlier compared with time delay chain B, and two output signals are locked by respective latch
Deposit, obtained comparative result is " 1 ", and vice versa.For all reference voltages to being all designed using this thinking, i.e.
Flash ADC to N positions is, it is necessary to design（2N-1）Individual DDLP.But due to being that difference is realized, maximum (2N-1-1)
Individual reference voltage pair and (the 2 of minimumN-1- 1) each reference voltage is to being symmetrical, so, as long as emulation draws the 2 of maximumN-1It is individual
Reference voltage is to corresponding DDLP, and remaining (2N-1- 1) individual DDLP, corresponding input signal need to only be exchanged.
In the present invention, the delay of time delay chain is made up of two parts, as shown in Figure 2.Each time delay chain is first by several bases
This delay unit is in series, to determine the scope of its delay.Basic delay unit is sequentially connected by NAND gate and NOT gate to be formed,
As shown in Fig. 2 tops, the NMOS tube N that is grounded in NAND gate2With one of PMOS P2Grid all connect input control signal
In, and remaining NMOS tube N1With PMOS P1Grid meets clock Clock.Input control signal In is maintained at larger level, so that
PMOS P2Turn off and NMOS tube N always2Constantly on, such Clock to output delay is by NMOS tube N2Grid voltage,
Namely In is controlled.If In increases, NMOS tube N is crossed2Electric current also increase, Clock upset is also rapider at output.It is on the contrary
It is as the same.NOT gate after NAND gate is to ensure output with inputting same phase.During several such elementary cell series connection, Mei Geji
This units shared inputs control signal In, and inputs the output that Clock is previous elementary cell.So each unit delay
Superposition is the delay of whole time delay chain.Decoupling capacitance is connect behind time delay chain, it is possible to achieve fine setting delay, so that DDLP is accurate
Meet design requirement, the comparison and latch of certain precision can be realized.
The present invention uses tri-state gate cell and decoupling capacitance structure sampling hold circuit；Differential input signal passes through respectively
The differential delay chain of several accurate simulations is to obtaining different delays, then latched device compares two delay sizes, complete with
The comparison of corresponding differential reference voltage pair, obtains corresponding thermometer-code.The delay of time delay chain is mainly determined by NAND gate/non-door chain
It is fixed, and be finely adjusted by decoupling capacitance, to meet to be preset in the requirement of the differential reference voltage of differential delay chain centering.It is right
Flash ADC in N positions, according to each pair differential reference voltage, emulation obtains corresponding differential delay chain pair, so
Differential delay chain is to number（2N-1）.This digital N positions Flash ADC built is without inputting with reference to electricity
Pressure, its reference voltage are built in（2N-1）Individual differential delay chain centering, preferable analog-to-digital conversion can be realized at the higher speeds
Performance, area, power consumption are saved, while be greatly reduced design complexities.
Brief description of the drawings
Fig. 1 is the connected mode for the triple gate for realizing sampling hold circuit.
Fig. 2 is DDLP implementation.
Fig. 3 is the implementation of conventional Flash type analog-to-digital converter.
Fig. 4 illustrates for general structure of the present invention.
Embodiment
A kind of Flash ADC of full digital starting to being proposed in the present invention is described further below.
The Flash ADC of full digital starting proposed by the present invention, its feature have three, are respectively：By tri-state
The sampling hold circuit that door/decoupling capacitance array is formed（201）, by DDLP arrays form without reference voltage input comparison
Device structure（202）, it is delayed by NAND gate/NOT gate coarse adjustment, the time delay chain implementation of decoupling capacitance fine setting delay（Fig. 2）.
The waste of power consumption and area caused by solve traditional analog or modulus mixed analog to digital converter, and improve automation
Design efficiency, the present invention propose a kind of Flash ADC of full digital starting.The flicker pattern of the full digital starting
Number converter is compared with conventional Flash type analog-to-digital converter, it is characterised in that all circuit modules are all used in standard cell lib
Digital units are realized.The sampling hold circuit realized firstly, for traditional analog, the substitute is triple gate here.
Fig. 1 is the tri-state gate circuit in standard cell lib.M1And M2Phase inverter is formed, obtains inputting the anti-of enable signal OE
Phase.M3、M4、M5、M6Nor gate is formed, the input of this nor gate is OE anti-phase and input signal I.The output conduct of nor gate
M12Grid control signal.OE and input signal I is input to by M simultaneously7、M8、M9、M10In the NAND gate of composition, NAND gate
Output is used as M11Grid control signal.M11And M12Output of the common drain as whole triple gate.Whole triple gate is realized
Effect be, when OE is low level, export floating；When OE is high level, output follows input I.Here triple gate is used as sampling
The connection and operation principle on point road are as follows, and input I meets high voltage VDD, such M signal line Mid（It is red line in figure）Always
For low level, 3 NMOS tube M4、M7、M12It is all off, NMOS tube M10All the time turn on；The Enable Pin OE incoming clocks of triple gate,
Clock is added in PMOS M after reversely11Grid, input signal to be sampled and pass through PMOS M11It is all under OE control
The sampling and holding of phase property.According to the requirement to sampling hold circuit driving force, it is necessary to be adopted using several Fig. 1 structure compositions
Sample array, sampling array are followed by some decoupling capacitances and make holding capacitor.Secondly, comparator here uses several DDLP
Realize.Each corresponding differential reference voltage pair of DDLP, comprising two time delay chains, the design of two time delay chains needs what is met
Condition is that when input signal is respectively corresponding reference voltage pair, the output rising edge of two time delay chains reaches simultaneously.So, after
The delay that continuous circuit need to only compare the output of DDLP two can successively obtain input differential signal and corresponding reference voltage indirectly
Comparative result, obtain corresponding thermometer-code.DDLP delay chain structures such as Fig. 2.The determination of time delay chain delay uses coarse adjustment+fine setting
Two steps, the basic delay unit that the former is made up of several NAND gate/NOT gates are formed, and the latter is completed by decoupling capacitance.
Basic delay unit for middle NAND gate connection as shown in Fig. 2 tops, the NMOS tube N of ground connection2With one of PMOS P2Grid
Pole, which all connects, inputs control signal In, and remaining tubing N1And P1Grid meets clock Clock.Input control signal In is maintained at larger
Level so that P2Turn off and N always2Constantly on, such Clock to output delay is by N2Grid voltage, that is, In
Control.If In increases, N is crossed2Electric current also increase, Clock upset is also rapider at output.Vice versa.After NAND gate
It is to ensure output with inputting same phase to connect NOT gate.During several such elementary cell series connection, each elementary cell shares defeated
Enter control signal In, and input the output that Clock is previous elementary cell.The superposition of so each unit delay is realized whole
The coarse delay of time delay chain.The reference voltage of this DDLP comparative structures is preset and is built in two time delay chains, without outside
Input reference voltage.
The DDLP time delay chains that the present invention uses can also use multi input using two input nand gates in java standard library
NAND gate or high threshold voltage（HVT）/ low threshold voltage（LVT）Corresponding module in storehouse realizes time delay chain.
The control that control signal is delayed to time delay chain is inputted in the present invention makes negative correlation, can also use positively related control
Thinking processed, as long as keeping delay and the monotonic of input signal.
The present invention use the rising edge of clock to be delayed as comparing foundation, can also use trailing edge as time-delay conversion with
The foundation compared.
Claims (2)
1. a kind of Flash ADC of full digital starting, it is characterised in that structure includes：
The differential signal sampling being made up of two groups of parallel connection triple gates and decoupling capacitance keeps array（201）；By NAND gate/NOT gate
Have with what decoupling capacitance was formed using built-in reference voltage（2N-1）Individual differential delay chain is to DDLP arrays（202）；With
And latch arrays；Wherein：
Differential signal keeps array, corresponding a pair of the differential reference voltages of each DDLP, difference letter by two identical samplings
Corresponding DDLP number is controlled to produce different delayed time during holding, the delay of time delay chain is determined by several NAND gates and NOT gate, and
Realize and finely tune by decoupling capacitance；Compare again by latch, obtain the delay size of DDLP two output rising edges, from
And obtain the digital comparison output of thermometer-code；
Described differential signal sampling keeps array（201）Mainly realized using triple gate and decoupling capacitance；Tri-state gate circuit
By 12 metal-oxide-semiconductor M1~M12Circuit connection composition；Wherein, metal-oxide-semiconductor M1And M2Phase inverter is formed, obtains inputting enable signal OE's
It is anti-phase；Metal-oxide-semiconductor M3、M4、M5、M6Form nor gate, this nor gate input for OE anti-phase and input signal I, nor gate it is defeated
Go out as PMOS M12Grid control signal；By metal-oxide-semiconductor M7、M8、M9、M10NAND gate is formed, enable signal OE and input are believed
Number I is input to by metal-oxide-semiconductor M7、M8、M9、M10In the NAND gate of composition, the output of NAND gate is as PMOS M11Grid control
Signal；Metal-oxide-semiconductor M11And M12Output of the common drain as whole triple gate；High level is connect at input I, is connect at Enable Pin OE
Clock, and signal to be sampled is inputted by output end PMOS, periodically sampling can be achieved under OE control；By several
Tri-state gate circuit forms sampling array, and sampling array is followed by some decoupling capacitances and makees holding capacitor.
2. the Flash ADC of full digital starting according to claim 1, it is characterised in that in described DDLP,
For a pair of differential reference voltage vrefp, vrefn specified, two time delay chains are designed with：Time delay chain A and time delay chain B so that
Input vip, vin are respectively corresponding differential reference voltage vrefp, and during vrefn, the output rising edge of time delay chain reaches simultaneously；
So, when time delay chain A input is more than vrefp, time delay chain A delay is less than time delay chain B, and the rising edge of output is compared with time delay chain
B is reached earlier, and two output signals are latched by respective latch, and obtained comparative result is " 1 ", and vice versa；For all
Reference voltage to being all designed using this thinking, i.e. to the Flash ADC of N positions, design（2N-1）Individual DDLP；
Wherein, the delay of time delay chain is made up of two parts；Each time delay chain is in series by several basic delay units first,
To determine the scope of its delay；Basic delay unit is sequentially connected the NMOS for forming, being grounded in NAND gate by NAND gate and NOT gate
Pipe N2With one of PMOS P2Grid all meet input control signal In, and NMOS tube N1With PMOS P1Grid connects clock
Clock；Input control signal In is maintained at larger level, so that PMOS P2Turn off and NMOS tube N always2It is constantly on, this
Sample Clock is to the delay exported by NMOS tube N2Grid voltage, that is, In control；Several above-mentioned basic delay unit strings
During connection, each basic delay unit shares input control signal In, and it is the defeated of previous basic delay unit to input Clock
Go out；The superposition of so each basic delay unit delay is the delay of whole time delay chain；Decoupling capacitance is connect behind time delay chain,
To realize fine setting delay.
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| CN106027055B (en) * | 2016-05-16 | 2019-05-07 | 中国科学技术大学先进技术研究院 | A kind of low-power consumption two-step Flash ADC |
| CN112542954B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Adaptive soft drive control circuit suitable for DCM |
| CN112737339B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit |
| CN112564511B (en) * | 2020-12-16 | 2022-06-24 | 南京微盟电子有限公司 | Self-adaptive soft drive control circuit suitable for CCM |
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| An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system;Chen Huabin等;《Journal of Semiconductors》;20141130;第35卷(第11期);全文 * |
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