CN105162469A - Synchronous latch register - Google Patents
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- CN105162469A CN105162469A CN201510131780.8A CN201510131780A CN105162469A CN 105162469 A CN105162469 A CN 105162469A CN 201510131780 A CN201510131780 A CN 201510131780A CN 105162469 A CN105162469 A CN 105162469A
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Abstract
The invention brings forward a synchronous latch register. The synchronous latch register comprises a first level and a second level. Input signals of the first level are first differential signals. The first level is used for conducting phase reversal on the first differential signals, so reversed-phase second differential signals art obtained. The second level is connected to the first level, and is used for conducting phase reversal on the second differential signals and obtaining differential output signals. The advantages are that the synchronous latch register can work quickly, is simple in circuit structure, and is easy to realize.
Description
Technical field
The present invention relates to D/A converting circuit technical field, particularly relate to a kind of synchrolock storage.
Background technology
Along with the development of signal processing technology and the communication technology, the interfacing between digital signal and analog signal becomes the bottleneck of restriction digital-to-analogue hybrid system.In order to satisfied, high-precision data transaction requirement, digital to analog converter and analog to digital converter need to reach speed high as far as possible and precision.In modern number weighted-voltage D/A converter, current mode digital-to-analog converter can Direct driver resistive load owing to having, and fireballing advantage, becomes the first-selected structure of numerous engineers.
Common current mode digital-to-analog converter structure as shown in Figure 1, mainly comprises following components: supplied with digital signal decoding and buffer module, current supply switch array.Wherein, decoding buffer module is used for the digital signal of input to carry out decoding and reprocessing, realizes the synchronous and level conversion of control signal etc. by synchrolock storage, makes the signal of output can directly as the control signal of current supply switch array breaker in middle.Current supply switch array comprises multiple current supply switch unit, and each current supply switch unit comprises current source and switch.The electric current that current source exports is sent to positive output end or the negative output terminal of digital to analog converter by switch under the effect of control signal.Any one output in the positive output end of digital to analog converter and negative output terminal as the output of digital to analog converter, also can use the output of difference as digital to analog converter of these two outputs.
Improve constantly along with to the requirement of processing speed, digital to analog converter dynamic characteristic at high frequencies becomes the bottleneck limiting its application.During high frequency, the dynamic characteristic of current mode digital-to-analog converter worsens and mainly contains following three reasons: (1) switch controlling signal can not strict sequential order synchronous.(2) current source transistor drain voltage fluctuation.(3) control signal is coupled to output by the parasitic capacitance of switching tube, produces the distortion relevant to control signal.In order to address these problems, need the current supply switch of logarithmic mode transducer to carry out strict timing synchronization and controlling, to reduce harmonic distortion, this just needs to design suitable synchrolock storage.Synchrolock storage can control the timing synchronization of each current source branch switch, and reducing the timing skew of control signal, is the important component part of current mode digital-to-analog converter.
Traditional synchrolock latch circuit as shown in Figure 2.The difference output (VOUTP and VOUTN in accompanying drawing 2) of latch is for directly controlling the differential switch in current branch.Latch has two basic functions at this: one is carry out synchronously to reduce the Control timing sequence deviation of current switch as far as possible to control signal; Two is crosspoint level of adjustment difference dividing control signal VOUTP and VOUTN, the differential switch of electric current is made to equal to the electric current sum in handoff procedure the electric current that tail current source provides as far as possible, guarantee that two switching tubes can not turn off simultaneously, to reduce the fluctuation of current source transistor drain voltage, thus reduce the burr in switching over process.The people such as Bosch give the latch structure of improvement, as shown in Figure 3.This latch is another PMOS in parallel in the PMOS on top, charging and discharging can be carried out simultaneously, decrease the time delay of latch, accelerate speed.In addition, add one group of the first inverter connected, improve isolation and the stability of synchrolock storage, decrease the impact of input burr.This synchrolock storage can work under 1GHz sample frequency.
But along with the lifting of digital to analog converter operating rate, the operating rate of synchrolock storage may become the limiting factor of whole digital to analog converter performance, therefore, while adopting suitable latch structure, the level switch speed improving synchrolock storage difference control signal further to also be managed.
Summary of the invention
The present invention is intended to solve one of technical problem in correlation technique at least to a certain extent.For this reason, the object of the invention is to propose that a kind of speed is fast, structure simple and be easy to the synchrolock storage that realizes.
To achieve these goals, the synchrolock storage of the embodiment of the present invention, comprises the first order and the second level.The input signal of the described first order is the first differential signal, and the described first order is used for anti-phase for described first differential signal, to obtain the second anti-phase differential signal.The described second level is connected with the described first order, for by anti-phase for described second differential signal, to obtain differential output signal.
According to the synchrolock storage of the embodiment of the present invention, obviously improve the operating rate of synchrolock storage when without the need to significantly improving circuit complexity, circuit structure simply and easily realize.
In some instances, described synchrolock storage also comprises, the third level, and the described third level is connected with the described second level, for isolating described differential output signal and amplifying, and regulates the overlapping level of output of described synchrolock storage.
In some instances, the described first order comprises 8 metal-oxide-semiconductors, and the input anode (VINP) of described first differential signal is connected with the grid of the first metal-oxide-semiconductor (M1) with the 6th metal-oxide-semiconductor (M6); The input negative terminal (VINN) of described first differential signal is connected with the grid of the 3rd metal-oxide-semiconductor (M3) with the 8th metal-oxide-semiconductor (M8); Clock signal (CLK) is connected with the grid of the 5th metal-oxide-semiconductor (M5) with the 7th metal-oxide-semiconductor (M7); Clock signal after negate
be connected with the grid of the second metal-oxide-semiconductor (M2) with the 4th metal-oxide-semiconductor (M4); Described first metal-oxide-semiconductor (M1) is connected with power supply (VCC) with the source electrode of described 3rd metal-oxide-semiconductor M3, the drain electrode of described first metal-oxide-semiconductor (M1) is connected with the source electrode of described second metal-oxide-semiconductor M2, and the drain electrode of described 3rd metal-oxide-semiconductor (M3) is connected with the source electrode of described 4th metal-oxide-semiconductor (M4); The source electrode of described 6th metal-oxide-semiconductor (M6) and described 8th metal-oxide-semiconductor (M8) be connected to (VSS), the drain electrode of described 6th metal-oxide-semiconductor (M6) is connected with the source electrode of described 5th metal-oxide-semiconductor (M5); The drain electrode of described 8th metal-oxide-semiconductor (M8) is connected with the source electrode of described 7th metal-oxide-semiconductor (M7), described second metal-oxide-semiconductor (M2) is connected with first output (X1) of the described first order with the described drain electrode of the 5th metal-oxide-semiconductor (M5), and described 4th metal-oxide-semiconductor (M4) is connected with second output (X2) of the described first order with the described drain electrode of the 7th metal-oxide-semiconductor (M7).
In some instances, the described second level comprises: end to end first inverter (D1) and the second inverter (D2), the input of described first inverter (D1) is connected with described second output (X2), the output of described first inverter (D1) is connected with described first output (X1), the input of described second inverter (D2) is connected with described first output (X1), and the output of described second inverter (D2) is connected with described second output (X2).
In some instances, the described third level comprises: 6 metal-oxide-semiconductors, 9th metal-oxide-semiconductor (M9) is connected with described first output (X1) with the grid of the 13 metal-oxide-semiconductor (M13), 12 metal-oxide-semiconductor (M12) is connected with described second output (X2) with the grid of the 14 metal-oxide-semiconductor (M14), described 9th metal-oxide-semiconductor (M9), tenth metal-oxide-semiconductor (M10), the source electrode of the 11 metal-oxide-semiconductor (M11) and the 12 metal-oxide-semiconductor (M12) receives described power supply (VCC), the source electrode of described 13 metal-oxide-semiconductor (M13) and described 14 metal-oxide-semiconductor (M14) is connected to describedly (VSS), described 9th metal-oxide-semiconductor (M9), the drain electrode of the tenth metal-oxide-semiconductor (M10) and the 13 metal-oxide-semiconductor (M13) is connected with the 3rd output (VOUTP) of the described third level with the grid of described 11 metal-oxide-semiconductor (M11), described 11 metal-oxide-semiconductor (M11), the drain electrode of the 12 metal-oxide-semiconductor (M12) and the 14 metal-oxide-semiconductor (M14) is connected with the 4th output (VOUTN) of the described third level with the grid of described tenth metal-oxide-semiconductor (M10).
The aspect that the present invention adds and advantage will part provide in the following description, and part will become obvious from the following description, or be recognized by practice of the present invention.
Accompanying drawing explanation
Fig. 1 is current mode digital-to-analog converter structural representation common in background technology;
Fig. 2 is synchrolock latch circuit structural representation traditional in background technology;
Fig. 3 is the synchrolock storage structural representation that in background technology, the people such as Bosch improves;
Fig. 4 is the structured flowchart of synchrolock storage according to an embodiment of the invention;
Fig. 5 is the synchrolock storage structural representation of one embodiment of the invention;
Fig. 6 is each several part signal waveform schematic diagram that the synchrolock storage of one embodiment of the invention carries out emulating;
Fig. 7 is that the latch that the people such as Bosch propose contrasts schematic diagram with the synchronous Latch output signal simulation waveform of the embodiment of the present invention.
Embodiment
In describing the invention, it will be appreciated that, term " " center ", " longitudinal direction ", " transverse direction ", " length ", " width ", " thickness ", " on ", D score, " front ", " afterwards ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward ", " clockwise ", " counterclockwise ", " axis ", " radial direction ", orientation or the position relationship of the instruction such as " circumference " are based on orientation shown in the drawings or position relationship, only the present invention for convenience of description and simplified characterization, instead of indicate or imply that the device of indication or element must have specific orientation, with specific azimuth configuration and operation, therefore limitation of the present invention can not be interpreted as.
In addition, term " first ", " second " only for describing object, and can not be interpreted as instruction or hint relative importance or imply the quantity indicating indicated technical characteristic.Thus, be limited with " first ", the feature of " second " can express or impliedly comprise at least one this feature.In describing the invention, the implication of " multiple " is at least two, such as two, three etc., unless otherwise expressly limited specifically.
In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " being connected ", " connection ", " fixing " should be interpreted broadly, and such as, can be fixedly connected with, also can be removably connect, or integral; Can be mechanical connection, also can be electrical connection; Can be directly be connected, also indirectly can be connected by intermediary, can be the connection of two element internals or the interaction relationship of two elements, unless otherwise clear and definite restriction.For the ordinary skill in the art, above-mentioned term concrete meaning in the present invention can be understood as the case may be.
In the present invention, unless otherwise clearly defined and limited, fisrt feature second feature " on " or D score can be that the first and second features directly contact, or the first and second features are by intermediary indirect contact.And, fisrt feature second feature " on ", " top " and " above " but fisrt feature directly over second feature or oblique upper, or only represent that fisrt feature level height is higher than second feature.Fisrt feature second feature " under ", " below " and " below " can be fisrt feature immediately below second feature or tiltedly below, or only represent that fisrt feature level height is less than second feature.
Be described below in detail embodiments of the invention, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has element that is identical or similar functions from start to finish.Be exemplary below by the embodiment be described with reference to the drawings, be intended to for explaining the present invention, and can not limitation of the present invention be interpreted as.
See Fig. 4, the synchrolock storage 10 of the embodiment of the present invention, comprising: the first order 100 and the second level 200.
The input signal of the first order 100 is the first differential signal, the first order 100 for by anti-phase for the first differential signal, to obtain the second anti-phase differential signal.The second level 200 is connected with the first order 100, for by anti-phase for the second differential signal, to obtain differential output signal.
Further, the synchrolock storage 10 of the embodiment of the present invention also comprises: the third level 300.The third level 300 is connected with the second level 200, for isolating differential output signal and amplifying, and regulates the overlapping level of the output of synchrolock storage 10.
Composition graphs 5, introduces the synchrolock storage 10 of the embodiment of the present invention in detail.
The first order 100 comprises 8 field-effect transistor (metaloxidsemiconductor, MOS) pipes.The input signal of the first order 100 is a pair the first anti-phase differential signal VINP and VINN.Namely, when VINP is high level, VINN is low level, and vice versa.
The input anode (VINP) of the first differential signal is connected with the grid of the first metal-oxide-semiconductor (M1) with the 6th metal-oxide-semiconductor (M6).The input negative terminal (VINN) of the first differential signal is connected with the grid of the 3rd metal-oxide-semiconductor (M3) with the 8th metal-oxide-semiconductor (M8).Clock signal (CLK) is connected with the grid of the 5th metal-oxide-semiconductor (M5) with the 7th metal-oxide-semiconductor (M7).Clock signal after negate
be connected with the grid of the second metal-oxide-semiconductor (M2) with the 4th metal-oxide-semiconductor (M4).First metal-oxide-semiconductor (M1) is connected with power supply (VCC) with the source electrode of the 3rd metal-oxide-semiconductor M3, the drain electrode of the first metal-oxide-semiconductor (M1) is connected with the source electrode of the second metal-oxide-semiconductor M2, and the drain electrode of the 3rd metal-oxide-semiconductor (M3) is connected with the source electrode of the 4th metal-oxide-semiconductor (M4).The source electrode of the 6th metal-oxide-semiconductor (M6) and the 8th metal-oxide-semiconductor (M8) be connected to (VSS), the drain electrode of the 6th metal-oxide-semiconductor (M6) is connected with the source electrode of the 5th metal-oxide-semiconductor (M5).The drain electrode of the 8th metal-oxide-semiconductor (M8) is connected with the source electrode of the 7th metal-oxide-semiconductor (M7), second metal-oxide-semiconductor (M2) is connected with first output (X1) of the first order with the drain electrode of the 5th metal-oxide-semiconductor (M5), and the 4th metal-oxide-semiconductor (M4) is connected with second output (X2) of the first order with the drain electrode of the 7th metal-oxide-semiconductor (M7).
The second level 200 comprises: end to end first inverter (D1) and the second inverter (D2).The input of the first inverter (D1) is connected with the second output (X2), and the output of the first inverter (D1) is connected with the first output (X1).The input of the second inverter (D2) is connected with the first output (X1), and the output of the second inverter (D2) is connected with the second output (X2).X1 and X2 is as a pair output of the second level 200.D1 and D2 achieves the conversion of synchrolock storage 10 low and high level, level maintains and isolation, decreases charge leakage and the burr impact of input.
The third level 300 comprises: 6 metal-oxide-semiconductors.9th metal-oxide-semiconductor (M9) is connected with the first output (X1) with the grid of the 13 metal-oxide-semiconductor (M13), and the 12 metal-oxide-semiconductor (M12) is connected with the second output (X2) with the grid of the 14 metal-oxide-semiconductor (M14).9th metal-oxide-semiconductor (M9), tenth metal-oxide-semiconductor (M10), the source electrode of the 11 metal-oxide-semiconductor (M11) and the 12 metal-oxide-semiconductor (M12) receives power supply (VCC), the source electrode of the 13 metal-oxide-semiconductor (M13) and the 14 metal-oxide-semiconductor (M14) be connected to (VSS), 9th metal-oxide-semiconductor (M9), tenth metal-oxide-semiconductor (M10) and the drain electrode of the 13 metal-oxide-semiconductor (M13) are connected with the 3rd output (VOUTP) of the third level 300 with the grid of the 11 metal-oxide-semiconductor (M11), 11 metal-oxide-semiconductor (M11), the drain electrode of the 12 metal-oxide-semiconductor (M12) and the 14 metal-oxide-semiconductor (M14) is connected with the 4th output (VOUTN) of the third level with the grid of the tenth metal-oxide-semiconductor (M10).VOUTP and VOUTN, as a pair difference output of the third level 300, is sent to each current supply switch unit of current mode analog to digital converter, controls corresponding current source and flows to anode or negative terminal.
In an example of the present invention, the third level 300 has continued to use traditional synchronous latch structure, the overlapping level of output regulating synchrolock storage 10 is mainly used in example of the present invention, ensure that current supply switch pipe can not turn off simultaneously in the current mode digital-to-analog converter of application, to reduce the fluctuation of current source transistor drain voltage, thus reduce the burr in switching over process.
Like this, the first order 100 adds metal-oxide-semiconductor M1 ~ M4 relative to conventional latch, and M1 ~ M4 forms the inverter structure of a pair clock control.When clock signal clk is high level, the equal conducting of each metal-oxide-semiconductor that CLK controls, now the level of X1 and X2 becomes rapidly the level contrary with VINP and VINN, this makes the level conversion time of these two nodes (change-over time especially from low to high) greatly be reduced, thus the switch speed of synchrolock storage 10 output level can be significantly improved.
Output VOUTP with VOUTN of synchrolock storage 10 then becomes rapidly the level identical with VINP with VINN, and realizes the maintenance of level and the isolation of signal by two of the second level 200 end to end inverters.When clock signal clk is low level, CLK control each metal-oxide-semiconductor all not conducting, now synchrolock storage 10 output VOUTP and VOUTN keep before state constant.Like this, it is consistent with input that this synchrolock storage 10 achieves output when clock signal is high level, exports the state before keeping, thus achieve the function of synchrolock storage 10 when clock signal clk is low level.
By emulating the synchrolock storage 10 of the embodiment of the present invention, its simulation result as shown in Figure 6.The square wave of clock signal clk to be frequency be 2GHz, the rise/fall time is 20ps.The square wave of input signal VINP and VINN to be frequency be 1GHz, the rise/fall time is 50ps.Two-way input signal is anti-phase differential signal.By calculating the rise/fall time of output signal VOUTP and VOUTN, the level switch speed of synchrolock storage 10 can be analyzed.The latch proposed the people such as Bosch respectively and synchrolock storage 10 of the present invention emulate, and contrast output signal, for VOUTN, simulation result as shown in Figure 7.Can find out, synchrolock storage 10 output level switch speed of the present invention is faster, and waveform rise/fall is along more precipitous.The waveform rise/fall time of both actual measurements, shown in its result following table 1, visible synchrolock storage of the present invention significantly improves level conversion speed, is the desirable synchrolock storage of performance.
The latch that the people such as table 1Bosch propose and synchronous Latch output signal velocity contrast result of the present invention
| Rise time/ps | Fall time/ps | |
| The synchrolock storage of Fig. 3 | 45.52 | 91.36 |
| The synchrolock storage of the embodiment of the present invention | 35.43 | 62.27 |
According to the synchrolock storage of the embodiment of the present invention, the first order adds four metal-oxide-semiconductors relative to common synchrolock storage, the inverter structure of these four formations clock control, make the operating rate obviously improving synchrolock storage when without the need to significantly improving circuit complexity, the second level adopts two end to end inverter structures, achieves the conversion of synchrolock storage low and high level, level maintenance and isolation.The synchrolock storage of the embodiment of the present invention, circuit structure simply and easily realize.
In the description of this specification, specific features, structure, material or feature that the description of reference term " embodiment ", " some embodiments ", " example ", " concrete example " or " some examples " etc. means to describe in conjunction with this embodiment or example are contained at least one embodiment of the present invention or example.In this manual, to the schematic representation of above-mentioned term not must for be identical embodiment or example.And the specific features of description, structure, material or feature can combine in one or more embodiment in office or example in an appropriate manner.In addition, when not conflicting, the feature of the different embodiment described in this specification or example and different embodiment or example can carry out combining and combining by those skilled in the art.
Although illustrate and describe embodiments of the invention above, be understandable that, above-described embodiment is exemplary, can not be interpreted as limitation of the present invention, and those of ordinary skill in the art can change above-described embodiment within the scope of the invention, revises, replace and modification.
Claims (5)
1. a synchrolock storage, is characterized in that, comprising:
The first order, the input signal of the described first order is the first differential signal, and the described first order is used for anti-phase for described first differential signal, to obtain the second anti-phase differential signal;
The second level, the described second level is connected with the described first order, for by anti-phase for described second differential signal, to obtain differential output signal.
2. synchrolock storage as claimed in claim 1, it is characterized in that, described synchrolock storage also comprises:
The third level, the described third level is connected with the described second level, for isolating described differential output signal and amplifying, and regulates the overlapping level of output of described synchrolock storage.
3. synchrolock storage as claimed in claim 1, it is characterized in that, the described first order comprises 8 metal-oxide-semiconductors,
The input anode (VINP) of described first differential signal is connected with the grid of the first metal-oxide-semiconductor (M1) with the 6th metal-oxide-semiconductor (M6);
The input negative terminal (VINN) of described first differential signal is connected with the grid of the 3rd metal-oxide-semiconductor (M3) with the 8th metal-oxide-semiconductor (M8);
Clock signal (CLK) is connected with the grid of the 5th metal-oxide-semiconductor (M5) with the 7th metal-oxide-semiconductor (M7);
Clock signal after negate
be connected with the grid of the second metal-oxide-semiconductor (M2) with the 4th metal-oxide-semiconductor (M4);
Described first metal-oxide-semiconductor (M1) is connected with power supply (VCC) with the source electrode of described 3rd metal-oxide-semiconductor M3, the drain electrode of described first metal-oxide-semiconductor (M1) is connected with the source electrode of described second metal-oxide-semiconductor M2, and the drain electrode of described 3rd metal-oxide-semiconductor (M3) is connected with the source electrode of described 4th metal-oxide-semiconductor (M4);
The source electrode of described 6th metal-oxide-semiconductor (M6) and described 8th metal-oxide-semiconductor (M8) be connected to (VSS), the drain electrode of described 6th metal-oxide-semiconductor (M6) is connected with the source electrode of described 5th metal-oxide-semiconductor (M5);
The drain electrode of described 8th metal-oxide-semiconductor (M8) is connected with the source electrode of described 7th metal-oxide-semiconductor (M7), described second metal-oxide-semiconductor (M2) is connected with first output (X1) of the described first order with the described drain electrode of the 5th metal-oxide-semiconductor (M5), and described 4th metal-oxide-semiconductor (M4) is connected with second output (X2) of the described first order with the described drain electrode of the 7th metal-oxide-semiconductor (M7).
4. synchrolock storage as claimed in claim 1, it is characterized in that, the described second level comprises:
End to end first inverter (D1) and the second inverter (D2), the input of described first inverter (D1) is connected with described second output (X2), the output of described first inverter (D1) is connected with described first output (X1), the input of described second inverter (D2) is connected with described first output (X1), and the output of described second inverter (D2) is connected with described second output (X2).
5. synchrolock storage as claimed in claim 2, it is characterized in that, the described third level comprises: 6 metal-oxide-semiconductors,
9th metal-oxide-semiconductor (M9) is connected with described first output (X1) with the grid of the 13 metal-oxide-semiconductor (M13), 12 metal-oxide-semiconductor (M12) is connected with described second output (X2) with the grid of the 14 metal-oxide-semiconductor (M14), described 9th metal-oxide-semiconductor (M9), tenth metal-oxide-semiconductor (M10), the source electrode of the 11 metal-oxide-semiconductor (M11) and the 12 metal-oxide-semiconductor (M12) receives described power supply (VCC), the source electrode of described 13 metal-oxide-semiconductor (M13) and described 14 metal-oxide-semiconductor (M14) is connected to describedly (VSS), described 9th metal-oxide-semiconductor (M9), the drain electrode of the tenth metal-oxide-semiconductor (M10) and the 13 metal-oxide-semiconductor (M13) is connected with the 3rd output (VOUTP) of the described third level with the grid of described 11 metal-oxide-semiconductor (M11), described 11 metal-oxide-semiconductor (M11), the drain electrode of the 12 metal-oxide-semiconductor (M12) and the 14 metal-oxide-semiconductor (M14) is connected with the 4th output (VOUTN) of the described third level with the grid of described tenth metal-oxide-semiconductor (M10).
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687305A (en) * | 2021-01-05 | 2021-04-20 | 深圳芯邦科技股份有限公司 | Data storage circuit |
| CN116054834A (en) * | 2023-02-13 | 2023-05-02 | 集益威半导体(上海)有限公司 | Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter |
| WO2024041437A1 (en) * | 2022-08-26 | 2024-02-29 | 深圳市中兴微电子技术有限公司 | Differential latch circuit, switch driver, and digital-to-analog conversion circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050128117A1 (en) * | 2003-12-10 | 2005-06-16 | Samsung Electronics Co., Ltd. | Differential switching circuit and digital-to-analog converter |
| CN103840832A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Current rudder type digital-to-analogue conversion circuit with burr inhibiting ability |
-
2015
- 2015-03-24 CN CN201510131780.8A patent/CN105162469A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050128117A1 (en) * | 2003-12-10 | 2005-06-16 | Samsung Electronics Co., Ltd. | Differential switching circuit and digital-to-analog converter |
| CN103840832A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Current rudder type digital-to-analogue conversion circuit with burr inhibiting ability |
Non-Patent Citations (1)
| Title |
|---|
| 徐震: "DAC的校准技术及实现", 《中国优秀硕士学位论文全文数据库 信息科级辑》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112687305A (en) * | 2021-01-05 | 2021-04-20 | 深圳芯邦科技股份有限公司 | Data storage circuit |
| CN112687305B (en) * | 2021-01-05 | 2024-05-10 | 深圳芯邦科技股份有限公司 | Data storage circuit |
| WO2024041437A1 (en) * | 2022-08-26 | 2024-02-29 | 深圳市中兴微电子技术有限公司 | Differential latch circuit, switch driver, and digital-to-analog conversion circuit |
| CN116054834A (en) * | 2023-02-13 | 2023-05-02 | 集益威半导体(上海)有限公司 | Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter |
| CN116054834B (en) * | 2023-02-13 | 2023-07-04 | 集益威半导体(上海)有限公司 | Four-way or eight-way time sequence interweaved high-speed digital-to-analog converter |
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