CN106656124B - A kind of low imbalance dynamic comparer of high speed - Google Patents
A kind of low imbalance dynamic comparer of high speed Download PDFInfo
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- CN106656124B CN106656124B CN201611252308.0A CN201611252308A CN106656124B CN 106656124 B CN106656124 B CN 106656124B CN 201611252308 A CN201611252308 A CN 201611252308A CN 106656124 B CN106656124 B CN 106656124B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
Abstract
A kind of low imbalance dynamic comparer of high speed, including dynamic difference comparison circuit, comparator calibration circuit, clock control circuit, first switch, second switch, third switch, the 4th switch and the 5th switch, wherein, the clock control circuit has input end of clock, the first output terminal of clock and second clock output end；The dynamic difference comparison circuit has input end of clock, non-inverting input terminal, inverting input terminal, same-phase compensation control signal, reverse compensation control signal, in-phase output end and reversed-phase output；The comparator calibration circuit has input end of clock, resets enabled input terminal, same-phase compensation output end, reverse compensation output end, non-inverting input terminal and inverting input terminal.The low imbalance dynamic comparer of high speed of the invention can reduce the influence of comparator imbalance voltage, be very suitable for the mistuning calibration function of high-speed receiver.
Description
Technical field
The present invention relates to the low imbalance dynamics of a kind of dynamic comparer more particularly to a kind of high speed suitable for high-speed receiver
Comparator.
Background technique
With the further development of information technology, volume of transmitted data is significantly increased, and transmission speed is continuously improved, and high speed receives
The design of device, which seems, to become more and more important.The key modules that comparator is formed as high-speed receiver, speed, precision and power consumption etc.
Performance indicator suffers from very big influence to entire receiver.General high-speed comparator is all using dynamic latch comparator configuration
To meet the requirement of speed, but all there is very big offset voltage in usually this kind of dynamic comparer, seriously constrain dynamic ratio
Compared with the precision of device, application of the dynamic comparer in high-speed receiver is limited.
Mistuning calibration function suitable for high-speed receiver becomes urgent problem to be solved, it is therefore proposed a kind of low imbalance of high speed
Dynamic comparer reduces the influence of comparator imbalance voltage.
Summary of the invention
In order to solve the shortcomings of the prior art, the purpose of the present invention is to provide a kind of low imbalance Dynamic comparisons of high speed
Device can reduce the influence of comparator imbalance voltage, the mistuning calibration function suitable for high-speed receiver.
To achieve the above object, the low imbalance dynamic comparer of high speed provided by the invention, comprising: dynamic difference is more electric
Road, comparator calibration circuit, clock control circuit, first switch, second switch, third switch, the 4th switch and the 5th switch,
Wherein,
The clock control circuit has input end of clock, the first output terminal of clock and second clock output end；
The dynamic difference comparison circuit has input end of clock, non-inverting input terminal, inverting input terminal, same-phase compensation control
Input terminal, reverse compensation control signal, in-phase output end and reversed-phase output；
The comparator calibration circuit has input end of clock, resets enabled input terminal, same-phase compensation output end, reverse phase benefit
Repay output end, non-inverting input terminal and inverting input terminal；
The externally input clock signal of the clock input of the clock control circuit；
First output terminal of clock of the clock control circuit provides clock control signal to the dynamic difference ratio
Compared with the input end of clock of circuit；
The second clock output end of the clock control circuit provides clock control signal and calibrates to the comparator
The input end of clock of circuit；
The non-inverting input terminal of the dynamic difference comparison circuit is switched by the first switch, the third respectively
Receive externally input in-phase input signals for 1 and common-mode signal；
The inverting input terminal of the dynamic difference comparison circuit passes through the second switch, the 4th switch respectively
Receive externally input rp input signal and common-mode signal；
The same-phase compensation control signal, the reverse compensation control signal point of the dynamic difference comparison circuit
The same phase that the same-phase compensation output end and the reverse compensation output end for not receiving the comparator calibration circuit provide is mended
Repay control signal and reverse compensation control signal；
The in-phase output end, the reversed-phase output of the dynamic difference comparison circuit are exported respectively with mutually output letter
Number and reversed-phase output signal；
The reset of the comparator calibration circuit enables input terminal and receives externally input reset enable signal；
The non-inverting input terminal, the inverting input terminal of the comparator calibration circuit receive the dynamic difference respectively
The in-phase output end of comparison circuit and the In-phase output signal and reversed-phase output signal of reversed-phase output output；
The both ends of 5th switch are separately connected the non-inverting input terminal of the dynamic difference comparison circuit and described
Inverting input terminal.
Further, the dynamic difference comparison circuit includes: the first phase inverter being sequentially connected in series, the second phase inverter
And third phase inverter, wherein
The input end of clock of the input terminal of first phase inverter as the dynamic difference comparison circuit, and it is defeated
Outlet outputs signal to second phase inverter, and second inverter output signal gives the third phase inverter.
Further, the dynamic difference comparison circuit further include: the first transistor, second transistor, third transistor,
9th transistor, the 15th transistor and the 16th transistor, and the first multiple groups crystal being in parallel with the third transistor
Pipe group, and the second multiple groups transistor group being in parallel with the 9th transistor, wherein
The source electrode and the described 15th of the first transistor, the third transistor, the first multiple groups transistor group
The drain electrode of transistor is connected；
The second transistor, the 9th transistor, the second multiple groups transistor group source electrode and the described 16th
The drain electrode of transistor is connected；
15th transistor, the 16th transistor grid be connected, and be controlled by the third phase inverter
Output signal；
The source electrode of 15th transistor and the 16th transistor ground connection；
The drain electrode of the first transistor, the third transistor, the first multiple groups transistor group is connected at first point；
The drain electrode of the second transistor, the 9th transistor, the second multiple groups transistor group is connected to second point；
The grid of every group transistor group receives the ratio respectively in the third transistor, the first multiple groups transistor group
Same-phase compensation compared with device calibration circuit output controls signal；
The grid of every group transistor group receives the ratio respectively in 9th transistor, the second multiple groups transistor group
Reverse compensation compared with device calibration circuit output controls signal；
The first transistor, the second transistor grid respectively as described in the dynamic difference comparison circuit
Non-inverting input terminal and the inverting input terminal.
Further, in the first multiple groups transistor group and the second multiple groups transistor group transistor group group number phase
Together.
Further, the quantity of every group transistor group is 2 in the first multiple groups transistor groupN, and be incremented by,
In, N is positive integer；
The quantity of every group transistor group is 2 in the second multiple groups transistor groupN, and be incremented by, wherein N is positive whole
Number.
Further, the dynamic difference comparison circuit further include: the 17th transistor, the 18th transistor, the 19th
Transistor, the 20th transistor, the 21st transistor, the 20th two-transistor and the 23rd transistor, wherein
18th transistor, the drain electrode of the 20th transistor and the 21st transistor and described
The grid of 19 transistors and the 20th two-transistor is connected at described first point；
The grid and the 19th transistor of 18th transistor and the 21st transistor, described
The drain electrode of 20 two-transistors and the 23rd transistor, is connected to the second point；
The source electrode of the drain electrode of 17th transistor and the 18th transistor, the 19th transistor is connected
It connects；
The grid of 17th transistor, the 20th transistor and the 23rd transistor receives described the
The output signal of two phase inverters；
The source electrode of 17th transistor is grounded；
20th transistor, the 21st transistor, the 20th two-transistor and the described 23rd
The source electrode of transistor is separately connected power supply.
Further, the dynamic difference comparison circuit further include: the 24th transistor, the 25th transistor, string
The hex inverter and the 7th phase inverter for joining the 4th phase inverter connected and the 5th phase inverter and being connected in series, wherein
4th phase inverter, the 5th phase inverter tie point be connected with the drain electrode of the 25th transistor
It connects；
The hex inverter, the 7th phase inverter tie point be connected with the drain electrode of the 24th transistor
It connects；
4th phase inverter, the hex inverter input terminal be connected to the second point and described first
Point；
5th phase inverter, the 7th phase inverter output end respectively as the dynamic difference comparison circuit institute
State in-phase output end and the reversed-phase output；
24th transistor, the 25th transistor grid receive the defeated of first phase inverter respectively
Signal out；
24th transistor, the 25th transistor source electrode be grounded respectively.
The low imbalance dynamic comparer of high speed of the invention is suitable for high-speed receiver, is realized by increasing based on digital code
Comparator calibrate circuit, control dynamic difference comparison circuit input terminal, compensate dynamic difference comparator offset error, greatly
Reduce to amplitude the influence of dynamic difference comparator imbalance voltage.
Other features and advantages of the present invention will be illustrated in the following description, also, partly becomes from specification
It obtains it is clear that understand through the implementation of the invention.
Detailed description of the invention
Attached drawing is used to provide further understanding of the present invention, and constitutes part of specification, and with it is of the invention
Embodiment together, is used to explain the present invention, and is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the schematic diagram of the low imbalance dynamic comparer of high speed according to the present invention；
Fig. 2 is the schematic diagram of the clock circuit of dynamic difference comparison circuit according to the present invention；
Fig. 3 is the schematic diagram of the input circuit of dynamic difference comparison circuit according to the present invention；
Fig. 4 is the schematic diagram of the latch cicuit of dynamic difference comparison circuit according to the present invention；
Fig. 5 is the schematic diagram of the output circuit of dynamic difference comparison circuit according to the present invention.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings, it should be understood that preferred reality described herein
Apply example only for the purpose of illustrating and explaining the present invention and is not intended to limit the present invention.
Fig. 1 is the schematic diagram of the low imbalance dynamic comparer of high speed according to the present invention, below with reference to Fig. 1, to of the invention
The low imbalance dynamic comparer of high speed is described in detail.
The low imbalance dynamic comparer of high speed of the invention can reduce the influence of comparator imbalance voltage, be very suitable for height
The mistuning calibration function of fast receiver.
The low imbalance dynamic comparer of high speed of the invention, including dynamic difference comparison circuit 101, comparator calibrate circuit
102, clock control circuit 103, first switch S1, second switch S2, third switch S3, the 4th switch S4 and the 5th switch S5,
Wherein,
Clock control circuit 103 has input end of clock 31, the first output terminal of clock 32 and second clock output end 33；
Dynamic difference comparison circuit 101 has input end of clock 11, non-inverting input terminal 12, inverting input terminal 13, same mutually benefit
Repay control signal 14, reverse compensation control signal 15, in-phase output end 16 and reversed-phase output 17；
Comparator calibrate circuit 102 have input end of clock 21, reset enabled input terminal 22, same-phase compensation output end 23,
Reverse compensation output end 24, non-inverting input terminal 25 and inverting input terminal 26.
Further,
The input end of clock 31 of clock control circuit 103 receives externally input clock signal clk；
First output terminal of clock 32 of clock control circuit 103 provides clock control signal CLK_COMP and gives dynamic difference ratio
Compared with the input end of clock 11 of circuit 101；
The second clock output end 33 of clock control circuit 103 provides clock control signal CLK_CAL and calibrates to comparator
The input end of clock 21 of circuit 102.
The non-inverting input terminal 12 of dynamic difference comparison circuit 101 is received by first switch S1, third switch S3 outer respectively
The in-phase input signals for 1 VIP and common-mode signal VCM of portion's input；
The inverting input terminal 13 of dynamic difference comparison circuit 101 is received by second switch S2, the 4th switch S4 outer respectively
The rp input signal VIN and common-mode signal VCM of portion's input；
Same-phase compensation control signal 14, the reverse compensation control signal 15 of dynamic difference comparison circuit 101 connect respectively
The same-phase compensation that the same-phase compensation output end 23 and reverse compensation output end 24 for receiving comparator calibration circuit 102 provide controls signal
CALP<5:0>and reverse compensation control signal CALN<5:0>；
In-phase output end 16, the reversed-phase output 17 of dynamic difference comparison circuit 101 export In-phase output signal VOP respectively
And reversed-phase output signal VON.
The reset of comparator calibration circuit 102 enables input terminal 22 and receives externally input reset enable signal RST；
Non-inverting input terminal 25, the inverting input terminal 26 of comparator calibration circuit 102 receive dynamic difference comparison circuit respectively
The In-phase output signal VOP and reversed-phase output signal VON of 101 in-phase output end 16 and reversed-phase output 17 output.
The both ends of 5th switch S5 are separately connected the non-inverting input terminal 12 and inverting input terminal of dynamic difference comparison circuit 101
13。
The low imbalance dynamic comparer of high speed of the invention calibrates circuit 102 by comparator and compensates dynamic difference comparison circuit
The influence of comparator imbalance voltage can be effectively reduced while guaranteeing high speed in imbalance of 101 inputs to pipe, improves high
The precision of quick access receipts comparator.
Fig. 2 is the schematic diagram of the clock circuit of dynamic difference comparison circuit according to the present invention, as shown in Fig. 2, of the invention
Dynamic difference comparison circuit clock circuit include the first phase inverter INV1 being sequentially connected in series, the second phase inverter INV2 and
Third phase inverter INV3, wherein
The clock when input terminal of first phase inverter INV1 is received as the input end of clock 11 of dynamic difference comparison circuit 101
Signal CLK_COMP processed, and output end output signal CLKB1 gives the second phase inverter INV2, the second phase inverter INV2 output signal
CLKD gives third phase inverter INV3, the output end output signal CLKB of third phase inverter INV3.
Fig. 3 is the schematic diagram of the input circuit of dynamic difference comparison circuit according to the present invention, as shown in figure 3, of the invention
The input circuit of dynamic difference comparison circuit include: the first transistor M1, second transistor M2, third transistor M30, the 4th
Transistor group M31<1:0>, the 5th transistor group M32<3:0>, the 6th transistor group M33<7:0>, the 7th transistor group M34<
15:0>, the 8th transistor group M35<31:0>, the 9th transistor M40, the tenth transistor group M41<1:0>, the 11st transistor group
M42<3:0>, the tenth two-transistor group M43<7:0>, the 13rd transistor group M44<15:0>, the 14th transistor group M45<31:
0 >, the 15th transistor M5 and the 16th transistor M6, wherein
The first transistor M1, third transistor M30, the 4th transistor group M31<1:0>, the 5th transistor group M32<3:0>,
6th transistor group M33<7:0>, the source electrode of the 7th transistor group M34<15:0>and the 8th transistor group M35<31:0>and
The drain electrode of 15 transistor M5 is connected；
Second transistor M2, the 9th transistor M40, the tenth transistor group M41<1:0>, the 11st transistor group M42<3:0
>, the source of the tenth two-transistor group M43<7:0>, the 13rd transistor group M44<15:0>, the 14th transistor group M45<31:0>
The drain electrode of pole and the 16th transistor M6 are connected；
15th transistor M5, the 16th transistor M6 grid be connected, and be controlled by the defeated of third phase inverter INV3
Signal CLKB out；
The source electrode of 15th transistor M5 and the 16th transistor M6 is grounded；
The first transistor M1, third transistor M30, the 4th transistor group M31<1:0>, the 5th transistor group M32<3:0>,
The drain electrode of 6th transistor group M33<7:0>, the 7th transistor group M34<15:0>and the 8th transistor group M35<31:0>are connected to
Point W1；
Second transistor M2, the 9th transistor M40, the tenth transistor group M41<1:0>, the 11st transistor group M42<3:0
>, the leakage of the tenth two-transistor group M43<7:0>, the 13rd transistor group M44<15:0>and the 14th transistor group M45<31:0>
Pole is connected to point W2；
Third transistor M30, the 4th transistor group M31<1:0>, the 5th transistor group M32<3:0>, the 6th transistor group
The grid of M33<7:0>, the 7th transistor group M34<15:0>and the 8th transistor group M35<31:0>receive comparator calibration respectively
The same-phase compensation that circuit 102 exports controls signal CALP<5:0>；
9th transistor M40, the tenth transistor group M41<1:0>, the 11st transistor group M42<3:0>, the 12nd crystal
The grid of pipe group M43<7:0>, the 13rd transistor group M44<15:0>and the 14th transistor group M45<31:0>receive ratio respectively
The reverse compensation exported compared with device calibration circuit 102 controls signal CALN<5:0>；
The first transistor M1, second transistor M2 grid respectively as dynamic difference comparison circuit 101 homophase input
End 12 and inverting input terminal 13, receive externally input in-phase input signals for 1 VIP and rp input signal VIN；
The group number for the transistor group being in parallel with third transistor M30 is the same as the transistor being in parallel with the 9th transistor M40
The group number of group is consistent.
Certainly, the group number for the transistor group being in parallel with third transistor M30 not only shall be limited only to the extent 5 groups (by the 4th crystal
Pipe group M31<1:0>, the 5th transistor group M32<3:0>, the 6th transistor group M33<7:0>, the 7th transistor group M34<15:0>
And the 8th transistor group M35<31:0>constitute), also can according to need and be adjusted；And it is in parallel with the 9th transistor M40
Transistor group group number, also not only shall be limited only to the extent 5 groups (by the tenth transistor group M41<1:0>, the 11st transistor group M42<
3:0>, the tenth two-transistor group M43<7:0>, the 13rd transistor group M44<15:0>and the 14th transistor group M45<31:0>
Constitute), it also can according to need and be adjusted.
Wherein,
4th transistor group M31<1:0>, the 5th transistor group M32<3:0>, the 6th transistor group M33<7:0>, the 7th crystalline substance
The quantity of transistor is 2 in body pipe group M34<15:0>and the 8th transistor group M35<31:0>N, and be incremented by, it is preferable that the
Four transistor group M31<1:0>, the 5th transistor group M32<3:0>, the 6th transistor group M33<7:0>, the 7th transistor group M34<
The quantity of transistor is followed successively by 2,4,8,16,32 in 15:0>and the 8th transistor group M35<31:0>.
Tenth transistor group M41<1:0>, the 11st transistor group M42<3:0>, the tenth two-transistor group M43<7:0>,
The quantity of transistor is 2 in 13 transistor group M44<15:0>and the 14th transistor group M45<31:0>N, and be incremented by,
Preferably, the tenth transistor group M41<1:0>, the 11st transistor group M42<3:0>, the tenth two-transistor group M43<7:0>,
In 13 transistor group M44<15:0>and the 14th transistor group M45<31:0>quantity of transistor be followed successively by 2,4,8,16,
32。
Certainly, in above-mentioned transistor group transistor quantity, be not limited only to 2N, can be adjusted according to actual needs.
Fig. 4 is the schematic diagram of the latch cicuit of dynamic difference comparison circuit according to the present invention, as shown in figure 4, of the invention
The latch cicuit of dynamic difference comparison circuit include: the 17th transistor M7, the 18th transistor M8, the 19th transistor
M9, the 20th transistor M10, the 21st transistor M11, the 20th two-transistor M12 and the 23rd transistor M13,
In,
Drain electrode and the 19th crystal of 18th transistor M8, the 20th transistor M10 and the 21st transistor M11
The grid of pipe M9 and the 20th two-transistor M12 are connected to point W1；
The grid and the 19th transistor M9, the 22nd crystal of 18th transistor M8 and the 21st transistor M11
The drain electrode of pipe M12 and the 23rd transistor M13 are connected to point W2；
The drain electrode of 17th transistor M7 and the source electrode of the 18th transistor M8, the 19th transistor M9 are connected；
The grid of 17th transistor M7, the 20th transistor M10 and the 23rd transistor M13 receive the second phase inverter
The output signal CLKD of INV2；
The source electrode of 17th transistor M7 is grounded；
20th transistor M10, the 21st transistor M11, the 20th two-transistor M12 and the 23rd transistor
The source electrode of M13 is separately connected power vd D.
Fig. 5 is the schematic diagram of the output circuit of dynamic difference comparison circuit according to the present invention, as shown in figure 5, of the invention
Dynamic difference comparison circuit output circuit include: the 24th transistor M14, the 25th transistor M15, be connected in series
The 4th phase inverter INV4 and the 5th phase inverter INV5 and be connected in series hex inverter INV6 and the 7th phase inverter INV7,
Wherein,
4th phase inverter INV4, the 5th phase inverter INV5 tie point be connected with the drain electrode of the 25th transistor M15；
Hex inverter INV6, the 7th phase inverter INV7 tie point be connected with the drain electrode of the 24th transistor M14；
4th phase inverter INV4, hex inverter INV6 input terminal be connected to point W2 and point W1；
5th phase inverter INV5, the 7th phase inverter INV7 output end respectively as the same of dynamic difference comparison circuit 101
Phase output terminal 16 and reversed-phase output 17；
24th transistor M14, the 25th transistor M15 grid receive the output of the first phase inverter INV1 respectively
Signal CLKB1；
24th transistor M14, the 25th transistor M15 source electrode be grounded respectively.
Below with reference to Fig. 1 to Fig. 5, the working principle of the low imbalance dynamic comparer of high speed of the invention is discussed in detail.
The compensating control signal CALP<5:0>that outputs it of reset enable signal RST of comparator calibration circuit 102 and
CALN<5:0>is all reset to low level.When received clock control signal CLK_COMP=1 of dynamic difference comparison circuit 101
When, third switch S3, the 4th switch S4 and the 5th switch S5 closure, the input terminal (12,13) of dynamic difference comparison circuit 101 connect
It is connected to common mode electrical level VCM, due to there is the influence of imbalance, the output signal of 101 output end of dynamic difference comparison circuit (16,17)
VOP and VON, one end export high level, and the other end exports low level.
When comparator calibrates 102 received clock control signal CLK_CAL=1 of circuit, comparator is calibrated circuit 102 and is examined
The level for measuring 101 output end of dynamic difference comparison circuit (16,17) output signal VOP and VON controls the compensation control of its output
Signal CALP<5:0>processed or CALN<5:0>are gradually incremented by, thus control and 101 non-inverting input terminal 12 of dynamic difference comparison circuit
The first transistor M1 of connection and the third transistor M30 of parallel connection, the 4th transistor group M31<1:0>, the 5th transistor group M32<
3:0>, the grid of the 6th transistor group M33<7:0>, the 7th transistor group M34<15:0>, the 8th transistor group M35<31:0>,
Or the second transistor M2 that is connect with 102 inverting input terminal 13 of dynamic difference comparison circuit and the 9th transistor M40 of parallel connection, the
Ten transistor group M41<1:0>, the 11st transistor group M42<3:0>, the tenth two-transistor group M43<7:0>, the 13rd transistor
The grid of group M44<15:0>, the 14th transistor group M45<31:0>, gradually to the offset voltage of dynamic difference comparison circuit 101
It compensates.Until the value of the output signal VOP and VON of 101 output end of dynamic difference comparison circuit (16,17) are flipped,
Complete mistuning calibration function process.
The low imbalance dynamic comparer of high speed of the invention is suitable for high-speed receiver, is realized by increasing based on digital code
Comparator calibrate circuit, control dynamic difference comparison circuit input terminal, compensate dynamic difference comparator offset error, greatly
Reduce to amplitude the influence of dynamic difference comparator imbalance voltage.
Those of ordinary skill in the art will appreciate that: the foregoing is only a preferred embodiment of the present invention, and does not have to
In the limitation present invention, although the present invention is described in detail referring to the foregoing embodiments, for those skilled in the art
For, still can to foregoing embodiments record technical solution modify, or to part of technical characteristic into
Row equivalent replacement.All within the spirits and principles of the present invention, any modification, equivalent replacement, improvement and so on should all include
Within protection scope of the present invention.
Claims (3)
1. a kind of low imbalance dynamic comparer of high speed characterized by comprising dynamic difference comparison circuit, comparator calibration electricity
Road, clock control circuit, first switch, second switch, third switch, the 4th switch and the 5th switch, wherein
The clock control circuit has input end of clock, the first output terminal of clock and second clock output end；
The dynamic difference comparison circuit has input end of clock, non-inverting input terminal, inverting input terminal, same-phase compensation control input
End, reverse compensation control signal, in-phase output end and reversed-phase output；
The comparator calibration circuit has the enabled input terminal of input end of clock, reset, same-phase compensation output end, reverse compensation defeated
Outlet, non-inverting input terminal and inverting input terminal；
The externally input clock signal of the clock input of the clock control circuit；
It is more electric to the dynamic difference that first output terminal of clock of the clock control circuit provides clock control signal
The input end of clock on road；
The second clock output end of the clock control circuit provides clock control signal and calibrates circuit to the comparator
The input end of clock；
The non-inverting input terminal of the dynamic difference comparison circuit is received by the first switch, third switch respectively
Externally input in-phase input signals for 1 and common-mode signal；
The inverting input terminal of the dynamic difference comparison circuit passes through the second switch respectively, the 4th switch receives
Externally input rp input signal and common-mode signal；
The same-phase compensation control signal, the reverse compensation control signal of the dynamic difference comparison circuit connect respectively
The same-phase compensation control that the same-phase compensation output end and the reverse compensation output end for receiving the comparator calibration circuit provide
Signal and reverse compensation processed control signal；
The in-phase output end, the reversed-phase output of the dynamic difference comparison circuit export respectively In-phase output signal and
Reversed-phase output signal；
The reset of the comparator calibration circuit enables input terminal and receives externally input reset enable signal；
The non-inverting input terminal, the inverting input terminal of the comparator calibration circuit receive the dynamic difference respectively and compare
The in-phase output end of circuit and the In-phase output signal and reversed-phase output signal of reversed-phase output output；
The both ends of 5th switch are separately connected the non-inverting input terminal and the reverse phase of the dynamic difference comparison circuit
Input terminal；
The dynamic difference comparison circuit further include:
The first phase inverter, the second phase inverter and third phase inverter, the first transistor, the second transistor, being sequentially connected in series
Three transistors, the 9th transistor, the 15th transistor and the 16th transistor, and be in parallel with the third transistor first
Multiple groups transistor group, and the second multiple groups transistor group being in parallel with the 9th transistor, wherein
The input end of clock of the input terminal of first phase inverter as the dynamic difference comparison circuit, and output end
Second phase inverter is outputed signal to, second inverter output signal gives the third phase inverter；
The source electrode and the 15th crystal of the first transistor, the third transistor, the first multiple groups transistor group
The drain electrode of pipe is connected；
The second transistor, the 9th transistor, the second multiple groups transistor group source electrode and the 16th crystal
The drain electrode of pipe is connected；
15th transistor, the 16th transistor grid be connected, and be controlled by the defeated of the third phase inverter
Signal out；
The source electrode of 15th transistor and the 16th transistor ground connection；
The grid of every group transistor group receives the comparator respectively in the third transistor, the first multiple groups transistor group
The same-phase compensation for calibrating circuit output controls signal；
The grid of every group transistor group receives the comparator respectively in 9th transistor, the second multiple groups transistor group
The reverse compensation for calibrating circuit output controls signal；
The first transistor, the second transistor grid respectively as the dynamic difference comparison circuit the same phase
Input terminal and the inverting input terminal；
The dynamic difference comparison circuit further include:
17th transistor, the 18th transistor, the 19th transistor, the 20th transistor, the 21st transistor, the 20th
Two-transistor and the 23rd transistor, wherein
The drain electrode of 17th transistor and the source electrode of the 18th transistor, the 19th transistor are connected；
It is anti-that the grid of 17th transistor, the 20th transistor and the 23rd transistor receives described second
The output signal of phase device；
The source electrode of 17th transistor is grounded；
20th transistor, the 21st transistor, the 20th two-transistor and the 23rd crystal
The source electrode of pipe is separately connected power supply；
The dynamic difference comparison circuit further include:
24th transistor, the 25th transistor, the 4th phase inverter being connected in series and the 5th phase inverter and series connection
Hex inverter and the 7th phase inverter, wherein
4th phase inverter, the 5th phase inverter tie point be connected with the drain electrode of the 25th transistor；
The hex inverter, the 7th phase inverter tie point be connected with the drain electrode of the 24th transistor；
5th phase inverter, the 7th phase inverter output end respectively as the described same of the dynamic difference comparison circuit
Phase output terminal and the reversed-phase output；
24th transistor, the 25th transistor grid receive respectively first phase inverter output letter
Number；
24th transistor, the 25th transistor source electrode be grounded respectively；
It is the first transistor, the third transistor, the first multiple groups transistor group, the 18th transistor, described
The drain electrode of 20th transistor and the 21st transistor, the 19th transistor and the 20th two-transistor
Grid, the hex inverter input terminal be connected；
It is the second transistor, the 9th transistor, the second multiple groups transistor group, the 19th transistor, described
Drain electrode, the 18th transistor and the 21st transistor of 20th two-transistor and the 23rd transistor
Grid, the 4th phase inverter input terminal be connected.
2. the low imbalance dynamic comparer of high speed according to claim 1, it is characterised in that:
The group number of transistor group is identical in the first multiple groups transistor group and the second multiple groups transistor group.
3. the low imbalance dynamic comparer of high speed according to claim 1, it is characterised in that:
The quantity of every group transistor group is 2 in the first multiple groups transistor groupN, and be incremented by, wherein N is positive integer；
The quantity of every group transistor group is 2 in the second multiple groups transistor groupN, and be incremented by, wherein N is positive integer.
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| CN107241098B (en) * | 2017-05-24 | 2020-10-16 | 东南大学 | Offset calibration circuit of comparator in asynchronous successive approximation type analog-to-digital converter |
| CN107800413B (en) * | 2017-11-20 | 2020-04-21 | 北京华大九天软件有限公司 | Low-offset high-speed dynamic comparator |
| CN111130512B (en) * | 2019-12-11 | 2023-08-01 | 芯创智创新设计服务中心(宁波)有限公司 | Quick comparison circuit and electronic equipment |
| CN111613171B (en) * | 2020-06-23 | 2023-11-21 | 京东方科技集团股份有限公司 | Signal selection circuit and display device |
| CN112583387A (en) * | 2020-12-14 | 2021-03-30 | 重庆百瑞互联电子技术有限公司 | Strong arm latch voltage comparator based on parallel path |
| CN114371753A (en) * | 2021-01-08 | 2022-04-19 | 中国科学院微电子研究所 | Comparator circuit with dynamic offset calibration circuit and electronic equipment |
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| US8836375B2 (en) * | 2012-09-06 | 2014-09-16 | Lsi Corporation | Continuously self-calibrated latched comparator |
| CN103036538B (en) * | 2012-12-06 | 2016-05-18 | 国民技术股份有限公司 | The circuit of calibration comparator offset voltage and method thereof |
| CN103178813B (en) * | 2013-02-26 | 2015-07-15 | 东南大学 | Low-offset full-motion comparator |
| US8786483B1 (en) * | 2013-03-14 | 2014-07-22 | Analog Devices Technology | Use of a DLL to optimize an ADC performance |
| CN104300983B (en) * | 2013-07-17 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Dynamic comparer for flow-line modulus converter |
| CN204967797U (en) * | 2015-08-28 | 2016-01-13 | 西安启微迭仪半导体科技有限公司 | Switch capacitance comparator circuit among adc |
| CN105720955B (en) * | 2016-01-20 | 2018-06-08 | 桂林电子科技大学 | A kind of dynamic comparer with offset compensation |
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