CN204967797U - Switch capacitance comparator circuit among adc - Google Patents

Abstract

The utility model discloses a switch capacitance comparator circuit among adc, its characterized in that: including the switched -capacitor circuit, in advance amplifier circuit, latch output circuit, the imbalance calibration circuit, switching capacity circuit connection amplifier circuit's input in advance, it connects to latch output circuit amplifier circuit's output in advance, the way is connected the imbalance calibration circuit with enlargeing even in advance. The utility model discloses this calibration technique can not introduce any parasitic wparameter on the signal node of comparator, can improve the response speed of comparator, is suitable for high -speed ADC's application scenario.

Description

A kind of analog to digital converter breaker in middle capacitance comparator circuit

Technical field

The utility model relates to semiconductor integrated circuit technical field, particularly a kind of analog to digital converter breaker in middle capacitance comparator circuit.

Background technology

Comparator is one of nucleus module of analog-digital converter (ADC).In all kinds of ADC such as complete also type, pipeline-type, successive approximation, over-sampling type, the response speed of comparator directly determines the conversion speed of ADC, and the imbalance situation of comparator then can have impact on the characteristics such as the signal to noise ratio (SNR) of ADC, Spurious Free Dynamic Range (SFDR), nonlinearity erron.Therefore, in High Speed High Precision ADC, high performance comparator is one of design difficulty of whole ADC system all the time.

Because the ADC of the overwhelming majority is the sampling system worked under fixed frequency clock drives, therefore comparator major part wherein is also all clock-driven switching capacity comparator.Switching capacity comparator configuration the most frequently used in ADC is as shown in Fig. 1 (a), and it is primarily of switched-capacitor circuit, pre-amplification circuit Preamp, latch cicuit Latch tri-part composition, and its clocked sequential is as shown in Fig. 1 (b).? with for the high level stage, electric capacity C ₁and C ₂respectively to input signal V _iN+and V _iN-sampling, electric capacity C ₃and C ₄respectively to reference signal V _rEF-and V _rEF+sampling; ? with for the high level stage, electric capacity realizes voltage by Charge scaling and subtracts each other, and is latched by latch cicuit Latch after result being amplified by pre-amplification circuit Preamp and export.

But in integrated circuits, the offset voltage caused by device mismatch is ubiquitous phenomenon.In the comparator of Fig. 1 (a), there is this problem, in the drawings with V in pre-amplification circuit Preamp and latch cicuit Latch _oS1and V _oS2represent respectively.The reference voltage that the existence of offset voltage can be equivalent to comparator deviate from actual value, thus causes ADC to produce error code.General way is reduced the mismatch of device, but the effect of this mode is limited.Size more usually by increasing device reduces mismatch, but this mode also can increase the parasitic capacitance of circuit simultaneously, thus reduces the speed of comparator.

More efficiently thinking still adopts small size device, but offset the imbalance of comparator by the mode of calibration, common structure as shown in Figure 2, here by the V in Fig. 1 (a) _oS1and V _oS2unified equivalence, to the input of pre-amplification circuit Preamp, is seen as an offset voltage V _oS.Basic thinking is: with for the high level stage, the positive negative input of pre-amplification circuit Preamp is short has all received common-mode voltage V _cMon, if at this moment there is no offset voltage V _oSexist, so comparator will output probability is equal under the impact of internal random noise 0 and 1 digital signal; If but there is offset voltage V in comparator input terminal _oS, the probability of so comparator output 0 and 1 will not wait.Utilize this feature, can control by control circuit CTRL the adjustable mismatch current I that specially adds _b1~ I _b4, thus reach the original offset voltage V of counteracting _oSobject, when comparator after system stability is by 0 and 1 equal for output probability again digital signal.Wherein the form of control circuit CTRL has a variety of, can be digital control, also can be analogue enlargement.

After adopting the method for Fig. 2, pre-amplification circuit Preamp and latch cicuit Latch can adopt small size device, thus ensure that the conversion speed of comparator, and calibration simultaneously also eliminates the impact of imbalance.But this calibration still will add bias current device in this key signal path of pre-amplification circuit Preamp output node, its parasitic capacitance introduced still can bring very large impact to the speed of setting up of prime amplifier.In special ADC system at a high speed, the impact that this restriction brings is very large.

Utility model content

For solving above-mentioned existing shortcoming, main purpose of the present utility model is to provide a kind of analog to digital converter breaker in middle capacitance comparator circuit, this collimation technique can not introduce any parasitic parameter in the signal node of comparator, the response speed of comparator can be improved, be suitable for the application scenario of high-speed ADC.

For reaching above-described object, a kind of analog to digital converter breaker in middle capacitance comparator circuit of the present utility model takes following technical scheme:

A kind of analog to digital converter breaker in middle capacitance comparator circuit, is characterized in that: comprise switched-capacitor circuit, pre-amplification circuit, latch circuit output, mistuning calibration function circuit; Described switched-capacitor circuit connects the input of described pre-amplification circuit, and described latch circuit output connects the output of described pre-amplification circuit, and described mistuning calibration function circuit is connected with pre-amplification link.

Comprise two-phase non-overlapping clock / two-phase non-overlapping clock / two-phase non-overlapping clock / two-phase non-overlapping clock calibration clock calibration sampling clock two-phase non-overlapping clock with two-phase non-overlapping clock for two-phase non-overlapping clock, two-phase non-overlapping clock trailing edge nose ahead in two-phase non-overlapping clock trailing edge, two-phase non-overlapping clock entirety lags behind two-phase non-overlapping clock slightly calibration clock for two-phase non-overlapping clock inversion clock and at two-phase non-overlapping clock low period between be pulled to for some time low level for calibration, calibration sampling clock for two-phase non-overlapping clock same frequency clock, its rising edge sampling calibration clock calibration export.

During switched-capacitor circuit is sampled to input signal, insert one mistuning calibration function period, in alignment time section, the input offset voltage of pre-amplification circuit amplifies to produce by latch circuit output calibrates control square-wave signal, and the threshold voltage of pre-amplification circuit load pipe is adjusted by mistuning calibration function electronic feedback, thus realize the counteracting of input offset voltage, except load pipe M in whole circuit ₅with load pipe M ₄substrate beyond, the substrate of all the other all NMOS tube is all connected to ground, the substrate of all PMOS is all connected to supply voltage.

Described pre-amplification circuit, comprises tail current bias current pipe M ₁, tail current bias voltage V _b1, input difference pipe M ₂, input difference pipe M ₃, diode connect load pipe M ₄, diode connect load pipe M ₅, during switched-capacitor circuit is sampled to input signal, Differential Input V _x+and V _x-all receive common mode electrical level V _cM, be equivalent to the input offset voltage of equivalent inpnt pre-amplification circuit, load pipe M ₄, load pipe M ₅threshold voltage can adjust in real time according to the situation of input offset voltage, to offset the impact of input offset voltage, realize offset voltage calibration.

Described latch circuit output, comprises input amplifier tube M ₆, input amplifier tube M ₇, switching tube M ₈, positive feedback connect load pipe M ₉, positive feedback connect load pipe M ₁₀, with door G ₁, with door G ₂, d type flip flop G ₃, d type flip flop G ₄, at switched-capacitor circuit, sampling and two-phase non-overlapping clock are carried out to input signal with two-phase non-overlapping clock during high level, calibration clock one section is provided to calibrate output time, load pipe M ₈at the control input offset voltage is enlarged into digital signal, and by calibration sampling clock sampling exports as calibration control signal V _c+and V _c-, when two-phase non-overlapping clock during for high level, to the normal comparative result of input signal by with door G ₁, with door G ₂after be produced as comparator output signal V _o+with output signal V _o-.

Described mistuning calibration function circuit, comprises tail current offset M _c1, tail current bias voltage V _b3, input difference pipe M _c2, input difference pipe M _c3, calibration reference voltage V _b2, load resistance R _c1, load resistance R _c2, charge pump bias current pipe M _c4with charge pump bias current pipe M _c7, charge pump bias voltage V _b4with charge pump bias voltage V _b5, charge pump switches pipe M _c5, charge pump switches pipe M _c6, charge pump capacitor C _c, offset M _c4with offset M _c7there is provided equal bias current, switching tube M _c5with switching tube M _c6at calibration control signal V _c+with calibration control signal V _c-control under alternately open, allow upper and lower bias current respectively to electric capacity C _cdischarge and recharge produces charge pump output voltage V _pUMP, charge pump output voltage V _pUMPwith calibration reference voltage V _b2calibration output signal V is produced after comparing amplification _a+with calibration output signal V _a-and feed back to pre-amplification circuit load pipe M respectively ₅with load pipe M ₄substrate, realize input offset voltage calibration.

Adopt the utility model of as above technical scheme, there is following beneficial effect:

The utility model its during switched-capacitor circuit is sampled to input signal, insert one mistuning calibration function period.In this section of alignment time section, the input offset voltage of pre-amplification circuit amplifies to be produced as by comparator calibrates control square-wave signal, and control the threshold voltage of mistuning calibration function electronic feedback adjustment pre-amplification circuit load pipe, thus realizing the counteracting of input offset voltage, comparator normally compares and enlarges input signal afterwards.This collimation technique can not introduce any parasitic parameter in the signal node of comparator, can improve the response speed of comparator, is suitable for the application scenario of high-speed ADC.

Accompanying drawing explanation

Fig. 1 a is traditional switch capacitance comparator.

Fig. 1 b is conventional operation timing waveform.

Fig. 2 is the mistuning calibration function mode of traditional switch capacitance comparator.

Fig. 3 a is the utility model backstage real-time mistuning calibration function switching capacity comparator circuit structure.

Fig. 3 b is the timing waveform of the utility model circuit.

Fig. 4 a is the main node waveform that the utility model+10mV inputs when lacking of proper care.

Fig. 4 b is the main node waveform that the utility model-10mV inputs when lacking of proper care

Embodiment

In order to further illustrate utility model, be described further below in conjunction with accompanying drawing:

As best shown in figures 3 a and 3b, a kind of analog to digital converter breaker in middle capacitance comparator circuit of the present utility model, the comparator background calibration schemes that the utility model proposes is as shown in Fig. 3 (a), primarily of switched-capacitor circuit, pre-amplification circuit, latch circuit output, mistuning calibration function circuit four part composition, Fig. 3 (b) is its timing waveform.Switched-capacitor circuit part is by switch S ₁, switch S ₂, switch S ₃, switch S ₄, switch S ₅, switch S ₆, switch S ₇, switch S ₈, switch S ₉, switch S ₁₀with electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, electric capacity C ₄composition, mainly completes input signal V _iN+with input signal V _iN-with reference signal V _rEF+with reference signal V _rEF-subtraction.Pre-amplification circuit is by NMOS tube M ₁, NMOS tube M ₂, NMOS tube M ₃with PMOS M ₄, PMOS M ₅composition, wherein NMOS tube M ₁for tail current bias current pipe, V _b1for tail current bias voltage, NMOS tube M ₂, NMOS tube M ₃for input difference pipe, PMOS M ₄, PMOS M ₅for the load pipe that diode connects.Latch circuit output is by PMOS M ₆, PMOS M ₇, NMOS tube M ₈, NMOS tube M ₉, NMOS tube M ₁₀, with door G ₁, with door G ₂with d type flip flop G ₃, d type flip flop G ₄composition, wherein PMOS M ₆, PMOS M ₇for input amplifier tube, NMOS tube M ₈for switching tube, NMOS tube M ₉, NMOS tube M ₁₀for load pipe, door G that positive feedback connects ₁, door G ₂be used for producing comparator output signal V _o+with output signal V _o-, door G ₃, door G ₄be used for producing calibration control signal V _c+with calibration control signal V _c-.Mistuning calibration function circuit is by NMOS tube M _c1, NMOS tube M _c2, NMOS tube M _c3, NMOS tube M _c4, NMOS tube M _c5, NMOS tube M _c6, PMOS M _c7, resistance R _c1, resistance R _c2with electric capacity C _ccomposition, wherein NMOS tube M _c1for bias current pipe, V _b3for tail current bias voltage, NMOS tube M _c2, NMOS tube M _c3for input difference pipe, V _b2for calibration reference voltage, resistance R _c1, resistance R _c2for load resistance, NMOS tube M _c4with NMOS tube M _c7for charge pump bias current, V _b4and V _b5for charge pump bias voltage, NMOS tube M _c5, NMOS tube M _c6for calibration control signal V _c+with calibration control signal V _c-the charge pump switches pipe, the C that control _cfor charge pump capacitor, the output signal V of mistuning calibration function circuit _a+with output signal V _a-feed back to pre-amplification circuit load pipe M respectively ₅with load pipe M ₄substrate.Except load pipe M in whole circuit ₅with load pipe M ₄substrate beyond, the substrate of all the other all NMOS tube is all connected to ground, the substrate of all PMOS is all connected to supply voltage.Two-phase non-overlapping clock with two-phase non-overlapping clock for two-phase non-overlapping clock; Two-phase non-overlapping clock trailing edge lead over two-phase non-overlapping clock trailing edge; Two-phase non-overlapping clock slightly lag behind two-phase non-overlapping clock calibration clock for two-phase non-overlapping clock inversion clock, and at two-phase non-overlapping clock low period between be pulled to for some time low level for calibration; Calibration sampling clock for two-phase non-overlapping clock same frequency clock, its rising edge sampling calibration clock calibration export.The working condition of whole circuit is as follows.

When two-phase non-overlapping clock with two-phase non-overlapping clock during for high level, switch S ₁, switch S ₂, switch S ₃, switch S ₄, switch S ₅, switch S ₆closed, switch S ₇, switch S ₈, switch S ₉, switch S ₁₀disconnect, at this moment input signal V _iN+with signal V _iN-respectively to electric capacity C ₁with electric capacity C ₂charging, reference signal V _rEF+with reference signal V _rEF-respectively to electric capacity C ₄with electric capacity C ₃charging.Two-phase non-overlapping clock than two-phase non-overlapping clock early jump becomes low level, allows switch S ₅, switch S ₆leading and switch S ₁, switch S ₂, switch S ₃, switch S ₄disconnect, thus allow electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, electric capacity C ₄right pole plate unsettled, realize electric charge locking.When two-phase non-overlapping clock saltus step is after low level, electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, C ₄the electric charge of upper storage is respectively (supposing that the capacitance of electric capacity is all C):

$\left\{\begin{array}{c}{Q}_{1a}=C(V_{CM}-V_{IN+})\\ Q_{2a}=C(V_{CM}-V_{IN-})\\ Q_{3a}=C(V_{CM}-V_{REF-})\\ Q_{4a}=C(V_{CM}-V_{REF+})\end{array}\right.$

When two-phase non-overlapping clock saltus step is after high level, electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, electric capacity C ₄electric charge redistribute, now electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, electric capacity C ₄the electric charge of upper storage is respectively:

$\left\{\begin{array}{c}{Q}_{1b}=C\·V_{X+}\\ Q_{2b}=C\·V_{X-}\\ Q_{3b}=C\·V_{X+}\\ Q_{4b}=C\·V_{X-}\end{array}\right.$

Due to electric capacity C ₁, electric capacity C ₂, electric capacity C ₃, electric capacity C ₄right pole plate unsettled, according to principle of charge conservation:

$\left\{\begin{array}{c}{Q}_{1a}+Q_{3a}=Q_{1b}+Q_{3b}\\ Q_{2a}+Q_{4a}=Q_{2b}+Q_{4b}\end{array}\right.$

The differential input voltage that can obtain pre-amplification circuit is thus:

$V_{X+}-V_{X-}=\frac{(V_{REF+}-V_{REF-})-(V_{IN+}-V_{IN-})}{2}$

This differential voltage, after pre-amplification circuit amplifies, transfers to latch circuit output.

The work of latch circuit output is divided into two processes: latch output procedure and calibration process.

1) two-phase non-overlapping clock with two-phase non-overlapping clock for being latch output procedure during high level, now calibrate clock for low level, switching tube M ₈turn off.Latch cicuit input pipe M ₆, latch cicuit input pipe M ₇with positive feedback load M ₉, load M ₁₀the output of pre-amplification circuit is enlarged into rapidly and latches output digit signals V _o1+with digital signal V _o1-.Due to two-phase non-overlapping clock for high level, with door G ₁, with door G ₂open, and by latch output signal V _o1+with latch output signal V _o1-export as comparator output signal V _o+with output signal V _o-.

2) two-phase non-overlapping clock with two-phase non-overlapping clock for low level period is calibration process, the now positive negative input V of pre-amplification circuit _x+with positive negative input V _x-all receive common mode electrical level V _cM, the input signal of pre-amplification circuit and input offset voltage.Calibration clock be first high level, switching tube M ₈conducting, PMOS M ₁, PMOS M ₂, PMOS M ₃, PMOS M ₄, PMOS M ₅, PMOS M ₆, PMOS M ₇, NMOS tube M ₈, NMOS tube M ₉, NMOS tube M ₁₀form two-stage amplifying circuit to amplify input offset voltage.Then clock is calibrated become low level, switching tube M ₈turn off, input offset voltage is enlarged into digital signal V rapidly _o1+with digital signal V _o1-, and by trigger G ₃, trigger G ₄be calibrated sampling clock sampling obtains calibrating control signal V _c+with calibration control signal V _c-.Calibrate clock subsequently again become high level, for comparator is prepared to normal input signal amplification below.

The offset M of mistuning calibration function circuit _c4with the offset M of mistuning calibration function circuit _c7there is provided equal bias current, switching tube M _c5with switching tube M _c6at calibration control signal V _c+with signal V _c-control under alternately open, allow upper and lower bias current respectively to electric capacity C _cdischarge and recharge produces charge pump output voltage V _pUMP.This voltage and reference voltage V _b2adjustment voltage V is produced after being amplified by differential amplifier circuit _a+with voltage V _a-, be used for adjusting pre-amplification circuit load pipe M ₄with load pipe M ₅underlayer voltage, thus formed comparator imbalance calibration negative feedback loop.

When comparator produces positive input offset voltage, i.e. V _x+higher than V _x-time, high level V can be produced at calibration phase comparator _c+with low level V _c-.At this moment charge pump is to electric capacity C _ccharging allows charge pump output voltage V _pUMPraise, and then allow calibration voltage V _a-rising, calibration voltage V _a+reduce.By this to load pipe M ₄with load pipe M ₅the adjustment of underlayer voltage, can affect their threshold voltage, thus causes the reciprocal mismatch of pre-amplification circuit load, thus offsets input offset voltage.When after loop stability, calibration control signal V _c+with calibration control signal V _c-low and high level alternately can be exported, charge pump output voltage V _pUMPtend towards stability.When comparator produces negative input offset voltage, loop still adjusts to opposite direction according to said process.

Fig. 4 a and 4b gives simulation waveform when comparator is operated in 100MHz.Wherein Fig. 4 (a) is the situation that there is+10mV input offset voltage, due to the impact of input imbalance, and originally V _c+all the time high level is exported, charge pump output voltage V _pUMPcontinuous rising, imbalance adjustment voltage V _a-raise, lack of proper care adjustment voltage V _a+reduce.After mistuning calibration function completes, V _pUMPfuctuation within a narrow range near a burning voltage, and imbalance adjustment voltage V _a-with adjust voltage V _a+also fuctuation within a narrow range near a stable pressure reduction, V _c+alternately export low and high level.Fig. 4 (b), for there is the situation of-10mV input offset voltage, can see after experienced by similar adjustment process, and loop realizes stable.

Claims (6)

1. an analog to digital converter breaker in middle capacitance comparator circuit, is characterized in that: comprise switched-capacitor circuit, pre-amplification circuit, latch circuit output, mistuning calibration function circuit; Described switched-capacitor circuit connects the input of described pre-amplification circuit, and described latch circuit output connects the output of described pre-amplification circuit, and described mistuning calibration function circuit is connected with pre-amplification link.

2. a kind of analog to digital converter breaker in middle capacitance comparator circuit according to claim 1, is characterized in that: comprise two-phase non-overlapping clock / two-phase non-overlapping clock / two-phase non-overlapping clock / two-phase non-overlapping clock calibration clock calibration sampling clock two-phase non-overlapping clock with two-phase non-overlapping clock for two-phase non-overlapping clock, two-phase non-overlapping clock trailing edge nose ahead in two-phase non-overlapping clock trailing edge, two-phase non-overlapping clock entirety lags behind two-phase non-overlapping clock slightly calibration clock for two-phase non-overlapping clock inversion clock and at two-phase non-overlapping clock low period between be pulled to for some time low level for calibration, calibration sampling clock for two-phase non-overlapping clock same frequency clock, its rising edge sampling calibration clock calibration export.

3. a kind of analog to digital converter breaker in middle capacitance comparator circuit according to claim 1 and 2, it is characterized in that: during switched-capacitor circuit is sampled to input signal, insert one mistuning calibration function period, in alignment time section, the input offset voltage of pre-amplification circuit amplifies to produce by latch circuit output calibrates control square-wave signal, and the threshold voltage of pre-amplification circuit load pipe is adjusted by mistuning calibration function electronic feedback, thus realize the counteracting of input offset voltage, except load pipe M in whole circuit ₅with load pipe M ₄substrate beyond, the substrate of all the other all NMOS tube is all connected to ground, the substrate of all PMOS is all connected to supply voltage.

4. a kind of analog to digital converter breaker in middle capacitance comparator circuit according to claim 1, is characterized in that: described pre-amplification circuit, comprises tail current bias current pipe M ₁, tail current bias voltage V _b1, input difference pipe M ₂, input difference pipe M ₃, diode connect load pipe M ₄, diode connect load pipe M ₅, during switched-capacitor circuit is sampled to input signal, Differential Input V _x+and V _x-all receive common mode electrical level V _cM, be equivalent to the input offset voltage of equivalent inpnt pre-amplification circuit, load pipe M ₄, load pipe M ₅threshold voltage can adjust in real time according to the situation of input offset voltage, to offset the impact of input offset voltage, realize offset voltage calibration.

5. a kind of analog to digital converter breaker in middle capacitance comparator circuit according to claim 1, is characterized in that: described latch circuit output, comprises input amplifier tube M ₆, input amplifier tube M ₇, switching tube M ₈, positive feedback connect load pipe M ₉, positive feedback connect load pipe M ₁₀, with door G ₁, with door G ₂, d type flip flop G ₃, d type flip flop G ₄, at switched-capacitor circuit, sampling and two-phase non-overlapping clock are carried out to input signal with two-phase non-overlapping clock during high level, calibration clock one section is provided to calibrate output time, load pipe M ₈at the control input offset voltage is enlarged into digital signal, and by calibration sampling clock sampling exports as calibration control signal V _c+and V _c-, when two-phase non-overlapping clock during for high level, to the normal comparative result of input signal by with door G ₁, with door G ₂after be produced as comparator output signal V _o+with output signal V _o-.

6. a kind of analog to digital converter breaker in middle capacitance comparator circuit according to claim 1, is characterized in that: described mistuning calibration function circuit, comprises tail current offset M _c1, tail current bias voltage V _b3, input difference pipe M _c2, input difference pipe M _c3, calibration reference voltage V _b2, load resistance R _c1, load resistance R _c2, charge pump bias current pipe M _c4with charge pump bias current pipe M _c7, charge pump bias voltage V _b4with charge pump bias voltage V _b5, charge pump switches pipe M _c5, charge pump switches pipe M _c6, charge pump capacitor C _c, offset M _c4with offset M _c7there is provided equal bias current, switching tube M _c5with switching tube M _c6at calibration control signal V _c+with calibration control signal V _c-control under alternately open, allow upper and lower bias current respectively to electric capacity C _cdischarge and recharge produces charge pump output voltage V _pUMP, charge pump output voltage V _pUMPwith calibration reference voltage V _b2calibration output signal V is produced after comparing amplification _a+with calibration output signal V _a-and feed back to pre-amplification circuit load pipe M respectively ₅with load pipe M ₄substrate, realize input offset voltage calibration.