CN203708221U - Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter - Google Patents
Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter Download PDFInfo
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- CN203708221U CN203708221U CN201320840851.8U CN201320840851U CN203708221U CN 203708221 U CN203708221 U CN 203708221U CN 201320840851 U CN201320840851 U CN 201320840851U CN 203708221 U CN203708221 U CN 203708221U
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Abstract
The utility model provides a broadband sample hold circuit used for a front end of a successive-approximation analog-to-digital converter. The broadband sample hold circuit is composed of a first stage voltage buffer, a clock processing unit, a sampling switch capacitance sub circuit and a second stage voltage buffer. An output terminal of the first stage voltage buffer is connected to an input terminal of the sampling switch capacitance sub circuit which is controlled by a voltage bootstrap unit circuit and a signal output terminal of the sampling switch capacitance sub circuit is connected to a signal input terminal of the second stage voltage buffer. A clock signal is sent to the first stage voltage buffer and the sampling switch capacitance sub circuit by the clock processing unit. The beneficial effects of the utility model are that: with the first stage voltage buffer and the second stage voltage buffer, wherein the first stage voltage buffer is enhanced by broadband and is controlled by a clock and the second stage voltage buffer employs a PMOS source follower with an copying unit of an N-well being biased, bandwidth of an input sampling signal can be increased and a requirement of linearity of the signal can be satisfied with a very low power consumption.
Description
Technical field
The utility model belongs to technical field of analog integrated circuit design, is specifically related to the wideband sampling holding circuit for gradual approaching A/D converter front end.
Background technology
Along with the development of integrated circuit Advanced Manufacturing Technology technology, semiconductor technology has developed into the node below 20 nanometers.The progress of semiconductor technology has brought the features such as low supply voltage, low-power consumption, high integration and little chip area to digital circuit; But for analog circuit, the design of traditional devices becomes more complicated and is difficult to and realizes.Therefore, in Circuits System, function as much as possible being transformed into numeric field that function becomes stronger day by day by analog domain goes to realize and becomes study hotspot.Analog to digital converter is bridge and the tie of building digital circuit and simulated world, need can compatible deep-submicron under the demand of low supply voltage provide enough wide input signal bandwidth in order to meet the demand needs of system maximum number simultaneously.The analog to digital converter of analog to digital converter, especially successive approximation is by the mode to internal circuit configuration---and adopt time-multiplexed serial manner of comparison to realize analog-digital conversion function, realize the maximized object that reduces analog module; Along with the progress of semiconductor technology, the analog to digital converter of successive approximation progressively replaces the analog to digital converter of other types in the hand-held and field of portable devices of demand super low-power consumption.
Modern wireless communication systems presents the feature of modularization, intellectuality, software implementation and functionalization, and require communication system to there is good compatible and stronger flexibility, so that exploitation and upgrading, under the drive of this demand, there is software and radio technique in the mid-90 in last century.This new technology core concept that comes from the requirement of u.s.a. military affairs radio communication is the general-purpose platform by constructing an exploitation, and communication function as much as possible is realized with software.On hardware implementing architecture, require Key Circuit module analog-digital converter circuit as much as possible near antenna, the radiofrequency signal Direct Digital of antenna reception is quantized to convert to digital signal and process for digital signal processor.Thereby the analog input signal bandwidth requirement of analog to digital converter is as much as possible up to more than GHz.But traditional gradual approaching A/D converter is because input sample bandwidth is below hundreds of MHz.The bandwidth requirement of the software radio receiver that is difficult to meet rear end to superfast input signal (more than GHz).Therefore, the bandwidth of the sampling hold circuit of existing structure and power consumption become the bottleneck of gradually-appoximant analog-digital converter performance boost.On market, be badly in need of a kind of for sampling hold circuit analog to digital converter, that take into account high input signal bandwidth and low-power consumption.
Utility model content
Main purpose of the present utility model is to provide a kind of sampling hold circuit for gradual approaching A/D converter front end, to meet the dual requirements of software radio system to high input signal bandwidth and low-power consumption.Its concrete structure is as follows:
For the wideband sampling holding circuit of gradual approaching A/D converter front end, formed by first order voltage buffer 1, clock processing unit 2, sampled, switched capacitor electronic circuit 3, second level voltage buffer 4; Wherein, the signal output part of first order voltage buffer 1 is connected with the signal input part of the sampled, switched capacitor electronic circuit 3 of voltage bootstrapping element circuit control; The signal output part of sampled, switched capacitor electronic circuit 3 is connected with the signal input part of second level voltage buffer 4; Clock processing unit 2 provides clock signal to first order voltage buffer 1 and sampled, switched capacitor electronic circuit 3 respectively;
First order voltage buffer 1, is responsible for, by isolated to sampled, switched capacitor electronic circuit 3 and front stage circuits, reducing the capacitance of equivalent input capacitance; Clock processing unit 2 produces a pair of non-overlapping clock signal, i.e. the first clock signal C K1 and second clock signal CK1N, and non-overlapping clock signal the first clock signal C K1 and second clock signal CK1N are passed to sampled, switched capacitor electronic circuit 3, control and realize the switch of sampled, switched capacitor electronic circuit 3; Clock processing unit 2 also produces multiplication of voltage clock signal C KB, and this multiplication of voltage clock signal C KB is passed to first order voltage buffer 1, realizes the switch of first order voltage buffer 1;
Sampled, switched capacitor electronic circuit 3 comprises voltage bootstrapping element circuit 31 and sample circuit unit 32 two parts; Voltage bootstrapping element circuit 31 is received from the first clock signal C K1 and the second clock signal CK1N that clock processing unit 2 produces and controls sample circuit 32 first order voltage buffer 1 is transmitted to the radiofrequency signal of the coming maintenance of sampling;
Second level voltage buffer 4, for sampled, switched capacitor electronic circuit 3 is isolated with the capacitor array unit of the sampling of rear class, and strengthens the driving force of the capacitor array unit of the sampling of sampled, switched capacitor electronic circuit 3 to rear class.
Say further, first order voltage buffer 1 adopts voltage buffer structure, and work under the non-overlapping clock signal of clock processing unit 2 that plays switch control action: when sampled, switched capacitor electronic circuit 3 is during in sampling configuration, 1 conducting of first order voltage buffer; When sampled, switched capacitor electronic circuit 3 is in Holdover mode lower time, first order voltage buffer 1 is closed, thereby reduces the radiofrequency signal inputted by the imbalance of introducing that is coupled of switch parasitic capacitance under Holdover mode, has reduced the average power consumption of this product simultaneously; Clock processing unit 2 produces a pair of not overlapping clock signal mutually (the first clock signal C K1 and second clock signal CK1N) and a multiplication of voltage clock signal C KB.Concrete steps are as follows:
First clock processing unit 2 produces a pair of not overlapping clock signal mutually, i.e. the first clock signal C K1 and second clock signal CK1N; Clock processing unit 2 provides the clock signal as Continuity signal to controlling voltage bootstrapping element circuit 31 and first order voltage buffer 1; Subsequently, not overlapping clock the first clock signal C K1 and second clock signal CK1N control capacitance multiplication of voltage produce multiplication of voltage clock signal C KB to above-mentioned two of clock processing unit 2 use mutually;
Sampled, switched capacitor electronic circuit 3 is switching tube, voltage bootstrapping element circuit 31 is at the first clock signal C K1, under the control of second clock signal CK1N and multiplication of voltage clock signal C KB, by the voltage transfer feature of electric capacity, produce a grid voltage control clock signal with input voltage linear change, by the grid of the sampling switch pipe in this grid voltage control clock signal control sampled, switched capacitor electronic circuit 3, make sampled, switched capacitor electronic circuit 3 conducting under sampling configuration, and keep gate source voltage and the conducting resistance of sampled, switched capacitor electronic circuit 3 interior switching tubes constant, guarantee that the sampled signal under sampling configuration has good linearity,
Second level voltage buffer 4 is PMOS source class follower configuration, wherein the N trap of PMOS adopts replica bias unit, be responsible for reducing due to the sampled voltage of sampled, switched capacitor electronic circuit 3 change cause that the non-linear to voltage of N trap and P type substrate parasitic capacitance changes the deterioration of the sampled signal linearity causing.
The wideband sampling holding circuit for gradual approaching A/D converter front end that the utility model provides, its first order voltage buffer 1, for isolating switch capacitor cell and front stage circuits, reduces the equivalent input capacitance of analog to digital converter; Clock processing unit 2 for generation of non-overlapping clock and multiplication of voltage clock for controlling bootstrapping clock switch capacitor cell in voltage bootstrapping element circuit 31 and the switch of first order voltage buffer 1; The sample circuit 32 that voltage bootstrapping element circuit 31 is controlled keeps for the sampling to input radio frequency signal; Second level voltage buffer 4, for the capacitor array unit of the sampling of isolating switch capacitor cell and rear class, increases the ability of the driving rear class heavy load electric capacity of switching capacity unit simultaneously.
useful technique effect
Utilize the utility model, adopt the first order voltage buffer of broadband enhancing and clock control and adopt the second level voltage buffer that N trap is carried out to the PMOS source class follower of copied cells biasing, can improve the bandwidth of input sample signal, meet the requirement of the signal linearity simultaneously with extremely low power consumption.Adopt front and back stages voltage buffer can reduce the requirement of extra front and back level drives ability, saved the hardware spending of system.Adopt the switching capacity sampling unit of Bootstrap control can guarantee that system linear degree can be because switching tube conducting resistance be due to the non-linear effects of grid voltage change in voltage introducing in the situation that input signal amplitude is larger.
First order voltage buffer 1 has adopted the voltage buffer structure of bandwidth enhancement, can in reducing power consumption, improve input signal bandwidth, simultaneously for the radiofrequency signal that reduces to input under Holdover mode has increased switch controlling signal by the imbalance of introducing that is coupled of switch parasitic capacitance on this buffer, make only conducting under sampling configuration of voltage buffer, under Holdover mode, close, this switch pattern has further reduced the average power consumption of system.
Sampled, switched capacitor electronic circuit 3 is under sampling configuration when switching tube conducting, and it is constant that the gate source voltage of switching tube keeps, and conducting resistance is constant.Thereby sampling configuration down-sampled signal can produce fabulous linearity index.
Second level voltage buffer 4 has adopted PMOS source class follower configuration, wherein the N trap of PMOS adopts replica bias unit, reduces because sampled voltage changes and causes that the non-linear to voltage of N trap and P type substrate parasitic capacitance changes the deterioration of the sampled signal linearity causing.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of this product.
Fig. 2 is the circuit diagram of first order voltage buffer 1 in Fig. 1.
Fig. 3 is that in Fig. 1, clock treatment circuit 2 produces a pair of non-overlapping clock signal, i.e. the principle of the first clock signal C K1 and second clock signal CK1N letter view.
Fig. 4 is the generation principle letter view of the multiplication of voltage clock of clock treatment circuit 2 in Fig. 1.
Fig. 5 is the circuit diagram of sampled, switched capacitor electronic circuit 3 in Fig. 1.
Fig. 6 is the circuit diagram of second level voltage buffer 4 in Fig. 1.
Sequence number in figure is followed successively by: first order voltage buffer 1, clock processing unit 2, sampled, switched capacitor electronic circuit 3, second level voltage buffer 4, voltage bootstrapping element circuit 31, sample circuit 32, the first clock signal C K1, second clock signal CK1N, multiplication of voltage clock signal C KB, source follower NMOS manages M1, gain enhancement mode PMOS pipe M2, the 3rd switching tube M3, the 4th switching tube M4, the first current source I1, the second current source I2, the 3rd capacitor C b, the 9th switching tube M9, the tenth switching tube M10, the 11 switching tube M11, twelvemo is closed pipe M12, the 13 switching tube M13, the 14 switching tube M14, the 4th capacitor C s, the 7th switching tube M7, reproduction switch pipe M8, the 15 switching tube M15 and sixteenmo close pipe M16, the 3rd current source I3, the 5th source follower PMOS pipe M5, the 4th current source I4, auxiliary the 6th source class follower PMOS pipe M6.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
Referring to Fig. 1, for the wideband sampling holding circuit of gradual approaching A/D converter front end, formed by first order voltage buffer 1, clock processing unit 2, sampled, switched capacitor electronic circuit 3, second level voltage buffer 4; The signal input part of the sampled, switched capacitor electronic circuit 3 that wherein, the signal output part of first order voltage buffer 1 is controlled with voltage bootstrapping element circuit 31 is connected; The signal output part of sampled, switched capacitor electronic circuit 3 is connected with the signal input part of second level voltage buffer 4; Clock processing unit 2 provides clock signal to first order voltage buffer 1 and sampled, switched capacitor electronic circuit 3 respectively;
First order voltage buffer 1, is responsible for, by isolated to sampled, switched capacitor electronic circuit 3 and front stage circuits, reducing the capacitance of equivalent input capacitance.
Referring to Fig. 3 and Fig. 4, clock processing unit 2 produces a pair of non-overlapping clock signal, i.e. the first clock signal C K1 and second clock signal CK1N, and this non-overlapping clock signal first clock signal C K1 and second clock signal CK1N are passed to sampled, switched capacitor electronic circuit 3, control and realize the switch of sampled, switched capacitor electronic circuit 3; Clock processing unit 2 also produces multiplication of voltage clock signal C KB, and this multiplication of voltage clock signal C KB is passed to first order voltage buffer 1, realize the switch of first order voltage buffer 1, wherein, the mechanism of production of the first clock signal C K1 and second clock signal CK1N refers to Fig. 3, and the mechanism of production of multiplication of voltage clock signal C KB refers to Fig. 4; Clock processing unit 2 adopts standard component in the market, produces above-mentioned signal.
Referring to Fig. 1, sampled, switched capacitor electronic circuit 3 comprises voltage bootstrapping element circuit 31 and sample circuit 32 two parts; Voltage bootstrapping element circuit 31 is received from controls sample circuit 32 after the first clock signal C K1 that clock processing unit 2 produces and second clock signal CK1N to transmitted the radiofrequency signal of the coming maintenance of sampling by first order voltage buffer 1;
Second level voltage buffer 4, for sampled, switched capacitor electronic circuit 3 is isolated with the capacitor array unit of the sampling of rear class, and strengthens the driving force of the capacitor array unit of the sampling of sampled, switched capacitor electronic circuit 3 to rear class.
First order voltage buffer 1 adopts voltage buffer structure, and works under the non-overlapping clock signal of clock processing unit 2 that plays switch control action: when sampled, switched capacitor electronic circuit 3 is during in sampling configuration, and 1 conducting of first order voltage buffer; When sampled, switched capacitor electronic circuit 3 is in Holdover mode lower time, first order voltage buffer 1 is closed; Reduce the radiofrequency signal inputted by the imbalance of introducing that is coupled of switch parasitic capacitance under Holdover mode, reduced the average power consumption of this product simultaneously; Clock processing unit 2 produces a pair of not overlapping clock signal mutually (the first clock signal C K1 and second clock signal CK1N) and a multiplication of voltage clock signal C KB.Concrete steps are as follows: first clock processing unit 2 produces a pair of not overlapping clock signal, i.e. the first clock signal C K1 and second clock signal CK1N mutually; Clock processing unit 2 provides clock signal the first clock signal C K1 and the second clock signal CK1N of conducting to controlling voltage bootstrapping element circuit 31 and first order voltage buffer 1; Subsequently, above-mentioned two not overlapping clock signal the first clock signal C K1 and second clock signal CK1N control capacitance multiplication of voltages produce multiplication of voltage clock signal C KB mutually of clock processing unit 2 use; Clock processing unit 2 directly adopts outsourcing piece, and the signal generator of clock processing unit 2 is managed referring to Fig. 3 and Fig. 4.
Sampled, switched capacitor electronic circuit 3 is included as switching tube, voltage bootstrapping element circuit 31 is at non-overlapping clock the first clock signal C K1, under the control of second clock signal CK1N and multiplication of voltage clock signal C KB, by the voltage transfer feature of electric capacity, produce a grid voltage control clock signal with input voltage linear change, by the grid of the sampling switch pipe in this grid voltage control clock signal control sampled, switched capacitor electronic circuit 3, make sampled, switched capacitor electronic circuit 3 conducting under sampling configuration, and keep gate source voltage and the conducting resistance of sampled, switched capacitor electronic circuit 3 interior switching tubes constant, guarantee that the sampled signal under sampling configuration has good linearity.
Second level voltage buffer 4 is PMOS source class follower configuration, wherein the N trap of PMOS adopts replica bias unit, be responsible for reducing due to the sampled voltage of sampled, switched capacitor electronic circuit 3 change cause that the non-linear to voltage of N trap and P type substrate parasitic capacitance changes the deterioration of the sampled signal linearity causing.The output of second level voltage buffer is exported by the drain electrode of pmos source follower, if the back grid of PMOS pipe and drain electrode are directly joined, output contact will a parasitic N trap and P type substrate between the reverse-biased electric capacity of diode, the size of this capacitance is the nonlinear function of reversed bias voltage.In the time that output voltage changes, this capacitance nonlinear change, thus introduce nonlinearity erron.By copying source class follower unit, produce a back gate voltage changing with input, can overcome the nonlinearity erron that the parasitic N trap of output contact and P type substrate parasitic non-linear capacitance are introduced.
Referring to Fig. 2, first order voltage buffer 1 is managed M2, switching tube M3 and M4, the first current source I1 and the second current source I2 and is formed by source follower NMOS pipe M1, gain enhancement mode PMOS; Wherein, the drain electrode of source follower NMOS pipe M1 is connected with the grid of gain enhancement mode PMOS pipe M2; The source electrode of source follower NMOS pipe M1 is connected with the drain electrode of the 4th switching tube M4; The drain electrode of source follower NMOS pipe M1 is connected with the output of the first current source I1, and the input of the first current source I1 is connected with the source electrode of the 3rd switching tube M3, the source electrode of the 4th switching tube M4 respectively; The source electrode of the 4th switching tube M4 is connected with the input of the second current source I2, the output head grounding of the second current source I2; Node between the source follower NMOS pipe source electrode of M1 and the drain electrode of the 4th switching tube M4 is connected with drain electrode, the drain electrode of the 4th switching tube M4 and the signal input part of sampled, switched capacitor electronic circuit 3 of the 3rd switching tube M3 respectively; The source follower NMOS pipe grid of M1 and the output of front stage circuits are connected; The non-overlapping clock signal second clock signal CK1N that the grid receive clock processing unit 2 of the 3rd switching tube M3 produces, non-overlapping clock signal the first clock signal C K1 that the grid receive clock processing unit 2 of the 4th switching tube M4 produces.
Traditional voltage buffer being made up of NMOS tube source grade follower and current source need to increase the power consumption of circuit in order to realize certain input signal bandwidth requirement, document (A 6-Bit, 1.2-GS/s ADC with Wideband THA in 0.13-um CMOS, 2008, IEEE ASSCC) analytic explanation under identical power consumption, enhancement mode source class follower can greatly increase input signal bandwidth.Under Holdover mode, sampling switch pipe is closed simultaneously, and still, due to the impact of parasitic capacitance, the radiofrequency signal of input can enter the imbalance that sampling capacitance causes sampled voltage.The input signal feedthrough causing in order to reduce this parasitic capacitance, in the utility model, switching tube M3 and M4 on the basis of first order voltage buffer, are increased, make the voltage buffer of the first order into break-make switch mode by traditional normal open pattern, switch conduction under sampling configuration, circuit carries out normal voltage-tracing sampling, when circuit is converted to after Holdover mode by sampling configuration, switching tube M3 and M4 close, the first voltage buffer is closed, the power consumption of having saved first order voltage buffer on the one hand, isolate on the one hand the output of input radio frequency signal and voltage buffer, isolate the feed-through path of input radio frequency signal and sampling capacitance voltage, reduce the nonlinear change of the sampled voltage of introducing due to the variation of input signal.
Referring to Fig. 3 and Fig. 4, clock processing unit 2 is to adopt the standard component on market to realize concrete function, is summarized as follows at this: clock processing unit 2 produces the electric circuit constitute by non-overlapping clock-generating circuit and clock multiplication of voltage, produces a pair of non-overlapping clock signal; Referring to Fig. 4 the first clock signal C K1 and second clock signal CK1N, control the 3rd clock signal C KB that is about 2 times of supply voltages by the first clock signal C K1 and second clock signal CK1N control clock voltage-multiplying circuit logic generation voltage is multiplication of voltage clock signal C KB.The schematic diagram that clock processing unit 2 produces multiplication of voltage clock signal C KB as shown in Figure 4, has specifically adopted six switching tubes (the 17 switching tube M17, eighteenmo close pipe M18, the 19 switching tube M19, the 20 switching tube M20, the 21 switching tube M21 and the second twelvemo and close pipe M22) and two electric capacity (the first capacitor C 1 and the second capacitor C 2).
Referring to Fig. 5, sampled, switched capacitor electronic circuit 3 is made up of voltage bootstrapping element circuit 31 and sample circuit 32 two parts; Wherein, voltage bootstrapping element circuit 31 closes pipe M12, the 13 switching tube M13, the 14 switching tube M14 by the 3rd capacitor C b, the 9th switching tube M9, the tenth switching tube M10, the 11 switching tube M11, twelvemo; Wherein, the 3rd capacitor C b, the 11 switching tube M11, twelvemo close pipe M12, the 13 switching tube M13 and the 14 switching tube M14 produces bootstrapping clock jointly, the 9th switching tube M9 and the tenth switching tube M10 produce the cut-off signals of sampling clock, concrete annexation is: the source ground of the 13 switching tube M13, is connected with the source electrode of the 14 switching tube M14 after drain electrode series connection the 3rd capacitor C b of the 13 switching tube M13; The drain electrode of the 13 switching tube M13 is also connected with the drain electrode of the 11 switching tube M11; The source electrode of the 14 switching tube M14 is also connected with the drain electrode of twelvemo pass pipe M12, and is closed the grid voltage of pipe M12 by the 14 switching tube M14 source electrode control twelvemo; The source electrode that twelvemo is closed pipe M12 is connected with the drain electrode of the 9th switching tube M9, and the source electrode of the 9th switching tube M9 is connected with the drain electrode of the tenth switching tube M10, the source ground of the tenth switching tube M10.
Referring to Fig. 5, sample circuit 32 closes pipe M16 by the 4th capacitor C s, the 7th switching tube M7, reproduction switch pipe M8, the 15 switching tube M15 and sixteenmo and forms; Wherein, the 4th capacitor C s and the 7th switching tube M7 realize the function of sampling jointly, and by reproduction switch pipe M8, the back grid of the 7th switching tube M7 is setovered, and in the time that this circuit is under Holdover mode, move the back grid of the 7th switching tube M7 in analog current potential by the conducting of the 15 switching tube M15 and sixteenmo pass pipe M16 successively; Its concrete structure is: the back grid of the 7th switching tube M7 is connected with the back grid of reproduction switch pipe M8; The back of the body grid of reproduction switch pipe M8 are connected with the drain electrode of the 15 switching tube M15; The source electrode of the 15 switching tube M15 closes pipe M16 drain electrode with sixteenmo and is connected, and sixteenmo closes the source ground of pipe M16; The drain electrode of the 7th switching tube M7 is ground connection after the 4th capacitor C s, and the output signal of the drain electrode of the 7th switching tube M7 is sampled signal VS; Being connected between voltage bootstrapping element circuit 31 and sample circuit unit be being connected of source electrode by the 11 switching tube M11 and the 7th switching tube M7, and twelvemo pass managed the drain electrode of M12 and realizes being connected of grid of the 6th switching tube M7.
Under the sampling hold circuit proposing at the utility model, can accomplish to keep certain linearity performance under larger input signal amplitude.
Referring to Fig. 6, second level voltage buffer 4 is made up of the 3rd current source I3, the 5th source class follower PMOS pipe M5, the 4th current source I4 and auxiliary the 6th source class follower PMOS pipe M6, the grid of the 5th source follower PMOS pipe M5 is connected as the input of second level voltage buffer with the grid of the 6th source class follower PMOS pipe M6, the source electrode of auxiliary the 6th source class follower PMOS pipe M6 is connected with the back grid of auxiliary the 6th source class follower PMOS pipe, auxiliary the 6th source electrode of source class follower PMOS pipe M6 and the tie point of back of the body grid are connected with the back of the body grid of the 5th source follower PMOS pipe M5, the source electrode of the 5th source follower PMOS pipe M5 is connected as the output of second level voltage buffer with the 3rd current source I3, the source electrode of auxiliary the 6th source class follower PMOS pipe M6 is connected with the 4th current source I4.The input of second level voltage buffer meets the output signal VS of sampled, switched capacitor unit, by the source electrode Vout output by source class follower PMOS after the voltage buffer of the second level.
Wherein main source class follower completes the transmission of sampled signal to late-class circuit, and auxiliary source class follower completes the N trap biasing to main PMOS pipe.Wherein the size of main source class follower and auxiliary source class follower and electric current can be by the ratio settings of 20:1.This circuit of realizing can greatly reduce because main source class is followed the N trap of organ pipe PMOS pipe and the linearity impact of the non-linear to voltage of the parasitic capacitance that P type substrate produces on sample circuit.
Claims (5)
1. for the wideband sampling holding circuit of gradual approaching A/D converter front end, it is characterized in that: formed by first order voltage buffer (1), clock processing unit (2), sampled, switched capacitor electronic circuit (3) and second level voltage buffer (4); The signal input part of the sampled, switched capacitor electronic circuit (3) that wherein, the signal output part of first order voltage buffer (1) is controlled with voltage bootstrapping element circuit (31) is connected; The signal output part of sampled, switched capacitor electronic circuit (3) is connected with the signal input part of second level voltage buffer (4); Clock processing unit (2) provides clock signal to first order voltage buffer (1) and sampled, switched capacitor electronic circuit (3) respectively; First order voltage buffer (1), is responsible for, by isolated to sampled, switched capacitor electronic circuit (3) and front stage circuits, reducing the capacitance of equivalent input capacitance; Clock processing unit (2) produces a pair of non-overlapping clock signal, i.e. the first clock signal C K1 and second clock signal CK1N, and by this to non-overlapping clock signal: the first clock signal C K1 and second clock signal CK1N are passed to sampled, switched capacitor electronic circuit (3), control and realize the switch of sampled, switched capacitor electronic circuit (3); Clock processing unit (2) also produces multiplication of voltage clock signal C KB, and this multiplication of voltage clock signal C KB is passed to first order voltage buffer (1), realizes the switch of first order voltage buffer (1); Sampled, switched capacitor electronic circuit (3) comprises voltage bootstrapping element circuit (31) and sample circuit (32) two parts; Voltage bootstrapping element circuit (31) is received from controls sample circuit (32) after the first clock signal C K1 that clock processing unit (2) produces and second clock signal CK1N to the radiofrequency signal of being come by first order voltage buffer (1) the transmission maintenance of sampling; Second level voltage buffer (4), for by isolated the capacitor array unit of the sampling of sampled, switched capacitor electronic circuit (3) and rear class, and strengthens the driving force of the capacitor array unit of the sampling of sampled, switched capacitor electronic circuit (3) to rear class.
2. the wideband sampling holding circuit for gradual approaching A/D converter front end as claimed in claim 1, it is characterized in that: first order voltage buffer (1) adopts voltage buffer structure, and work under the non-overlapping clock signal of clock processing unit (2) that plays switch control action: when sampled, switched capacitor electronic circuit (3) is during in sampling configuration, first order voltage buffer (1) conducting, when sampled, switched capacitor electronic circuit (3) is in Holdover mode lower time, first order voltage buffer (1) is closed, sampled, switched capacitor electronic circuit (3) is switching tube, voltage bootstrapping element circuit (31) is at the first clock signal C K1, under the control of second clock signal CK1N and multiplication of voltage clock signal C KB, by the voltage transfer feature of electric capacity, produce a grid voltage control clock signal with input voltage linear change, by the grid of the sampling switch pipe in this grid voltage control clock signal control sampled, switched capacitor electronic circuit (3), make sampled, switched capacitor electronic circuit (3) conducting under sampling configuration, and keep gate source voltage and the conducting resistance of the interior switching tube of sampled, switched capacitor electronic circuit (3) constant, guarantee that the sampled signal under sampling configuration has good linearity,
Second level voltage buffer (4) is PMOS source class follower configuration, wherein the N trap of PMOS adopts replica bias unit, be responsible for reducing due to the sampled voltage of sampled, switched capacitor electronic circuit (3) change cause that the non-linear to voltage of N trap and P type substrate parasitic capacitance changes the deterioration of the sampled signal linearity causing.
3. the wideband sampling holding circuit for gradual approaching A/D converter front end as claimed in claim 1 or 2, is characterized in that: first order voltage buffer (1) is made up of source follower NMOS pipe M1, gain enhancement mode PMOS pipe M2, the 3rd switching tube M3, the 4th switching tube M4, the first current source I1 and the second current source I2; Wherein, the drain electrode of source follower NMOS pipe M1 is connected with the grid of gain enhancement mode PMOS pipe M2; The source electrode of source follower NMOS pipe M1 is connected with the drain electrode of the 4th switching tube M4; The drain electrode of source follower NMOS pipe M1 is connected with the output of the first current source I1, and the input of the first current source I1 is connected with the source electrode of the 3rd switching tube M3, the source electrode of the 4th switching tube M4 respectively; The source electrode of the 4th switching tube M4 is connected with the input of the second current source I2, the output head grounding of the second current source I2; Node between the source follower NMOS pipe source electrode of M1 and the drain electrode of the 4th switching tube M4 is connected with drain electrode, the drain electrode of the 4th switching tube M4 and the signal input part of sampled, switched capacitor electronic circuit (3) of the 3rd switching tube M3 respectively; The source follower NMOS pipe grid of M1 and the output of front stage circuits are connected; The non-overlapping clock signal C K1N that the grid receive clock processing unit (2) of the 3rd switching tube M3 produces, the non-overlapping clock signal C K1 that the grid receive clock processing unit (2) of the 4th switching tube M4 produces.
4. the wideband sampling holding circuit for gradual approaching A/D converter front end as claimed in claim 1 or 2, is characterized in that: sampled, switched capacitor electronic circuit (3) is made up of voltage bootstrapping element circuit (31) and sample circuit (32) two parts; Wherein, voltage bootstrapping element circuit (31) closes pipe M12, the 13 switching tube M13 and the 14 switching tube M14 by the 3rd capacitor C b, the 9th switching tube M9, the tenth switching tube M10, the 11 switching tube M11, twelvemo; Wherein, the 3rd capacitor C b, the 11 switching tube M11, twelvemo close pipe M12, the 13 switching tube M13 and the 14 switching tube M14 produces bootstrapping clock jointly, the 9th switching tube M9 and the tenth switching tube M10 produce the cut-off signals of sampling clock, concrete annexation is: the source ground of the 13 switching tube M13, is connected with the source electrode of the 14 switching tube M14 after drain electrode series connection the 3rd capacitor C b of the 13 switching tube M13; The drain electrode of the 13 switching tube M13 is also connected with the drain electrode of the 11 switching tube M11; The source electrode of the 14 switching tube M14 is also connected with the drain electrode of twelvemo pass pipe M12, and is closed the grid voltage of pipe M12 by the 14 switching tube M14 source electrode control twelvemo; The source electrode that twelvemo is closed pipe M12 is connected with the drain electrode of the 9th switching tube M9, and the source electrode of the 9th switching tube M9 is connected with the drain electrode of the tenth switching tube M10, the source ground of the tenth switching tube M10;
Sample circuit (32) closes pipe M16 by the 4th capacitor C s, the 7th switching tube M7, reproduction switch pipe M8, the 15 switching tube M15 and sixteenmo and forms; Wherein, the 4th capacitor C s and the 7th switching tube M7 realize the function of sampling jointly, and by reproduction switch pipe M8, the back grid of the 7th switching tube M7 is setovered, and in the time that this circuit is under Holdover mode, the conducting of closing pipe M16 by the 15 switching tube M15 and sixteenmo is moved the back grid of the 7th switching tube M7 in analog current potential; Its concrete structure is: the back grid of the 7th switching tube M7 is connected with the back grid of reproduction switch pipe M8; The back grid of reproduction switch pipe M8 is connected with the drain electrode of the 15 switching tube M15; The source electrode of the 15 switching tube M15 closes pipe M16 drain electrode with sixteenmo and is connected, and sixteenmo closes the source ground of pipe M16; The drain electrode of the 7th switching tube M7 is ground connection after the 4th capacitor C s, and the output signal of the drain electrode of the 7th switching tube M7 is sampled signal VS; Being connected between voltage bootstrapping element circuit (31) and sample circuit (32) be being connected of source electrode by the 11 switching tube M11 and the 7th switching tube M7, and twelvemo pass managed the drain electrode of M12 and realizes being connected of grid of the 7th switching tube M7.
5. the wideband sampling holding circuit for gradual approaching A/D converter front end as claimed in claim 1 or 2, is characterized in that: second level voltage buffer (4) is made up of the 3rd current source I3, the 5th source follower PMOS pipe M5, the 4th current source I4 and auxiliary the 6th source class follower PMOS pipe M6; The grid of the 5th source follower PMOS pipe M5 is connected as the input of second level voltage buffer (4) with the grid of auxiliary the 6th source class follower PMOS pipe M6, the source electrode of auxiliary the 6th source class follower PMOS pipe M6 is connected with back grid and is connected with the back of the body grid of the 5th source follower PMOS pipe M5, the source electrode of five source follower PMOS pipe M5 is connected as the output of second level voltage buffer (4) with the 3rd current source I3, and the source electrode of auxiliary the 6th source class follower PMOS pipe M6 is connected with the 4th current source I4.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320840851.8U CN203708221U (en) | 2013-12-19 | 2013-12-19 | Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320840851.8U CN203708221U (en) | 2013-12-19 | 2013-12-19 | Broadband sample hold circuit used for front end of successive-approximation analog-to-digital converter |
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| CN203708221U true CN203708221U (en) | 2014-07-09 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103716054A (en) * | 2013-12-19 | 2014-04-09 | 中国电子科技集团公司第三十八研究所 | Broadband sampling holding circuit used for successive approximation type analog-to-digital converter front-end |
| CN104270153A (en) * | 2014-09-18 | 2015-01-07 | 东南大学 | Multi-channel sampling grid voltage bootstrapping switch suitable for streamline type analog-digital converter |
| CN111510148A (en) * | 2020-05-07 | 2020-08-07 | 西安交通大学 | High-speed multi-path time-interleaved SAR analog-to-digital converter |
| CN113014259A (en) * | 2021-02-25 | 2021-06-22 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN113300708A (en) * | 2021-04-09 | 2021-08-24 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
-
2013
- 2013-12-19 CN CN201320840851.8U patent/CN203708221U/en not_active Withdrawn - After Issue
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103716054A (en) * | 2013-12-19 | 2014-04-09 | 中国电子科技集团公司第三十八研究所 | Broadband sampling holding circuit used for successive approximation type analog-to-digital converter front-end |
| CN104270153A (en) * | 2014-09-18 | 2015-01-07 | 东南大学 | Multi-channel sampling grid voltage bootstrapping switch suitable for streamline type analog-digital converter |
| CN111510148A (en) * | 2020-05-07 | 2020-08-07 | 西安交通大学 | High-speed multi-path time-interleaved SAR analog-to-digital converter |
| CN113014259A (en) * | 2021-02-25 | 2021-06-22 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN113300708A (en) * | 2021-04-09 | 2021-08-24 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
| CN113300708B (en) * | 2021-04-09 | 2023-03-21 | 西安电子科技大学 | Broadband input signal buffer applied to ultra-high-speed analog-to-digital converter |
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