CN113114256B - Offset correction circuit of continuous time ADC comparator and analog-to-digital converter - Google Patents
Offset correction circuit of continuous time ADC comparator and analog-to-digital converter Download PDFInfo
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Abstract
The invention provides an offset correction circuit of a continuous time ADC comparator and an analog-to-digital converter, comprising a bias voltage generating circuit, a bias current generating circuit, a correction current generating circuit and a controller; the controller is connected with the output end of the ADC comparator and used for acquiring the output of the ADC comparator; the bias current generating circuit is used for generating a pair of adjustable differential voltages under the control of the controller; the bias current generating circuit is connected with the bias voltage generating circuit and is used for generating bias current under the control of the adjustable differential voltage; the correction current generation circuit is connected with the bias current generation circuit and used for generating corresponding correction current by taking the bias current as reference current under the control of the controller and inputting the correction current into the input end of the preamplifier in the ADC comparator as compensation current. By the mode, the influence of temperature on the offset voltage of the comparator is reduced, and the linearity consistency of the ADC at each temperature is improved.
Description
Technical Field
The invention relates to the technical field of digital-analog integrated circuits, in particular to an offset correction circuit of a continuous time ADC comparator and an analog-digital converter.
Background
As the demand for bandwidth in data transmission networks increases, the data converter, as a key circuit therein, is also moving towards higher precision and higher sampling rate. The comparator is the most important key circuit in an analog-to-digital converter (ADC), and its speed directly determines the sampling bandwidth and the conversion rate of the ADC. In advanced technologies, ADCs can use smaller feature size transistors to build high speed comparators and other circuits. The smaller size of the comparator, while achieving higher speed, causes the detuning to become more severe and the linearity of the ADC to deteriorate dramatically. The offset correction of the comparator is very necessary.
The conventional comparator correction circuit compensates for the offset by adding an adjustable voltage at the reference terminal or injecting a compensation current at both terminals of the comparator. The two methods can effectively correct at a certain temperature, but the offset voltage of the comparator can change along with the change of the temperature, so that the correction is invalid, and the linearity of the ADC is deteriorated. Although some methods can correct the ADC again after the temperature changes too much, the performance at the current temperature is guaranteed to be improved. This approach, however, causes an interruption in the operation of the ADC, which is unacceptable in many data acquisition systems. It is desirable to provide a scheme to reduce the effect of temperature on the offset voltage of the comparator while improving the uniformity of the linearity of the ADC at various temperatures.
Disclosure of Invention
The invention aims to provide an offset correction circuit of a continuous-time ADC comparator and an analog-to-digital converter, which are used for reducing the influence of temperature on offset voltage of the comparator and ensuring the technical effect that the linearity of the ADC is kept consistent at all temperatures.
In a first aspect, the present invention provides an offset correction circuit for a continuous-time ADC comparator, comprising a bias voltage generation circuit, a bias current generation circuit, a correction current generation circuit, and a controller; the controller is connected with the output end of the ADC comparator and used for acquiring the output of the ADC comparator; the bias voltage generating circuit is used for generating a pair of adjustable differential voltages under the control of the controller; the bias current generating circuit is connected with the bias voltage generating circuit and used for generating bias current under the control of the adjustable differential voltage; the correction current generation circuit is connected with the bias current generation circuit and used for generating corresponding correction current by taking the bias current as reference current under the control of the controller and inputting the correction current into the input end of a preamplifier in the ADC comparator to be used as compensation current.
Further, the bias voltage generating circuit is an adjustable resistor ladder circuit.
Further, the bias voltage generating circuit comprises a VRP output end, a VRN output end, a first regulating circuit, a second regulating circuit, a first resistor, a second resistor and a third resistor; the first end of the first regulating circuit is connected with a power supply; the first end of the first resistor is connected with the second end of the first regulating circuit; the first end of the second resistor and the second end of the first resistor are both connected with the VRP output end; the first end of the second regulating circuit is grounded; the first end of the third resistor is connected with the second end of the second regulating circuit; and the second end of the third resistor and the second end of the second resistor are both connected with the VRN output end.
Further, the first regulating circuit comprises a first CMOS tube, a second CMOS tube, a third CMOS tube, a fourth resistor, a fifth resistor and a sixth resistor; the grid electrode of the first CMOS tube, the grid electrode of the second CMOS tube and the grid electrode of the third CMOS tube are all connected with a controller; the source electrode of the first CMOS tube, the source electrode of the second CMOS tube and the source electrode of the third CMOS tube are all connected with a power supply; the fourth resistor is connected between the source electrode and the drain electrode of the first CMOS tube; the fifth resistor is connected between the drain electrode of the first CMOS tube and the drain electrode of the second CMOS tube; the sixth resistor is connected between the drain electrode of the second CMOS tube and the drain electrode of the third CMOS tube, and the drain electrode of the third CMOS tube is connected with the first end of the first resistor.
Further, the second regulating circuit comprises a fourth CMOS transistor, a fifth CMOS transistor, a sixth CMOS transistor, a seventh resistor, an eighth resistor and a ninth resistor; the grid electrode of the fourth CMOS tube, the grid electrode of the fifth CMOS tube and the grid electrode of the sixth CMOS tube are all connected with a controller; the source electrode of the fourth CMOS tube, the source electrode of the fifth CMOS tube and the source electrode of the sixth CMOS tube are all grounded; the seventh resistor is connected between the source electrode and the drain electrode of the fourth CMOS tube; the eighth resistor is connected between the drain electrode of the fourth CMOS tube and the drain electrode of the fifth CMOS tube; the ninth resistor is connected between the drain electrode of the fifth CMOS tube and the drain electrode of the sixth CMOS tube, and the drain electrode of the sixth CMOS tube is connected with the first end of the third resistor.
Further, the bias current generating circuit comprises a reference voltage input end, a seventh CMOS tube, an eighth CMOS tube, a ninth CMOS tube, a tenth CMOS tube, an eleventh CMOS tube and a bias current control circuit; the grid electrode of the seventh CMOS tube is connected with the reference voltage input end; the source electrode of the seventh CMOS tube is connected with a power supply; the source electrode of the eighth CMOS tube and the source electrode of the ninth CMOS tube are both connected with the drain electrode of the seventh CMOS tube; the grid electrode of the eighth CMOS tube is connected with the VRN output end; the grid electrode of the ninth CMOS tube is connected with the VRP output end; the drain electrode and the grid electrode of the tenth CMOS tube and the grid electrode of the eleventh CMOS tube are both connected with the drain electrode of the eighth CMOS tube; the source electrode of the tenth CMOS tube and the source electrode of the eleventh CMOS tube are both grounded; the bias current control circuit is used for generating two paths of bias currents according to input voltage under the control of given bias voltage, wherein one path of bias current is transmitted to the drain electrode of the eleventh CMOS tube and the drain electrode of the ninth CMOS tube, and the other path of bias current is transmitted to the correction current generation circuit.
Further, the bias current control circuit comprises a twelfth CMOS tube, a thirteenth CMOS tube, an operational amplifier and a bias voltage input end; the source electrode of the twelfth CMOS tube and the source electrode of the thirteenth CMOS tube are both connected with a power supply; the inverting input end of the operational amplifier is connected with the bias voltage input end; the output end of the operational amplifier is respectively connected with the grid electrode of the twelfth CMOS tube and the grid electrode of the thirteenth CMOS tube; the drain electrode of the twelfth CMOS tube is connected with the non-inverting input end of the operational amplifier, and meanwhile, the drain electrode of the twelfth CMOS tube is respectively connected with the drain electrode of the eleventh CMOS tube and the drain electrode of the ninth CMOS tube; and the drain electrode of the thirteenth CMOS tube is connected with the correction current generating circuit.
Further, the correction current generation circuit comprises a first correction current output end, a second correction current output end, a fourteenth CMOS transistor, a fifteenth CMOS transistor, a sixteenth CMOS transistor, a seventeenth CMOS transistor, an eighteenth CMOS transistor, a first adjustable CMOS transistor and a second adjustable CMOS transistor; the drain electrode and the grid electrode of the fourteenth CMOS tube, the grid electrode of the first adjustable CMOS tube and the grid electrode of the second adjustable CMOS tube are connected with the bias current generating circuit; the source electrode of the first adjustable CMOS tube, the source electrode of the fourteenth CMOS tube and the source electrode of the second adjustable CMOS tube are all grounded; the drain electrode and the grid electrode of the fifteenth CMOS tube and the grid electrode of the sixteenth CMOS tube are connected with the drain electrode of the first adjustable CMOS tube; the drain electrode of the sixteenth CMOS tube is connected with the first correction current output end; the drain electrode and the grid electrode of the seventeenth CMOS tube and the grid electrode of the eighteenth CMOS tube are connected with the drain electrode of the second adjustable CMOS tube; the drain electrode of the eighteenth CMOS tube is connected with the second correction current output end; the source electrode of the fifteenth CMOS tube, the source electrode of the sixteenth CMOS tube, the source electrode of the seventeenth CMOS tube and the source electrode of the eighteenth CMOS tube are all connected with a power supply; meanwhile, the first adjustable CMOS tube and the second adjustable CMOS tube are both connected with the controller.
In a second aspect, the present invention provides an analog-to-digital converter, comprising a plurality of cascaded integrators; the quantizer is connected with the output end of the last stage integrator and is a Flash ADC (analog to digital converter) consisting of a plurality of comparators; the digital-to-analog converters are connected with the output end of the quantizer; the offset calibration positive circuit is connected with the comparator; the adders are connected with the digital-to-analog converters in a one-to-one corresponding mode; the adder is used for integrating the output of the previous stage integrator and the output of the corresponding digital-to-analog converter and then taking the integrated output as the input of the next stage integrator.
The beneficial effects that the invention can realize are as follows: the controller in the offset correction circuit of the continuous time ADC comparator can adjust the bias voltage generation circuit, the correction current generation circuit and the like according to the output of the comparator until the output state of the comparator is turned over so as to finish correction; meanwhile, the bias current generating circuit adopts the same structure as the pre-amplifying circuit of the comparator, so that only a small differential voltage needs to be applied between the differential pairs to obtain a transconductance current, and a reference bias current is generated. The circuit can output a current which is positively correlated with the transconductance of the comparator, thereby ensuring the temperature stability of the comparator during correction, reducing the influence of the temperature on the offset voltage of the comparator and simultaneously improving the linearity consistency of the ADC at each temperature.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is an overall circuit schematic diagram of a conventional ADC comparator according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a topology of an offset correction circuit of a continuous-time ADC comparator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a bias voltage generating circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a bias current generating circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a calibration current generating circuit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a topology structure of an analog-to-digital converter according to an embodiment of the present invention.
An icon: 10-an analog-to-digital converter; 100-offset correction circuit; 110-bias voltage generating circuit; 111-a first regulating circuit; 112-a second regulating circuit; 120-bias current generating circuit; 121-bias current control circuit; 130-a correction current generating circuit; 140-a controller; 200-an integrator; 300-a quantizer; 400-a digital-to-analog converter; 500-adder.
Detailed Description
The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1 and fig. 2, fig. 1 is an overall circuit schematic diagram of a conventional ADC comparator according to an embodiment of the present invention; fig. 2 is a schematic diagram of a topology of an offset correction circuit of a continuous-time ADC comparator according to an embodiment of the present invention.
The applicant finds that the traditional comparator correction circuit compensates the offset by adding an adjustable voltage at the reference end or injecting a compensation current at two ends of the comparator. The two methods can effectively correct at a certain temperature, but the offset voltage of the comparator can change along with the change of the temperature, so that the correction is invalid, and the linearity of the ADC is deteriorated. Therefore, the present application provides an offset correction circuit 100 for a continuous-time ADC comparator to improve the linearity uniformity of the ADC at various temperatures while reducing the temperature effect on the offset voltage of the comparator.
The offset adjustment circuit 100 includes a bias voltage generation circuit 110, a bias current generation circuit 120, an adjustment current generation circuit 130 and a controller 140; the controller 140 is connected to the output end of the ADC comparator for obtaining the output of the ADC comparator; the bias voltage generating circuit 110 is used for generating a pair of adjustable differential voltages under the control of the controller 140; the bias current generating circuit 120 is connected to the bias voltage generating circuit 110, and is configured to generate a bias current under the control of the adjustable differential voltage; the correction current generation circuit 130 is connected to the bias current generation circuit 120, and is configured to generate a corresponding correction current using the bias current as a reference current under the control of the controller 140, and input the correction current to an input terminal of a preamplifier in the ADC comparator as a compensation current.
In the above implementation process, the controller 140 may be controlled by software, and the bias current generating circuit 120 and the correction current generating circuit 130 may be controlled by software programs. Specifically, under the control of the controller 140, the bias voltage generating circuit 110 may generate a pair of adjustable differential voltages, then control the bias current generating circuit 120 to generate a bias current through the pair of adjustable differential voltages, and finally the correction current generating circuit 130 generates a corresponding correction current according to the bias current and inputs the correction current to the input terminal of the preamplifier in the high-speed comparator as the compensation current.
It should be noted that the controller 140 may also be controlled by digital logic, and is not limited to controlling the bias current generating circuit 120 and the correction current generating circuit 130 by using software programs.
Referring to fig. 3, fig. 3 is a schematic diagram of a bias voltage generating circuit according to an embodiment of the invention.
In one implementation, the bias voltage generating circuit 110 provided in the embodiment of the present invention is an adjustable resistor ladder circuit. Illustratively, the bias voltage generating circuit 110 includes a VRP output terminal, a VRN output terminal, a first regulating circuit 111, a second regulating circuit 112, a first resistor (R1), a second resistor (R2), and a third resistor (R3); a first terminal of the first regulating circuit 111 is connected to a power supply (VCC); a first terminal of the first resistor (R1) is connected to a second terminal of the first adjusting circuit 111; the first end of the second resistor (R2) and the second end of the first resistor (R1) are both connected with the VRP output end; a first terminal of the second regulating circuit 112 is grounded; a first end of the third resistor (R3) is connected to a second end of the second adjusting circuit 112; and the second end of the third resistor (R3) and the second end of the second resistor (R2) are both connected with the VRN output end.
Specifically, the first adjusting circuit 111 includes a first CMOS transistor (CN 0), a second CMOS transistor (CN 1), a third CMOS transistor (CN 2), a fourth resistor (R4), a fifth resistor (R5), and a sixth resistor (R6); the grid electrode of the first CMOS tube (CN 0), the grid electrode of the second CMOS tube (CN 1) and the grid electrode of the third CMOS tube (CN 2) are all connected with the controller 140; the source electrode of the first CMOS tube (CN 0), the source electrode of the second CMOS tube (CN 1) and the source electrode of the third CMOS tube (CN 2) are all connected with a power supply (VCC); the fourth resistor (R4) is connected between the source electrode and the drain electrode of the first CMOS transistor (CN 0); the fifth resistor (R5) is connected between the drain electrode of the first CMOS tube (CN 0) and the drain electrode of the second CMOS tube (CN 1); the sixth resistor (R6) is connected between the drain electrode of the second CMOS tube (CN 1) and the drain electrode of the third CMOS tube (CN 2), and the drain electrode of the third CMOS tube (CN 2) is connected with the first end of the first resistor (R1).
The second adjusting circuit 112 includes a fourth CMOS transistor (C0), a fifth CMOS transistor (C1), a sixth CMOS transistor (C2), a seventh resistor (R7), an eighth resistor (R8), and a ninth resistor (R9); the grid electrode of the fourth CMOS tube (C0), the grid electrode of the fifth CMOS tube (C1) and the grid electrode of the sixth CMOS tube (C2) are all connected with the controller 140; the source electrode of the fourth CMOS tube (C0), the source electrode of the fifth CMOS tube (C1) and the source electrode of the sixth CMOS tube (C2) are all grounded; the seventh resistor (R7) is connected between the source electrode and the drain electrode of the fourth CMOS tube (C0); the eighth resistor (R8) is connected between the drain electrode of the fourth CMOS tube (C0) and the drain electrode of the fifth CMOS tube (C1); the ninth resistor (R9) is connected between the drain electrode of the fifth CMOS tube (C1) and the drain electrode of the sixth CMOS tube (C2), and the drain electrode of the sixth CMOS tube (C2) is connected with the first end of the third resistor (R3).
In the implementation process, the bias voltage generating circuit 110 adopts a resistor ladder circuit structure, and the controller 140 can obtain a series of differential voltages (VRP-VRN) with different amplitudes by adjusting and controlling C0-C2 and CN 0-CN 2, so as to implement output of the adjustable differential voltage.
Referring to fig. 4, fig. 4 is a schematic diagram of a bias current generating circuit according to an embodiment of the invention.
The preamplifier input differential pair M1 and M2 shown in fig. 1, ideally without input, should have the same parameters and flow the same current. However, random errors occur in two pipes in the actual production process, and the errors can be divided into two parts: the threshold voltage mismatch Δ VTH and the current factor mismatch Δ β/β. These two parameters are unknown at the design stage but are fixed after production. Therefore, the mismatch Δ I of the differential current can be expressed as:
where current I is the normalized current of the differential pair and gm is the normalized transconductance of the differential pair. Δ V TH Remains substantially constant over temperature, and Δ β/β is weakly temperature dependent. But because of the mobility dependence, the transconductance gm of the tube shows a strong temperature dependence. The current mismatch Δ I and the temperature T therefore show a strong correlation, which can be expressed as:
the normalized current mismatch can be expressed as:
since the input of the high-speed comparator usually adopts a small-sized input tube, the offset current mainly consists of gm and Δ V TH Dominating, the effect of Δ β/β is smaller. Therefore, to ensure the temperature stability of the offset correction of the comparator, the correction current needs to be a current that is positively correlated with gm of the input tube of the comparator.
In one implementation, the bias current generating circuit 120 provided by the embodiment of the present invention includes a reference voltage input terminal (VBCS), a seventh CMOS transistor (M5), an eighth CMOS transistor (M6), a ninth CMOS transistor (M7), a tenth CMOS transistor (M10), an eleventh CMOS transistor (M11), and a bias current control circuit 121; the grid electrode of the seventh CMOS tube (M5) is connected with the reference voltage input end; the source electrode of the seventh CMOS tube (M5) is connected with a power supply; the source electrode of the eighth CMOS transistor (M6) and the source electrode of the ninth CMOS transistor (M7) are both connected with the drain electrode of the seventh CMOS transistor (M5); the grid electrode of the eighth CMOS tube (M6) is connected with the VRN output end; the grid electrode of the ninth CMOS tube (M7) is connected with the VRP output end; the drain electrode and the grid electrode of the tenth CMOS tube (M10) and the grid electrode of the eleventh CMOS tube (M11) are both connected with the drain electrode of the eighth CMOS tube (M6); the source electrode of the tenth CMOS tube (M10) and the source electrode of the eleventh CMOS tube (M11) are both grounded; the bias current control circuit 121 is configured to generate two bias currents according to an input voltage under control of a given bias voltage, wherein one bias current is supplied to a drain of the eleventh CMOS transistor (M11) and a drain of the ninth CMOS transistor (M7), and the other bias current is supplied to the correction current generation circuit 130.
Exemplarily, the bias current control circuit 121 includes a twelfth CMOS transistor (M8), a thirteenth CMOS transistor (M9), an operational amplifier (U1), and a bias voltage input terminal (Vbias); the source electrode of the twelfth CMOS tube (M8) and the source electrode of the thirteenth CMOS tube (M9) are both connected with a power supply; the inverting input end of the operational amplifier (U1) is connected with the bias voltage input end; the output end of the operational amplifier (U1) is respectively connected with the grid electrode of the twelfth CMOS tube (M8) and the grid electrode of the thirteenth CMOS tube (M9); the drain electrode of the twelfth CMOS tube (M8) is connected with the non-inverting input end of the operational amplifier (U1), and the drain electrode of the twelfth CMOS tube (M8) is connected with the drain electrode of the eleventh CMOS tube (M11) and the drain electrode of the ninth CMOS tube (M7) respectively; the drain of the thirteenth CMOS transistor (M9) is connected to the correction current generation circuit 130.
In the implementation process, a circuit composed of the seventh CMOS transistor (M5), the eighth CMOS transistor (M6) and the ninth CMOS transistor (M7) is a replica unit (replica in fig. 4) of a preamplifier in the ADC comparator, and the seventh CMOS transistor (M5) and the preamplifier use a common input voltage of a reference Voltage (VBCS), and operate at the same bias current, so that the circuit has the same transconductance (gm) as the preamplifier in the comparator. Applying a small differential voltage to the differential pair input, a reference current Igm = gm (VRP-VRN) is obtained.
Referring to fig. 5, fig. 5 is a schematic diagram of a calibration current generating circuit according to an embodiment of the invention.
In one implementation, the correction current generation circuit 130 provided by the embodiment of the present invention includes a first correction current output terminal (ICALN), a second correction current output terminal (ICALP), a fourteenth CMOS transistor (M12), a fifteenth CMOS transistor (M13), a sixteenth CMOS transistor (M14), a seventeenth CMOS transistor (M15), an eighteenth CMOS transistor (M16), a first tunable CMOS transistor (ADJN), and a second tunable CMOS transistor (ADJP); the drain and the gate of the fourteenth CMOS transistor (M12), the gate of the first adjustable CMOS transistor (ADJN), and the gate of the second adjustable CMOS transistor (adjjp) are all connected to the bias current generating circuit 120; the source electrode of the first adjustable CMOS tube (ADJN), the source electrode of the fourteenth CMOS tube (M12) and the source electrode of the second adjustable CMOS tube (ADJP) are all grounded; the drain electrode and the grid electrode of the fifteenth CMOS tube (M13) and the grid electrode of the sixteenth CMOS tube (M14) are connected with the drain electrode of the first adjustable CMOS tube (ADJN); the drain electrode of the sixteenth CMOS tube (M14) is connected with the first correction current output end; the drain electrode and the grid electrode of the seventeenth CMOS tube (M15) and the grid electrode of the eighteenth CMOS tube (M16) are connected with the drain electrode of the second adjustable CMOS tube (ADJP); the drain electrode of the eighteenth CMOS tube (M16) is connected with the second correction current output end; the source electrode of the fifteenth CMOS transistor (M13), the source electrode of the sixteenth CMOS transistor (M14), the source electrode of the seventeenth CMOS transistor (M15) and the source electrode of the eighteenth CMOS transistor (M16) are all connected with a power supply; meanwhile, the first adjustable CMOS transistor (ADJN) and the second adjustable CMOS transistor (ADJP) are both connected with the controller 140, and the number of the connected transistors of the first adjustable CMOS transistor (ADJN) and the second adjustable CMOS transistor (ADJP) can be controlled through the controller 140, so that the adjustment of the current proportion is realized.
In the implementation process, the correction current generation circuit 130 generates the correction currents through the first tunable CMOS transistor and the second tunable CMOS transistor respectively by using the Igm as a reference current. The differential current is injected into the input terminal of the preamplifier in the comparator to be used as compensation current to compensate the mismatch of the preamplifier.
Referring to fig. 6, fig. 6 is a schematic diagram of a topology structure of an analog-to-digital converter according to an embodiment of the invention.
As shown in fig. 6, in an implementation, an embodiment of the present invention further provides an analog-to-digital converter, which includes a plurality of cascaded integrators 200; a quantizer 300 connected to an output terminal of the last integrator 200, the quantizer 300 being a Flash ADC composed of a plurality of comparators; a plurality of digital-to-analog converters 400 connected to the output of the quantizer 300; an upper offset correction circuit 100 connected to the comparator; and adders 500 connected in one-to-one correspondence with the digital-to-analog converters 400; the adder 500 is used to integrate the output of the previous integrator and the output of the corresponding digital-to-analog converter 400 as the input of the next integrator.
In summary, the embodiment of the present invention provides an offset calibration circuit of a continuous-time ADC comparator and an analog-to-digital converter, including a bias voltage generation circuit, a bias current generation circuit, a calibration current generation circuit, and a controller; the controller is connected with the output end of the ADC comparator and used for acquiring the output of the ADC comparator; the bias current generating circuit is used for generating a pair of adjustable differential voltages under the control of the controller; the bias current generating circuit is connected with the bias voltage generating circuit and used for generating bias current under the control of the adjustable differential voltage; the correction current generation circuit is connected with the bias current generation circuit and used for generating corresponding correction current by taking the bias current as reference current under the control of the controller, and inputting the correction current into the input end of the preamplifier in the ADC comparator to be used as compensation current, so that the influence of temperature on offset voltage of the comparator is reduced, and the consistency of the linearity of the ADC at each temperature is improved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of the changes or substitutions within the technical scope of the present invention, and shall cover the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. An offset correction circuit of a continuous time ADC comparator is characterized by comprising a bias voltage generation circuit, a bias current generation circuit, a correction current generation circuit and a controller; the controller is connected with the output end of the ADC comparator and used for acquiring the output of the ADC comparator; the bias voltage generating circuit is used for generating a pair of adjustable differential voltages under the control of the controller; the bias current generating circuit is connected with the bias voltage generating circuit and used for generating bias current under the control of the adjustable differential voltage; the correction current generation circuit is connected with the bias current generation circuit and used for generating corresponding correction current by taking the bias current as reference current under the control of the controller and inputting the correction current into the input end of a preamplifier in the ADC comparator to be used as compensation current.
2. The offset correction circuit of claim 1 wherein the bias voltage generation circuit is an adjustable resistor ladder.
3. The offset correction circuit of claim 2 wherein the bias voltage generating circuit comprises a VRP output, a VRN output, a first regulating circuit, a second regulating circuit, a first resistor, a second resistor, and a third resistor; the first end of the first regulating circuit is connected with a power supply; the first end of the first resistor is connected with the second end of the first regulating circuit; the first end of the second resistor and the second end of the first resistor are both connected with the VRP output end; the first end of the second regulating circuit is grounded; the first end of the third resistor is connected with the second end of the second regulating circuit; and the second end of the third resistor and the second end of the second resistor are both connected with the VRN output end.
4. The offset correction circuit of claim 3, wherein the first regulation circuit comprises a first CMOS transistor, a second CMOS transistor, a third CMOS transistor, a fourth resistor, a fifth resistor, and a sixth resistor; the grid electrode of the first CMOS tube, the grid electrode of the second CMOS tube and the grid electrode of the third CMOS tube are all connected with a controller; the source electrode of the first CMOS tube, the source electrode of the second CMOS tube and the source electrode of the third CMOS tube are all connected with a power supply; the fourth resistor is connected between the source electrode and the drain electrode of the first CMOS tube; the fifth resistor is connected between the drain electrode of the first CMOS tube and the drain electrode of the second CMOS tube; the sixth resistor is connected between the drain electrode of the second CMOS tube and the drain electrode of the third CMOS tube, and the drain electrode of the third CMOS tube is connected with the first end of the first resistor.
5. The offset correction circuit of claim 3, wherein the second adjustment circuit comprises a fourth CMOS transistor, a fifth CMOS transistor, a sixth CMOS transistor, a seventh resistor, an eighth resistor, and a ninth resistor; the grid electrode of the fourth CMOS tube, the grid electrode of the fifth CMOS tube and the grid electrode of the sixth CMOS tube are all connected with a controller; the source electrode of the fourth CMOS tube, the source electrode of the fifth CMOS tube and the source electrode of the sixth CMOS tube are all grounded; the seventh resistor is connected between the source electrode and the drain electrode of the fourth CMOS tube; the eighth resistor is connected between the drain electrode of the fourth CMOS tube and the drain electrode of the fifth CMOS tube; the ninth resistor is connected between the drain electrode of the fifth CMOS tube and the drain electrode of the sixth CMOS tube, and the drain electrode of the sixth CMOS tube is connected with the first end of the third resistor.
6. The offset correction circuit of claim 3, wherein the bias current generating circuit comprises a reference voltage input terminal, a seventh CMOS transistor, an eighth CMOS transistor, a ninth CMOS transistor, a tenth CMOS transistor, an eleventh CMOS transistor and a bias current control circuit; the grid electrode of the seventh CMOS tube is connected with the reference voltage input end; the source electrode of the seventh CMOS tube is connected with a power supply; the source electrode of the eighth CMOS tube and the source electrode of the ninth CMOS tube are both connected with the drain electrode of the seventh CMOS tube; the grid electrode of the eighth CMOS tube is connected with the VRN output end; the grid electrode of the ninth CMOS tube is connected with the VRP output end; the drain electrode and the grid electrode of the tenth CMOS tube and the grid electrode of the eleventh CMOS tube are both connected with the drain electrode of the eighth CMOS tube; the source electrode of the tenth CMOS tube and the source electrode of the eleventh CMOS tube are both grounded; the bias current control circuit is used for generating two paths of bias currents according to input voltage under the control of given bias voltage, wherein one path of bias current is transmitted to the drain electrode of the eleventh CMOS tube and the drain electrode of the ninth CMOS tube, and the other path of bias current is transmitted to the correction current generation circuit.
7. The offset correction circuit of claim 6, wherein the bias current control circuit comprises a twelfth CMOS transistor, a thirteenth CMOS transistor, an operational amplifier and a bias voltage input terminal; the source electrode of the twelfth CMOS tube and the source electrode of the thirteenth CMOS tube are both connected with a power supply; the inverting input end of the operational amplifier is connected with the bias voltage input end; the output end of the operational amplifier is respectively connected with the grid electrode of the twelfth CMOS tube and the grid electrode of the thirteenth CMOS tube; the drain electrode of the twelfth CMOS tube is connected with the non-inverting input end of the operational amplifier, and meanwhile, the drain electrode of the twelfth CMOS tube is respectively connected with the drain electrode of the eleventh CMOS tube and the drain electrode of the ninth CMOS tube; and the drain electrode of the thirteenth CMOS tube is connected with the correction current generating circuit.
8. The offset correction circuit of claim 1, wherein the correction current generation circuit comprises a first correction current output terminal, a second correction current output terminal, a fourteenth CMOS transistor, a fifteenth CMOS transistor, a sixteenth CMOS transistor, a seventeenth CMOS transistor, an eighteenth CMOS transistor, a first tunable CMOS transistor and a second tunable CMOS transistor; the drain electrode and the grid electrode of the fourteenth CMOS tube, the grid electrode of the first adjustable CMOS tube and the grid electrode of the second adjustable CMOS tube are connected with the bias current generating circuit; the source electrode of the first adjustable CMOS tube, the source electrode of the fourteenth CMOS tube and the source electrode of the second adjustable CMOS tube are all grounded; the drain electrode and the grid electrode of the fifteenth CMOS tube and the grid electrode of the sixteenth CMOS tube are connected with the drain electrode of the first adjustable CMOS tube; the drain electrode of the sixteenth CMOS tube is connected with the first correction current output end; the drain electrode and the grid electrode of the seventeenth CMOS tube and the grid electrode of the eighteenth CMOS tube are connected with the drain electrode of the second adjustable CMOS tube; the drain electrode of the eighteenth CMOS tube is connected with the second correction current output end; the source electrode of the fifteenth CMOS tube, the source electrode of the sixteenth CMOS tube, the source electrode of the seventeenth CMOS tube and the source electrode of the eighteenth CMOS tube are all connected with a power supply; meanwhile, the first adjustable CMOS tube and the second adjustable CMOS tube are both connected with the controller.
9. An analog-to-digital converter is characterized by comprising a plurality of cascaded integrators; the quantizer is connected with the output end of the last stage integrator and is a Flash ADC (analog to digital converter) consisting of a plurality of comparators; the digital-to-analog converters are connected with the output end of the quantizer; the offset correction circuit of any of claims 1-8 connected to the comparator; the summators are connected with the digital-to-analog converters in a one-to-one correspondence manner; and the adder is used for integrating the output of the previous-stage integrator and the output of the corresponding digital-to-analog converter and then taking the integrated output as the input of the next-stage integrator.
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