CN117826562A

CN117826562A - High-precision digital time converter circuit with calibration loop

Info

Publication number: CN117826562A
Application number: CN202410117481.8A
Authority: CN
Inventors: 刘马良; 赵天博; 罗朋
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2024-01-26
Filing date: 2024-01-26
Publication date: 2024-04-05

Abstract

The invention discloses a high-precision digital time converter circuit with a calibration loop, which comprises: a pulse generation circuit and a calibration loop; wherein the pulse generating circuit includes: a sub-digital time converter dtc_1, a sub-digital time converter dtc_2, and a D flip-flop; the calibration loop includes: charge pumps and loop filters. The pulse generation circuit is based on two chargeable constant slope sub-digital time converters and a D trigger, and can generate a pulse signal CLK_S with a speed of 100M and a duty ratio of 25%; the calibration loop outputs a calibration signal VCTRL by using a charge pump and a loop filter, adjusts the pulse width of the pulse signal CLK_S to be equal to the pulse width of the reference signal CLK_REF, and outputs an adjusted pulse signal CLK_S; the whole pulse signal is subjected to phase shift by changing an external control code, so that a phase-locked loop circuit in the traditional technology is omitted; the power consumption and the area of the circuit are reduced, and meanwhile, higher precision is ensured, and the cost is reduced.

Description

High-precision digital time converter circuit with calibration loop

Technical Field

The invention belongs to the field of mixed signal integrated circuit design, and particularly relates to a high-precision digital time converter circuit with a calibration loop.

Background

UWB (Ultra Wide Band) radar is a radar technology that uses Ultra wideband signals for detection and imaging. The method has the advantages of high resolution, low power consumption, interference resistance and the like, and is widely applied to the fields of military, safety, industry, medical treatment and the like. The equivalent time sampling structure enables the sampling rate which is multiple times of the sampling clock to be realized by utilizing the multiphase clock for sampling and then synthesizing, and the equivalent time sampling structure can be applied to a direct radio frequency sampling system.

In addition, UWB radar is beginning to enter the IOT (Internet of Things ) field widely, and higher requirements are put on the overall power consumption of the receiver chip. The traditional multiphase clock is generated by a phase-locked loop circuit, and the clock quality is guaranteed, but the power consumption is large, the area is large, and the traditional multiphase clock is not suitable for the scene of low power consumption and low cost.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a high-precision digital-to-time converter circuit with a calibration loop. The technical problems to be solved by the invention are realized by the following technical scheme:

a high precision digital-to-time converter circuit with a calibration loop, comprising: a pulse generation circuit and a calibration loop; wherein,

The pulse generation circuit includes: a sub-digital time converter dtc_1, a sub-digital time converter dtc_2, and a D flip-flop;

the sub-digital time converter dtc_1 and the sub-digital time converter dtc_2 process an external control code and a first reference signal CLK to generate a signal DTC1 and a signal DTC2, respectively;

the D trigger generates a pulse signal CLK_S according to the signal DTC1 and the signal DTC2;

phase shifting the rising edge of the pulse signal clk_s by changing the external control code;

the calibration loop includes: a charge pump and loop filter;

the charge pump compares the pulse signal CLK_S with a second reference signal CLK_REF, and generates a control signal for controlling the loop filter to charge or discharge according to a comparison result;

the loop filter outputs a calibration signal VCTRL to the pulse generating circuit according to the control signal, the calibration signal VCTRL adjusts the charging current of the pulse generating circuit so as to adjust the pulse width of the pulse signal clk_s to be equal to the pulse width of the second reference signal clk_ref, and outputs the adjusted pulse signal clk_s, thereby completing the conversion from the digital signal to the time signal.

In one embodiment of the invention, in the pulse generating circuit,

a first input end of the sub-digital time converter dtc_1 is connected to the first reference signal CLK, a second input end of the sub-digital time converter dtc_1 is connected to the external control code, a third input end of the sub-digital time converter dtc_1 is connected to the calibration signal VCTRL, and an output end of the sub-digital time converter dtc_1 is connected to a first input end of the D flip-flop;

a first input end of the sub-digital time converter dtc_2 is connected to the first reference signal CLK, a second input end of the sub-digital time converter dtc_2 is connected to the external control code, a third input end of the sub-digital time converter dtc_2 is connected to the calibration signal VCTRL, and an output end of the sub-digital time converter dtc_2 is connected to a second input end of the D flip-flop;

the output end of the D trigger is connected with the input end of the calibration loop.

In one embodiment of the present invention, the circuit structure of any one of the sub-digital time converter dtc_1 and the sub-digital time converter dtc_2 includes:

the device comprises a current source, a reset module, an adjusting module, a DAC capacitor array, a comparator and an OR gate; wherein,

A first input end of the current source is connected with a power supply voltage, a first control end VB1 of the current source is connected with the calibration signal VCTRL, a second control end VB2 of the current source is connected with an externally applied bias voltage, and an output end of the current source is connected with an input end of the reset module;

the control end of the reset module is connected with a reset signal CLK_R, and the output end of the reset module is connected with the first input end of the DAC capacitor array;

the first input end of the adjusting module is connected with an external control signal DAC_P, the second input end of the adjusting module is connected with an external control signal DAC_N, and the output end of the adjusting module is connected with the input end of the resetting module;

the second input end of the DAC capacitor array is connected with a reference voltage VREF, the third input end of the DAC capacitor array is grounded, and the output end of the DAC capacitor array is connected with the forward input end of the comparator;

the negative input end of the comparator is connected with an external fixed voltage VTH;

the first input end of the OR gate is connected with the signal CLK_OUT, the second input end of the OR gate is connected with the output end of the comparator, and the output end of the OR gate is used as the output end of the sub-digital time converter.

In one embodiment of the invention, the current source comprises: MOS tube M1 and MOS tube M2; wherein,

the source electrode of the MOS tube M1 is connected with the power supply voltage, the grid electrode of the MOS tube M1 is connected with the calibration signal VCTRL, and the drain electrode of the MOS tube M1 is connected with the source electrode of the MOS tube M2;

the grid electrode of the MOS tube M2 is connected with the externally applied bias voltage, and the drain electrode of the MOS tube M2 is connected with the input end of the reset module.

In one embodiment of the present invention, the reset module includes: MOS tube M3, MOS tube M4, first switch; wherein,

the source electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M2, the grid electrode of the MOS tube M3 is connected with the reset signal CLK_R, and the drain electrode of the MOS tube M3 is connected with the drain electrode of the MOS tube M4;

the source electrode of the MOS tube M4 is grounded, and the grid electrode of the MOS tube M4 is connected with the reset signal CLK_R;

the first control end of the first switch is connected to the reset signal CLK_R, the second control end of the first switch is connected to the reverse signal CLK_RN of the reset signal CLK_R, the first end of the first switch is connected with the source electrode of the MOS tube M3, and the second end of the first switch is grounded.

In one embodiment of the invention, the regulation module includes 15 identical CURRENT regulation units CURRENT CELL; the 15 identical CURRENT regulating units CURRENT CELL are connected with each other in a parallel mode; the circuit structure of any one of the 15 identical CURRENT regulation units CURRENT CELL comprises:

The second switch, the third switch, the MOS tube M5, the MOS tube M6, the MOS tube M7 and the MOS tube M8; wherein,

a first control end of the second switch is connected to the external control signal DAC_P, a second control end of the second switch is connected to the external control signal DAC_N, a first end of the second switch is connected to the calibration signal VCTRL, and a second end of the second switch is connected with a drain electrode of the MOS tube M5;

a first control end of the third switch is connected with the external control signal DAC_P, a second control end of the third switch is connected with the external control signal DAC_N, a first end of the third switch is connected with the externally applied bias voltage, and a second end of the third switch is connected with a drain electrode of the MOS tube M7;

the source electrode of the MOS tube M5 is connected with the power supply voltage, the grid electrode of the MOS tube M5 is connected with the external control signal DAC_P, and the drain electrode of the MOS tube M5 is connected with the grid electrode of the MOS tube M6;

the source electrode of the MOS tube M6 is connected with the power supply voltage, and the drain electrode of the MOS tube M6 is connected with the source electrode of the MOS tube M8;

the source electrode of the MOS tube M7 is connected with the power supply voltage, the grid electrode of the MOS tube M7 is connected with the external control signal DAC_P, and the drain electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8;

The drain electrode of the MOS tube M8 is connected with the source electrode of the MOS tube M3.

In one embodiment of the invention, a DAC capacitive array includes:

a first capacitor C0, a second capacitor C1, a third capacitor C2, a fourth capacitor C3, a fifth capacitor C4, a sixth capacitor C5, a seventh capacitor C6, an eighth capacitor C7, a ninth capacitor C8, a tenth capacitor C9, a first switch S0, a second switch S1, a third switch S2, a fourth switch S3, a fifth switch S4, a sixth switch S5, a seventh switch S6, an eighth switch S7, a ninth switch S8, and a tenth switch S9; wherein,

a first end of the first capacitor C0 is connected with a positive input end of the comparator, and a second end of the first capacitor C0 is connected with a first end of the first switch S0;

a first end of the second capacitor C1 is connected to a first end of the first capacitor C0, and a second end of the second capacitor C1 is connected to a first end of the second switch S1;

the first end of the third capacitor C2 is connected to the first end of the second capacitor C1, and the second end of the third capacitor C2 is connected to the first end of the third switch S2;

the first end of the fourth capacitor C3 is connected to the first end of the third capacitor C2, and the second end of the fourth capacitor C3 is connected to the first end of the fourth switch S3;

A first end of the fifth capacitor C4 is connected to a first end of the fourth capacitor C3, and a second end of the fifth capacitor C4 is connected to a first end of the fifth switch S4;

a first end of the sixth capacitor C5 is connected to a first end of the fifth capacitor C4, and a second end of the sixth capacitor C5 is connected to a first end of the sixth switch S5;

a first end of the seventh capacitor C6 is connected to a first end of the sixth capacitor C5, and a second end of the seventh capacitor C6 is connected to a first end of the seventh switch S6;

a first end of the eighth capacitor C7 is connected to a first end of the seventh capacitor C6, and a second end of the eighth capacitor C7 is connected to a first end of the eighth switch S7;

a first end of the ninth capacitor C8 is connected to a first end of the eighth capacitor C7, and a second end of the ninth capacitor C8 is connected to a first end of the ninth switch S8;

the first end of the tenth capacitor C9 is connected to the first end of the ninth capacitor C8, the first end of the tenth capacitor C9 is further connected to the drain of the MOS transistor M4, and the second end of the tenth capacitor C9 is connected to the first end of the tenth switch S9;

the second end of the first change-over switch S0 is connected to the reference voltage VREF, and the third end of the first change-over switch S0 is grounded;

A second end of the second change-over switch S1 is connected to the reference voltage VREF, and a third end of the second change-over switch S1 is grounded;

the second end of the third change-over switch S2 is connected to the reference voltage VREF, and the third end of the third change-over switch S2 is grounded;

a second end of the fourth switch S3 is connected to the reference voltage VREF, and a third end of the fourth switch S3 is grounded;

a second end of the fifth change-over switch S4 is connected to the reference voltage VREF, and a third end of the fifth change-over switch S4 is grounded;

a second end of the sixth change-over switch S5 is connected to the reference voltage VREF, and a third end of the sixth change-over switch S5 is grounded;

a second end of the seventh change-over switch S6 is connected to the reference voltage VREF, and a third end of the seventh change-over switch S6 is grounded;

a second end of the eighth switch S7 is connected to the reference voltage VREF, and a third end of the eighth switch S7 is grounded;

a second end of the ninth change-over switch S8 is connected to the reference voltage VREF, and a third end of the ninth change-over switch S8 is grounded;

a second end of the tenth switching switch S9 is connected to the reference voltage VREF, and a third end of the tenth switching switch S9 is grounded;

The first switch S0, the second switch S1, the third switch S2, the fourth switch S3, the fifth switch S4, the sixth switch S5, the seventh switch S6, the eighth switch S7, the ninth switch S8 and the tenth switch S9 are switched under the control of the external control code.

In one embodiment of the present invention, the operation of the D flip-flop generating the pulse signal clk_s according to the signal DTC1 and the signal DTC2 includes:

the D flip-flop generates the pulse signal clk_s by combining the rising edge of the signal DTC1 as the rising edge of the generated pulse signal clk_s and the rising edge of the signal DTC2 as the falling edge of the generated pulse signal clk_s.

In one embodiment of the present invention, a circuit structure of a charge pump includes:

MOS tube M9, MOS tube M10, MOS tube M11, MOS tube M12, MOS tube M13, MOS tube M14, MOS tube M15, MOS tube M16, MOS tube M17, MOS tube M18, MOS tube M19, MOS tube M20, MOS tube M21, MOS tube M22, MOS tube M23, first operational amplifier, second operational amplifier, fourth switch, fifth switch, sixth switch, seventh switch, P group CURRENT unit CURRENT CELL_P and N group CURRENT unit CURRENT CELL_N; wherein,

The source electrode of the MOS tube M9 is connected with the power supply voltage, the grid electrode of the MOS tube M9 is connected with the grid electrode of the MOS tube M10, and the drain electrode of the MOS tube M9 is connected with the source electrode of the MOS tube M10;

the drain electrode of the MOS tube M10 is connected with the grid electrode of the MOS tube M10;

the source electrode of the MOS tube M11 is connected with the power supply voltage, the grid electrode of the MOS tube M11 is connected with the grid electrode of the MOS tube M9, and the drain electrode of the MOS tube M11 is connected with the source electrode of the MOS tube M12;

the grid electrode of the MOS tube M12 is connected with the grid electrode of the MOS tube M10, and the drain electrode of the MOS tube M12 is connected with the non-inverting input end of the first operational amplifier;

the source electrode of the MOS tube M13 is connected with the power supply voltage, the grid electrode of the MOS tube M13 is connected with the grid electrode of the MOS tube M11, and the drain electrode of the MOS tube M13 is connected with the source electrode of the MOS tube M14;

the grid electrode of the MOS tube M14 is connected with the grid electrode of the MOS tube M12, and the drain electrode of the MOS tube M14 is connected with the first end of the fourth switch;

the source electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M16, the grid electrode of the MOS tube M15 is connected with the drain electrode of the MOS tube M15, and the drain electrode of the MOS tube M15 is connected with a signal IREF_50U;

the source electrode of the MOS tube M16 is grounded, and the grid electrode of the MOS tube M16 is connected with the grid electrode of the MOS tube M15;

The source electrode of the MOS tube M17 is grounded to the drain electrode of the MOS tube M18, the grid electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M15, and the drain electrode of the MOS tube M17 is connected with a signal IREF_50U_1;

the source electrode of the MOS tube M18 is grounded, and the grid electrode of the MOS tube M18 is connected with the drain electrode of the MOS tube M17;

the source electrode of the MOS tube M19 is grounded, the grid electrode of the MOS tube M19 is connected with the grid electrode of the MOS tube M18, and the drain electrode of the MOS tube M19 is connected with the drain electrode of the MOS tube M10;

the source electrode of the MOS tube M20 is connected with the drain electrode of the MOS tube M21, the grid electrode of the MOS tube M20 is connected with the grid electrode of the MOS tube M17, and the drain electrode of the MOS tube M20 is connected with the non-inverting input end of the first operational amplifier;

the source electrode of the MOS tube M21 is grounded, and the grid electrode of the MOS tube M21 is connected with the grid electrode of the MOS tube M19;

the source electrode of the MOS tube M22 is connected with the drain electrode of the MOS tube M23, the grid electrode of the MOS tube M22 is connected with the grid electrode of the MOS tube M20, and the drain electrode of the MOS tube M22 is connected with the second end of the fifth switch;

the source electrode of the MOS tube M23 is grounded, and the grid electrode of the MOS tube M23 is connected with the grid electrode of the MOS tube M21;

the inverting input end of the first operational amplifier is connected with the signal CP_OUT, and the output end of the first operational amplifier is connected with the grid electrode of the MOS tube M11;

The non-inverting input end of the second operational amplifier is connected with the second end of the sixth switch, the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier, and the output end of the second operational amplifier is connected with the second end of the fourth switch;

the first control end of the fourth switch is connected with a signal UP_N, the second control end of the fourth switch is connected with a signal UP_P, the first end of the fourth switch is connected with the first end of the sixth switch, and the second end of the fourth switch is connected with the first end of the fifth switch;

the first control end of the fifth switch is connected with a signal DN_N, the second control end of the fifth switch is connected with a signal DN_P, and the second end of the fifth switch is connected with the second end of the seventh switch;

a first control end of the sixth switch is connected to the signal UP_P, a second control end of the sixth switch is connected to the signal UP_N, and a second end of the sixth switch is connected to the signal CP_OUT;

a first control end of the seventh switch is connected to the signal DN_P, a second control end of the seventh switch is connected to the signal DN_N, and a first end of the seventh switch is connected with a second end of the sixth switch;

The first input end of the P group CURRENT unit CURRENT cell_P is connected with a signal CP_P, the second input end of the P group CURRENT unit CURRENT cell_P is connected with a signal CP_N, and the output end of the P group CURRENT unit CURRENT cell_P is connected with the first end of the fourth switch;

the first input end of the N groups of CURRENT units CURRENT CELL_N is connected with the signal CP_P, the second input end of the N groups of CURRENT units CURRENT CELL_N is connected with the signal CP_N, and the output end of the N groups of CURRENT units CURRENT CELL_N is connected with the second end of the fifth switch.

In one embodiment of the present invention, the charge pump compares the pulse signal clk_s with the second reference signal clk_ref, and generates a control signal for controlling the loop filter to charge or discharge according to the comparison result, comprising:

the charge pump converts the pulse signal clk_s into a differential signal as the signal up_n and the signal up_p;

the charge pump converts the second reference signal clk_ref into a differential signal as the signal dn_n and the signal dn_p;

when the signal UP_N and the signal UP_P are at a high level, generating a first control signal to control the loop filter to charge;

When the signal DN_N and the signal DN_P are at a high level, a second control signal is generated to control the loop filter to discharge.

The invention has the beneficial effects that:

in the scheme provided by the embodiment of the invention, the signals DTC1 and DTC2 generated by the two sub-digital time converters are combined through the D trigger to generate the pulse signal CLK_S, and the error caused by the change of the turning point is reduced through the structure; comparing the pulse signal CLK_S with the second reference signal CLK_REF by adopting a charge pump, generating a control signal according to a comparison result to adjust the voltage of a loop filter, and outputting a calibration signal VCTRL by the loop filter to adjust the pulse width of the pulse signal CLK_S so that the pulse width of the pulse signal CLK_S is equal to the pulse width of the second reference signal CLK_REF; the phase shift of the whole pulse signal is realized by changing the external control code, so that a phase-locked loop circuit in the traditional technology is omitted; the power consumption and the area of the circuit are reduced, and meanwhile, higher precision is ensured, and the cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a high-precision digital-to-time converter circuit with a calibration loop according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a sub-time digitizer of a high precision digitizer circuit with a calibration loop according to an embodiment of the present invention;

FIG. 3 is a timing diagram of the operation of a sub-time digitizer of a high precision digitizer circuit with a calibration loop according to an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a charge pump with a calibration loop high-precision digital-to-time converter circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram of the operation of a high-precision digital-to-time converter circuit with a calibration loop according to an embodiment of the present invention;

fig. 6 is a diagram of a loop locking process when clk_s and clk_ref pulse widths are different for a high-precision digital-to-time converter circuit with a calibration loop according to an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

An embodiment of the present invention provides a high-precision digital-to-time converter circuit with a calibration loop, as shown in fig. 1, which may include:

a pulse generation circuit and a calibration loop; wherein,

the sub-digital time converter dtc_1 and the sub-digital time converter dtc_2 process the external control code and the first reference signal CLK to generate a signal DTC1 and a signal DTC2, respectively;

the rising edge of the pulse signal CLK_S is subjected to phase shift by changing an external control code;

the calibration loop includes: a charge pump and loop filter;

the charge pump compares the pulse signal CLK_S with the second reference signal CLK_REF, and generates a control signal for controlling the loop filter to charge or discharge according to the comparison result;

the loop filter outputs a calibration signal VCTRL to the pulse generating circuit according to the control signal, the calibration signal VCTRL adjusts the charging current of the pulse generating circuit to adjust the pulse width of the pulse signal clk_s to be equal to the pulse width of the second reference signal clk_ref, and outputs the adjusted pulse signal clk_s to complete the conversion from the digital signal to the time signal.

In the high-precision digital time converter circuit provided by the embodiment of the invention, the signals DTC1 and DTC2 generated by the two sub-digital time converters are combined through the D trigger to generate the pulse signal CLK_S, and the error caused by the change of the turning point is reduced through the structure; comparing the pulse signal CLK_S with the second reference signal CLK_REF by adopting a charge pump, generating a control signal according to a comparison result to adjust the voltage of a loop filter, and outputting a calibration signal VCTRL by the loop filter to adjust the pulse width of the pulse signal CLK_S so that the pulse width of the pulse signal CLK_S is equal to the pulse width of the second reference signal CLK_REF; the phase-locked loop circuit in the traditional technology is omitted by changing the external control code pair so as to enable the whole of the pulse signal to be phase-shifted.

For ease of understanding, the following description of the various blocks in the high-precision digital-to-time converter circuit set forth in embodiments of the present invention is provided.

Pulse generating circuit

The pulse generating circuit may include: the sub-digital time converter dtc_1, the sub-digital time converter dtc_2 and the D flip-flop.

Specifically, in the pulse generating circuit,

a first input end of the sub-digital time converter DTC_1 is connected with a first reference signal CLK, a second input end of the sub-digital time converter DTC_1 is connected with an external control code, a third input end of the sub-digital time converter DTC_1 is connected with a calibration signal VCTRL, and an output end of the sub-digital time converter DTC_1 is connected with a first input end of a D trigger;

A first input end of the sub-digital time converter DTC_2 is connected with a first reference signal CLK, a second input end of the sub-digital time converter DTC_2 is connected with an external control code, a third input end of the sub-digital time converter DTC_2 is connected with a calibration signal VCTRL, and an output end of the sub-digital time converter DTC_2 is connected with a second input end of the D trigger;

the output of the D flip-flop is connected to the input of the calibration loop.

Sub-digital time converter dtc_1 and sub-digital time converter dtc_2

The circuit configuration of any one of the sub-digital time converter dtc_1 and the sub-digital time converter dtc_2, as shown in fig. 2, may include:

a first input end of the current source is connected with a power supply voltage, a first control end VB1 of the current source is connected with a calibration signal VCTRL, a second control end VB2 of the current source is connected with an externally applied bias voltage, and an output end of the current source is connected with an input end of the reset module;

The sub-digital time converter dtc_1 and the sub-digital time converter dtc_2 are two charged constant slope sub-digital time converters.

Specifically, the current source may include: MOS tube M1 and MOS tube M2; wherein,

the source electrode of the MOS tube M1 is connected with a power supply voltage, the grid electrode of the MOS tube M1 is connected with a calibration signal VCTRL, and the drain electrode of the MOS tube M1 is connected with the source electrode of the MOS tube M2;

the grid electrode of the MOS tube M2 is connected with an externally applied bias voltage, and the drain electrode of the MOS tube M2 is connected with the input end of the reset module.

The current source is a constant current source for providing a constant current to the DAC capacitive array in the sub-digital time converter.

Specifically, the reset module includes: MOS tube M3, MOS tube M4, first switch; wherein,

The source electrode of the MOS tube M4 is grounded, and the grid electrode of the MOS tube M4 is connected with a reset signal CLK_R;

the first control end of the first switch is connected with the reset signal CLK_R, the second control end of the first switch is connected with the reverse signal CLK_RN of the reset signal CLK_R, the first end of the first switch is connected with the source electrode of the MOS tube M3, and the second end of the first switch is grounded.

Referring to fig. 2, after the clock signal CLK is processed by the not gate and the DELAY module, the clock signal CLK is input into the and gate together with the clock signal CLK, and then the reset signal clk_r is output; the reset signal clk_r outputs the inverse signal clk_rn of the reset signal clk_r through the not gate.

The reset module resets the DAC capacitor array in the sub-digital time converter under the control of the reset signal CLK_R.

In particular, the regulation module may comprise 15 identical CURRENT regulation units CURRENT CELL; the 15 identical CURRENT regulating units CURRENT CELL are connected with each other in parallel; the circuit configuration of any one of the 15 identical CURRENT regulation units CURRENT CELL may include:

the first control end of the second switch is connected with an external control signal DAC_P, the second control end of the second switch is connected with an external control signal DAC_N, the first end of the second switch is connected with a calibration signal VCTRL, and the second end of the second switch is connected with the drain electrode of the MOS tube M5;

The first control end of the third switch is connected with an external control signal DAC_P, the second control end of the third switch is connected with an external control signal DAC_N, the first end of the third switch is connected with an externally applied bias voltage, and the second end of the third switch is connected with the drain electrode of the MOS tube M7;

the source electrode of the MOS tube M5 is connected with a power supply voltage, the grid electrode of the MOS tube M5 is connected with an external control signal DAC_P, and the drain electrode of the MOS tube M5 is connected with the grid electrode of the MOS tube M6;

the source electrode of the MOS tube M7 is connected with a power supply voltage, the grid electrode of the MOS tube M7 is connected with an external control signal DAC_P, and the drain electrode of the MOS tube M7 is connected with the grid electrode of the MOS tube M8;

In the CURRENT regulation unit CURRENT CELL of fig. 2, the external control signal dac_p is simplified to P and the external control signal dac_n is simplified to N due to the size of the picture.

In the regulating module, the CURRENTs of the 15 CURRENT regulating units CURRENT CELL are added, so that the added CURRENTs are equal to the output CURRENTs of the CURRENT sources; the CURRENTs of the 15 CURRENT adjusting units CURRENT CELL are adjusted through external control signals DAC_P and DAC_N, and then the output CURRENTs of the CURRENT sources are adjusted to adapt to different environments. When the external control signal dac_p is at a high level, the MOS transistor M5 and the MOS transistor M7 are turned on.

Specifically, the DAC capacitive array may include:

the first end of the second capacitor C1 is connected with the first end of the first capacitor C0, and the second end of the second capacitor C1 is connected with the first end of the second change-over switch S1;

the first end of the third capacitor C2 is connected with the first end of the second capacitor C1, and the second end of the third capacitor C2 is connected with the first end of the third change-over switch S2;

the first end of the fourth capacitor C3 is connected with the first end of the third capacitor C2, and the second end of the fourth capacitor C3 is connected with the first end of the fourth change-over switch S3;

the first end of the fifth capacitor C4 is connected with the first end of the fourth capacitor C3, and the second end of the fifth capacitor C4 is connected with the first end of the fifth change-over switch S4;

The first end of the sixth capacitor C5 is connected with the first end of the fifth capacitor C4, and the second end of the sixth capacitor C5 is connected with the first end of the sixth change-over switch S5;

the first end of the seventh capacitor C6 is connected with the first end of the sixth capacitor C5, and the second end of the seventh capacitor C6 is connected with the first end of the seventh change-over switch S6;

the first end of the eighth capacitor C7 is connected with the first end of the seventh capacitor C6, and the second end of the eighth capacitor C7 is connected with the first end of the eighth switch S7;

a first end of the ninth capacitor C8 is connected with a first end of the eighth capacitor C7, and a second end of the ninth capacitor C8 is connected with a first end of the ninth change-over switch S8;

the first end of the tenth capacitor C9 is connected with the first end of the ninth capacitor C8, the first end of the tenth capacitor C9 is also connected with the drain electrode of the MOS tube M4, and the second end of the tenth capacitor C9 is connected with the first end of the tenth change-over switch S9;

the second end of the first change-over switch S0 is connected with the reference voltage VREF, and the third end of the first change-over switch S0 is grounded;

the second end of the second change-over switch S1 is connected with the reference voltage VREF, and the third end of the second change-over switch S1 is grounded;

the second end of the third change-over switch S2 is connected with the reference voltage VREF, and the third end of the third change-over switch S2 is grounded;

The second end of the fourth change-over switch S3 is connected with the reference voltage VREF, and the third end of the fourth change-over switch S3 is grounded;

the second end of the fifth change-over switch S4 is connected with the reference voltage VREF, and the third end of the fifth change-over switch S4 is grounded;

the second end of the sixth change-over switch S5 is connected with the reference voltage VREF, and the third end of the sixth change-over switch S5 is grounded;

the second end of the seventh change-over switch S6 is connected with the reference voltage VREF, and the third end of the seventh change-over switch S6 is grounded;

the second end of the eighth transfer switch S7 is connected with the reference voltage VREF, and the third end of the eighth transfer switch S7 is grounded;

the second end of the ninth change-over switch S8 is connected with the reference voltage VREF, and the third end of the ninth change-over switch S8 is grounded;

the second end of the tenth switching switch S9 is connected with the reference voltage VREF, and the third end of the tenth switching switch S9 is grounded;

the first switch S0, the second switch S1, the third switch S2, the fourth switch S3, the fifth switch S4, the sixth switch S5, the seventh switch S6, the eighth switch S7, the ninth switch S8 and the tenth switch S9 are switched under the control of an external control code.

The external control code controls the output voltage DAC_OUT of the DAC capacitor array by controlling the first switch S0, the second switch S1, the third switch S2, the fourth switch S3, the fifth switch S4, the sixth switch S5, the seventh switch S6, the eighth switch S7, the ninth switch S8 and the tenth switch S9 in the DAC capacitor array to correspondingly switch, so that the output voltage DAC_OUT of the DAC capacitor array is controlled, after the output voltage of the DAC capacitor array is not changed, the DAC capacitor array is charged by the current source, and after a period of time, the output voltage DAC_OUT of the DAC capacitor array is charged to the turnover threshold value of the comparator, so that the output is turned over. The time required to reach the rollover threshold may be adjusted by adjusting the external control code.

By utilizing the combined structure of the constant current source and the DAC capacitor array, errors caused by change of the turning point can be reduced.

Comparator with a comparator circuit

The output voltage DAC_OUT of the DAC capacitor array is compared with the external fixed voltage VTH through the comparator, when the output voltage DAC_OUT of the DAC capacitor array reaches the inversion threshold value, the comparator inverts, and the output pulse is converted from low level to high level. The external fixed voltage VTH is a fixed value of 700 millivolts, which is chosen to be appropriate for both the DAC capacitive array and the comparator.

OR gate

The OR gate provided by the embodiment of the invention processes the output voltage DAC_OUT of the DAC capacitor array by introducing the signal CLK_OUT so as to achieve the aim of charge protection.

The initial output voltage of the DAC capacitor array is adjusted during reset through an external control code. When the reset is completed, the constant current source starts to charge the DAC capacitive array. When the output DAC_OUT of the DAC capacitor array reaches the inversion threshold of the comparator, the comparator inverts, the output pulse signal is converted from low level to high level, and when the rising edge of the next first reference signal CLK arrives, the pulse signal is reset to low level. Thus, by adjusting the external control code, the phase shift of the rising edge of the pulse signal can be realized.

Fig. 3 is a schematic diagram illustrating an operation timing diagram of the sub-time digitizer according to an embodiment of the present invention. In fig. 3, CLK is a first reference signal, the duty cycle of the first reference signal CLK is 50%, clk_r is a reset signal, clk_out is a signal clk_out introduced by an or gate in the sub-time digitizer, dac_out is an output voltage of the DAC capacitor array, com_out is an output signal of the comparator, and OUT is an output signal of the sub-time digitizer.

The sub-time digital converter provided by the embodiment of the invention adjusts the initial output voltage of the DAC capacitor array during resetting through an external digital control code. When the reset is completed, the constant current source starts to charge the DAC capacitive array. When the output voltage DAC_OUT of the DAC capacitor array reaches the inversion threshold of the comparator, the comparator is inverted, the output pulse is converted from low level to high level, and when the next rising edge of the first reference signal CLK arrives, the pulse signal is reset to low level. Thus, by adjusting the external control code, the time required for reaching the inversion threshold is adjusted, and the phase shift of the rising edge of the pulse signal can be realized.

D trigger

The D flip-flop generates the pulse signal clk_s from the signal DTC1 and the signal DTC 2.

Specifically, the working process of the D flip-flop generating the pulse signal clk_s according to the signal DTC1 and the signal DTC2 includes:

Since the sub-time digitizer can only adjust the rising edge of the pulse signal. It is therefore necessary to combine the rising edges of both signals into one pulse signal by the D flip-flop, i.e. the rising edge of the signal DTC1 as the rising edge of the pulse signal clk_s and the rising edge of the signal DTC2 as the falling edge of the pulse signal clk_s. And then generates a pulse signal clk_s with a duty ratio of 25% and a speed of 100M, which can be phase-shifted with 10-bit precision, and the pulse width of the pulse signal clk_s is 2.5ns. The difference value of the two sub-time digital converter control codes can control the final pulse width, and on the premise of keeping the difference value, the two groups of control codes are added and subtracted at the same time, so that the integral phase shift of the pulse can be realized. Since the 10 bits of the sub-time digitizer correspond to a time length of 10ns, the control codes of the two sub-time digitizers are set to be 256 different, so that the pulse width is 2.5ns.

The pulse generating circuit provided by the embodiment of the invention can generate a pulse signal CLK_S with a speed of 100M and a duty ratio of 25% on the basis of two chargeable constant-slope sub-digital time converters and a D trigger.

Calibration loop

The calibration loop includes: charge pumps and loop filters.

Charge pump

Specifically, the circuit structure of the charge pump, as shown in fig. 4, may include:

the source electrode of the MOS tube M17 is grounded to the drain electrode of the MOS tube M18, the grid electrode of the MOS tube M17 is connected with the drain electrode of the MOS tube M15, and the drain electrode of the MOS tube M17 is connected with the signal IREF_50U_1;

the first control end of the fourth switch is connected with the signal UP_N, the second control end of the fourth switch is connected with the signal UP_P, the first end of the fourth switch is connected with the first end of the sixth switch, and the second end of the fourth switch is connected with the first end of the fifth switch;

the first control end of the sixth switch is connected with a signal UP_P, the second control end of the sixth switch is connected with a signal UP_N, and the second end of the sixth switch is connected with a signal CP_OUT;

The first control end of the seventh switch is connected with a signal DN_P, the second control end of the seventh switch is connected with a signal DN_N, and the first end of the seventh switch is connected with the second end of the sixth switch;

Specifically, the operation of the charge pump for comparing the pulse signal clk_s with the second reference signal clk_ref and generating a control signal for controlling the charge or discharge of the loop filter according to the comparison result may include:

the charge pump converts the pulse signal clk_s into a differential signal as a signal up_n and a signal up_p;

the charge pump converts the second reference signal clk_ref into a differential signal as a signal dn_n and a signal dn_p;

When the signals DN_N and DN_P are high, the second control signal is generated to control the loop filter to discharge.

In the charge pump circuit, a signal UP_N and a signal UP_P are connected into a charging current source switch formed by a fourth switch and a sixth switch, and a subsequent loop filter is subjected to current charging; and connecting the signal DN_N and the signal DN_P into a bleeder current source switch consisting of a fifth switch and a seventh switch, and performing current discharge on the subsequent loop filter. The magnitude of the two current sources is equal, and the length of the charging time will determine the rise or fall of the subsequent calibration signal VCTRL. The circuit is sensitive to size matching with the upper and lower current sources because the circuit does not introduce a phase frequency detector circuit in a traditional locked loop and does not perform a difference operation on the two signals. In the design process, the difference of upper and lower current sources is reduced by adding two clamping operational amplifiers, increasing the size of a current source tube, adopting a voltage insensitive common-source common-gate structure and other measures, and finally, the current precision within 1% can be ensured.

Loop filter

The loop filter outputs a calibration signal VCTRL to the pulse generating circuit according to the control signal, the calibration signal VCTRL adjusts the phases of the rising edges of the pulses of the signals DTC1 and DTC2 to adjust the pulse width of the pulse signal clk_s to be equal to the pulse width of the second reference signal clk_ref, and outputs the adjusted pulse signal clk_s to complete the conversion from the digital signal to the time signal.

The calibration loop provided by the embodiment of the invention utilizes the charge pump and the loop filter to output the calibration signal VCTRL, adjusts the pulse width of the pulse signal CLK_S to be equal to the pulse width of the reference signal CLK_REF, and outputs the adjusted pulse signal CLK_S. The duty cycle of the first reference signal CLK is 50% and the duty cycle of the second reference signal clk_ref is 25%.

Referring to fig. 5, CLK is a first reference signal, dac_1 is an output signal of a DAC capacitor array in a digital-to-analog time converter dtc_1, dtc_1 is an output signal of a digital-to-analog time converter dtc_1, dac_2 is an output signal of a DAC capacitor array in a digital-to-analog time converter dtc_2, dtc_2 is an output signal of a digital-to-analog time converter dtc_2, and clk_s is a pulse signal clk_s output from a pulse generating circuit.

FIG. 6 is a diagram showing a loop locking process of the high-precision digital-to-time converter circuit according to the embodiment of the present invention when the pulse widths of the CLK_S and CLK_REF are different, as can be seen from the left diagram of FIG. 6, when the pulse width of the pulse signal CLK_S is different from the pulse width of the second reference signal CLK_REF; when the second reference signal clk_ref is at a high level and the pulse signal clk_s is at a low level, the signals up_n and up_p are at a high level, and the charge pump outputs a first control signal to control the loop filter to charge; when the second reference signal clk_ref is at a low level and the pulse signal clk_s is at a high level, the signals dn_n and dn_p are at a high level, and the charge pump outputs a second control signal to control the loop filter to discharge; when the second reference signal clk_ref is at a high level and the pulse signal clk_s is at a high level, the charge pump charge and discharge time is the same, and the loop filter does not perform charge and discharge.

To prevent errors caused by current source current variations at different processes, voltages and temperatures, a calibration loop is introduced; the generated pulse signal clk_s is compared with a second reference signal clk_ref of a standard duty ratio of 25% and a speed of 100M, which is externally given. The charge pump converts the pulse signal clk_s into a differential signal as a signal up_n and a signal up_p; converting the second reference signal clk_ref into a differential signal as a signal dn_n and a signal dn_p; and further controls the loop filter to charge or discharge. When the pulse widths of the two signals are different, the charge pump adjusts the voltage of the loop filter. The voltage is connected back to the constant current source of the sub-digital time converter as a calibration signal VCTRL, and the charging current is adjusted to adjust the pulse width of the pulse signal clk_s. When the pulse widths of the pulse signal clk_s and the second reference signal clk_ref are equal, the charge pump charge and discharge time is the same, the circuit completes calibration, and the pulse signal clk_s is output.

The calibration loop compares the generated pulse signal clk_s with the externally provided second reference signal clk_ref via the charge pump, and the generated calibration signal VCTRL is coupled to the control voltage of the current source of the sub-digital time converter. The two signals are respectively connected to the switches of the charge current source and the discharge current source of the charge pump, and the switch is opened when the level is high so as to charge and discharge. And when the pulse widths of the two are the same, the charge and discharge time is the same, the voltage of the loop filter is kept constant, and the loop calibration is considered to be completed. When the pulse widths are not equal, the charge pump charges or discharges so that the calibration signal VCTRL output from the loop filter increases or decreases. Thus, the current sources in the sub-digital time converter are controlled to output currents with different magnitudes, the pulse width of the pulse signal CLK_S is adjusted until the current sources are equal, and the adjusted pulse signal CLK_S is output.

In the scheme provided by the embodiment of the invention, the signals DTC1 and DTC2 generated by the two sub-digital time converters are combined through the D trigger to generate the pulse signal CLK_S, and the error caused by the change of the turning point is reduced through the structure; the charge pump is adopted to compare the pulse signal CLK_S with the second reference signal CLK_REF, a control signal is generated according to the comparison result to adjust the voltage of the loop filter, the loop filter outputs a calibration signal VCTRL to adjust the pulse width of the pulse signal CLK_S, so that the whole pulse signal is subjected to phase shift, and a phase-locked loop circuit in the traditional technology is omitted; the power consumption and the area of the circuit are reduced, and meanwhile, higher precision is ensured, and the cost is reduced.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A high precision digital-to-time converter circuit with a calibration loop, comprising: a pulse generation circuit and a calibration loop; wherein,

the calibration loop includes: a charge pump and loop filter;

2. A high precision digital time converter circuit with calibration loop as set forth in claim 1 wherein, in said pulse generating circuit,

3. The high-precision digital-to-time converter circuit with calibration loop according to claim 2, wherein the circuit configuration of any one of the sub-digital-to-time converter dtc_1 and the sub-digital-to-time converter dtc_2 comprises:

4. A high precision digital time converter circuit with calibration loop according to claim 3, wherein said current source comprises: MOS tube M1 and MOS tube M2; wherein,

5. The high precision digital time converter circuit with calibration loop of claim 4, wherein said reset module comprises: MOS tube M3, MOS tube M4, first switch; wherein,

6. The high precision digital time converter circuit with calibration loop of claim 5, wherein said regulation module comprises 15 identical CURRENT regulation units CURRENT CELL; the 15 identical CURRENT regulating units CURRENT CELL are connected with each other in a parallel mode; the circuit structure of any one of the 15 identical CURRENT regulation units CURRENT CELL comprises:

7. The high precision digital time converter circuit with calibration loop of claim 6, wherein said DAC capacitive array comprises:

8. The high-precision digital-to-time converter circuit with calibration loop of claim 7, wherein said D flip-flop generates a pulse signal clk_s based on said signal DTC1 and said signal DTC2, comprising:

9. The high precision digital time converter circuit with calibration loop of claim 8, wherein said charge pump circuit structure comprises:

10. The high-precision digital-to-time converter circuit with calibration loop of claim 9, wherein said charge pump compares said pulse signal clk_s with said second reference signal clk_ref and generates a control signal for controlling said loop filter to charge or discharge based on the comparison result, comprising: