CN109194328B - High-precision on-chip oscillator - Google Patents
High-precision on-chip oscillator Download PDFInfo
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- CN109194328B CN109194328B CN201811283014.3A CN201811283014A CN109194328B CN 109194328 B CN109194328 B CN 109194328B CN 201811283014 A CN201811283014 A CN 201811283014A CN 109194328 B CN109194328 B CN 109194328B
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- H—ELECTRICITY
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
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Abstract
The invention discloses a high-precision on-chip oscillator, which uses a switched capacitor equivalent resistance module, realizes on-chip resistance (namely equivalent impedance) by using oscillator clock output, and then realizes voltage-current conversion by using reference voltage to obtain current proportional to clock frequency, namely proportional current for short. And comparing the reference current with the proportional current, and dynamically adjusting the oscillation frequency of the initial clock signal of the clock oscillation module by utilizing negative feedback of a comparison result, thereby realizing high-precision on-chip clock output. The invention can reduce the area of the silicon chip, and reduce the cost and the power consumption of the chip while realizing the generation of high-precision clock signals.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a high-precision on-chip oscillator.
Background
On-chip oscillators are as ubiquitous as power supplies in electronic systems, and their importance is thought to be equivalent to power supplies, and find application in any product requiring a time-series signal. Therefore, research into on-chip oscillators has never been stopped.
Prior art "Krishnakumar Sundaresan,Keith C.Brouse,Kongpop U-Yen,Farrokh Ayazi,Phillip E.Allen.'A 7-MHz Process,Temperature and Supply Compensated Clock Oscillator in 0.25μm CMOS'" has studied a conventional relaxation oscillator whose clock cycle is made up of capacitor charge time, comparator delay, etc. Wherein the capacitor charge-discharge time is a major part of the clock cycle. In order to obtain stable charge and discharge time, accurate discrimination voltage and accurate charge current are required to ensure that the charge time does not change with power supply voltage and temperature, so that a stable on-chip clock signal is obtained. However, the conventional technology does not dynamically adjust the electrical parameters that determine the clock period according to the clock signal: and distinguishing the voltage and the charging current.
In chinese patent CN102882471a, CN102882471B, a feedback technique is used to convert the clock frequency into a voltage, and then the frequency control of the voltage-controlled oscillator is implemented by an integrating circuit. In the case of a fluidic oscillator, the integrated voltage output needs to be converted into a current to control the oscillation frequency of the ICO (I-controlled oscillator, fluidic oscillator). Since the output frequency is proportional to the absolute value of the voltage-controlled voltage or current, the voltage-to-current conversion in this technique, as well as the integrator reference input, requires the use of an accurate reference voltage. In addition, the ICO architecture also converts voltage to current once more, which increases cost and circuit complexity.
Disclosure of Invention
The invention aims to provide a high-precision on-chip oscillator which realizes high-precision on-chip clock output and simultaneously reduces the cost and the power consumption of a chip.
In order to solve the above technical problems, the present invention provides a high-precision on-chip oscillator, comprising:
the device comprises a voltage and current generation module, a clock signal processing module, a switched capacitor equivalent resistance module, a clock frequency-current conversion module, a current comparison module and a clock oscillation module;
The clock signal processing module generates a two-phase non-overlapping switching signal according to an initial clock signal of the clock oscillation module, the two-phase non-overlapping switching signal is transmitted to the switch capacitor equivalent resistance module to obtain equivalent impedance, the equivalent impedance is combined with a reference voltage generated by the voltage current generation module to obtain a proportional current at the clock frequency-current conversion module, the proportional current and the reference current generated by the voltage current generation module obtain a comparison result at the current comparison module, and the comparison result is used for controlling the oscillation frequency of the initial signal of the clock oscillation module in a negative feedback and dynamic mode.
Optionally, for the high-precision on-chip oscillator, the voltage-current generating module includes: the NMOS tube MNAT, the NMOS tube MNAT1, the source electrode of the NMOS tube MNAT0 is grounded, the drain electrode is connected with the grid electrode, the drain electrode is also connected to one end of a plurality of resistors connected in series, the other ends of the plurality of resistors connected in series are connected with power supply voltage, reference voltage is led out from one node in the resistor string, the source electrode of the NMOS tube MNAT1 is grounded, the grid electrode is connected with the grid electrode of the NMOS tube MNAT0, the grid electrode of the PMOS tube MP0 and the grid electrode of the PMOS tube MP1 are connected to the drain electrode of the NMOS tube MNAT1, the source electrode of the PMOS tube MP0 and the source electrode of the PMOS tube MP1 are connected with power supply voltage, the drain electrode of the PMOS tube MP0 is connected with the source electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are connected with first bias voltage, and the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the NMOS tube MNAT1, and thus reference current is led out from the drain electrode of the PMOS tube MP 3.
Optionally, for the high-precision on-chip oscillator, the clock signal processing module generates an output clock signal with a duty cycle of 50%, and generates the two-phase non-overlapping clock switching signal according to the output clock signal.
Optionally, for the high-precision on-chip oscillator, the clock signal processing module includes a clock duty cycle adjusting module and a non-overlapping switching signal generating module, where the clock duty cycle adjusting module generates an output clock signal with a duty cycle of 50%, and the non-overlapping switching signal generating module generates the two-phase non-overlapping clock switching signal according to the output clock signal.
Optionally, for the high-precision on-chip oscillator, the switched capacitor equivalent resistance module includes a first terminal, a second terminal, an NMOS transistor MN0, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a first capacitor and a second capacitor; the drain electrode of the NMOS tube MN0 and the drain electrode of the NMOS tube MN1 are connected to the first terminal, the source electrode of the NMOS tube MN0, the drain electrode of the NMOS tube MN2 and one end of the first capacitor are connected, the source electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN3 and one end of the second capacitor are connected, the source electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN3, the other end of the first capacitor and the other end of the second capacitor are connected to the second terminal, the grid electrode of the NMOS tube MN0 and the grid electrode of the NMOS tube MN3 are connected with one phase clock switch signal, and the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 are connected with the other phase clock switch signal.
Optionally, for the high-precision on-chip oscillator, the oscillation frequency is f clk, the period is T clk, the capacitance values of the first capacitor and the second capacitor are both C s, the on time of the two-phase non-overlapping clock switch signal is T clk/2, the charge amount is Q, the current is I, the reference voltage is V ref, and then the equivalent impedance Z between the first terminal and the second terminal is calculated as follows:
Q＝CS*Vref，
Optionally, for the high-precision on-chip oscillator, the clock frequency-current conversion module includes an NMOS tube MN4, a PMOS tube MP5, an amplifier, and a switched capacitor equivalent resistor, where a gate of the NMOS tube MN4 is connected to an output end of the amplifier, a source of the NMOS tube MN4 is connected to a negative input end of the amplifier and one end of the switched capacitor equivalent resistor, another end of the switched capacitor equivalent resistor is grounded, the two-phase non-overlapping clock switching signal is applied to the negative input end of the amplifier through the switched capacitor equivalent resistor, a positive input end of the amplifier is connected to a reference voltage V ref generated by the voltage-current generation module, a drain of the NMOS tube MN4 is connected to a drain and a gate of the PMOS tube MP4, a source of the PMOS tube MP4 is connected to a power supply voltage, a gate of the PMOS tube MP4 is also connected to a gate of the PMOS tube MP5, and a source of the PMOS tube MP5 is connected to a power supply voltage, and the proportional current is output; then there is
Wherein I clk is the proportional current.
Optionally, for the high-precision on-chip oscillator, the current comparison module includes an NMOS tube MN5, an NMOS tube MN6, an NMOS tube MN7, an NMOS tube MN8, an NMOS tube MN9, a PMOS tube MP6, and a PMOS tube MP7, a drain of the NMOS tube MN7 is connected to a bias current, a source of the NMOS tube MN5 is connected to a drain of the NMOS tube MN6, a gate of the NMOS tube MN5 is connected to a drain of the NMOS tube MN6, a second bias voltage of the gate of the NMOS tube MN6 is generated, a source of the NMOS tube MN6 is grounded, a drain of the NMOS tube MN7 is connected to a reference current, a gate of the NMOS tube MN7 is connected to a drain of the NMOS tube MN7, a source of the NMOS tube MN8 is grounded, a drain of the NMOS tube MN8 is connected to a source of the NMOS tube MN9, a gate of the NMOS tube MN9 is connected to an NMOS bias voltage, a drain of the PMOS tube MP 9 is connected to a drain of the PMOS tube MP7, and a drain of the PMOS tube MP7 is connected to a drain of the NMOS tube MP7, and the drain of the NMOS tube MN7 is connected to a bias current, and the drain of the NMOS tube MN7 is connected to the drain of the NMOS tube MN7, and the drain of the NMOS tube is connected to the PMOS tube MN 7.
Optionally, for the high-precision on-chip oscillator, the clock oscillation module includes N inverting amplifiers with sequentially connected input ends and output ends, N third capacitors, where the third capacitors are in one-to-one correspondence with the inverting amplifiers, one end of each third capacitor is connected to an output end of a corresponding one of the inverting amplifiers, the other end of each third capacitor is grounded, the output end of the nth inverting amplifier is connected to an input end of a nand gate, the other input end of the nand gate is enabled, the output end of the nand gate generates the initial signal, one bias end of each inverting amplifier is connected to a third bias voltage, and the other bias end of each inverting amplifier is connected to a fourth bias voltage.
Alternatively, for the high precision on-chip oscillator,
Iclk＝K0*Iref，Vref＝K2*R*Iref，
Iclk＝2Cs*fckl*Vref,
K0*Iref＝2Cs*fclk*K2*R*Iref,
Where K 0、K1、K2 is a constant, VDD is the supply voltage, and R is a resistor.
In the high-precision on-chip oscillator provided by the invention, the switch capacitor equivalent resistance module is used, the on-chip resistance is realized by using the clock output of the oscillator (namely equivalent impedance is obtained), then voltage-current conversion is realized by using the reference voltage, the current proportional to the clock frequency is obtained, the proportional current is simply called, the reference current is compared with the proportional current, and the oscillation frequency of an initial clock signal of the clock oscillation module is dynamically adjusted by using the negative feedback of the comparison result, so that the high-precision on-chip clock output is realized.
The invention eliminates the requirement of the traditional high-precision on-chip oscillator on high-precision band-gap reference voltage and high-precision reference current, so that a band-gap reference source is not needed, the area of a silicon wafer can be reduced, the large static power consumption of a corresponding structure is also eliminated, the high-precision clock signal generation is realized, and the cost and the power consumption of a chip are reduced.
Drawings
FIG. 1 is a schematic diagram of a reference voltage and reference current generating module in the prior art;
FIG. 2 is a schematic diagram of a high-precision on-chip oscillator according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a voltage-current generating module according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a clock signal processing module according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a switched capacitor equivalent resistance module according to an embodiment of the invention;
FIG. 6 is a schematic diagram of a clock-to-current conversion module according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a current comparison module according to an embodiment of the invention;
fig. 8 is a schematic diagram of a clock oscillation module according to an embodiment of the invention.
Detailed Description
The high precision on-chip oscillator of the present invention will be described in more detail below in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art could modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Fig. 1 shows a schematic diagram of a reference voltage and reference current generation module in the prior art. Comprises two triodes Q0 and Q1, the base electrode and collector electrode of the triodes are grounded, the emitter electrode of the triode Q0 is connected with the drain electrode of a PMOS tube T0 through two resistors R0 and R2 which are connected in series, the emitter electrode of the triode Q1 is connected with the source electrode of the PMOS tube T1 through a resistor R1, the reference voltage VREF is led out from the middle of the resistor R0 resistor string, and the reference current can be led out from the source electrode of the PMOS tube MP2 … … MP (n+2) respectively.
However, in order to obtain a relatively stable reference voltage and reference current, a clamp amplifier (clamp-amp) needs to be added, a positive input end is arranged between the resistor R0 and the resistor R1, a negative input end is arranged between the resistor R1 and the emitter of the triode Q1, and an output end is arranged at the grid electrode of the PMOS tube.
The inventor finds that the structure is bulky and complex, the power consumption is large, and the occupied area is large. To improve this situation, the present invention proposes a high-precision on-chip oscillator.
As shown in fig. 2, the high-precision on-chip oscillator of the embodiment of the present invention includes:
the device comprises a voltage and current generation module, a clock signal processing module, a switched capacitor equivalent resistance module, a clock frequency-current conversion module, a current comparison module and a clock oscillation module;
The clock signal processing module generates two-phase non-overlapping switching signals according to the initial signals of the clock oscillation module, the two-phase non-overlapping switching signals are transmitted to the switch capacitor equivalent resistance module to obtain equivalent impedance, the equivalent impedance is combined with the reference voltage generated by the voltage current generation module to obtain proportional current at the clock frequency-current conversion module, the proportional current and the reference current generated by the voltage current generation module obtain comparison results at the current comparison module, and the comparison results are used for negatively feeding back and dynamically adjusting the oscillation frequency of the initial clock signals of the clock oscillation module.
The invention mainly converts the output of the clock oscillation module into proportional current with corresponding proportion, and gives an error signal (namely a comparison result) to dynamically feed back and control and adjust the output clock frequency of the clock oscillation module through comparison with reference current.
The deviation in the process can be corrected by fine tuning the parameters of the device, and clock deviation and jitter caused by temperature and voltage are corrected in real time by dynamic monitoring and feedback of clock frequency in the invention, so that good clock precision is realized. The specific implementation scheme is as follows:
(1) Generating an output clock signal with a duty ratio of 50% by a clock signal processing module, and generating a two-phase non-overlapping clock switching signal by the output clock signal;
(2) The generated two-phase non-overlapping clock switch signals control the switch capacitor equivalent resistance module to realize the equivalent impedance of a switch capacitor related to clock frequency;
(3) The equivalent impedance is combined with the reference voltage generated by the voltage-current generation module and is applied to the clock frequency-current conversion module to generate a current signal related to the clock frequency, the current signal is called proportional current, the proportional current is compared with the reference current, and the generated error signal (namely the comparison result) dynamically controls the output clock frequency of the clock oscillation module in a feedback control mode. When the oscillation frequency increases, the equivalent impedance decreases, the corresponding proportional current increases, the proportional current is larger than the reference current, the output error signal level increases, and if the error signal controls the P-type device of the clock oscillation module, the oscillation frequency will decrease. And vice versa.
In summary, the error signal always negatively feedback dynamically adjusts the oscillation frequency of the output clock signal until the output error signal is close to 0, at which point the oscillation frequency is nearly perfectly close to the target clock frequency. When the disturbance factor affects the clock frequency balance again, the negative feedback will act again until the clock frequency is stable.
The practical test shows that the stability of the oscillation frequency is below 0.5%.
Moreover, as can be seen from the above description, the clamp amplifier as shown in fig. 1 is not required in the present invention, the actual occupied area can be reduced by 50% -75%, and the power consumption can be reduced by more than 50%. For example, if the switched capacitor equivalent resistance module adopts MIM capacitor or MOM capacitor, the switched capacitor equivalent resistance module can be realized by means of top metal or sub-top metal, without occupying extra chip cost.
The following illustrates the specific construction of the various modules of the invention, which can be flexibly adapted and modified by those skilled in the art based on the description below.
In the figures below, the reference numerals of the various devices are understood as conventional in the art, e.g. "MP x" may denote PMOS transistors, "x" is a number, e.g. R denotes resistance, etc.
As shown in fig. 3, in one embodiment of the present invention, the voltage and current generating module mainly includes: the NMOS tube MNAT, the NMOS tube MNAT, the source electrode of the NMOS tube MNAT is grounded, the drain electrode is connected to the gate electrode, and the drain electrode is further connected to one end of a plurality of resistors (n in the figure, n=1, 2,3 … …) connected in series, the plurality of resistors can be consistent, the other ends of the plurality of resistors connected in series are connected with a power supply voltage, voltage division is achieved through the resistors, the reference voltage V ref is led out from a node in the resistor string, and the node is adjustable according to actual requirements. The source of NMOS tube MNAT is grounded and the gate is connected to the gate of NMOS tube MNAT0, thereby mirroring. The grid electrode of the PMOS tube MP0 and the grid electrode of the PMOS tube MP1 are connected to the drain electrode of the NMOS tube MNAT, the source electrode of the PMOS tube MP0 and the source electrode of the PMOS tube MP1 are connected with the power supply voltage, the drain electrode of the PMOS tube MP0 is connected with the source electrode of the PMOS tube MP2, the drain electrode of the PMOS tube MP1 is connected with the source electrode of the PMOS tube MP3, the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are connected with the first bias voltage VCSP, and the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the NMOS tube MNAT1, so that the reference current I ref is led out from the drain electrode of the PMOS tube MP 3.
Therefore, the voltage and current generation module does not need a clamping amplifier, the voltage dividing resistance of the reference voltage and the reference current is only related to the proportion of the resistance and is irrelevant to the absolute value, and the resistance with smaller width can be used as long as the total area of the resistance meets the matching requirement.
In the invention, the clock signal processing module generates an output clock signal with a duty ratio of 50%, and generates the two-phase non-overlapping clock switching signal according to the output clock signal.
Specifically, referring to fig. 4, the clock signal processing module includes a clock duty ratio adjusting module and a non-overlapping switching signal generating module, where the clock duty ratio adjusting module generates an output clock signal with a duty ratio of 50%, and the non-overlapping switching signal generating module generates the two-phase non-overlapping clock switching signals Sw0 and Sw1 according to the output clock signal.
The specific structure of the clock signal processing module including the clock duty cycle adjustment module and the non-overlapping switching signal generation module is not illustrated herein, and one skilled in the art can easily provide a specific design structure in light of the above-mentioned needs.
Referring to fig. 5, in an embodiment of the present invention, the switched capacitor equivalent resistance module includes a first terminal a, a second terminal B, an NMOS transistor MN0, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a first capacitor C0 and a second capacitor C1; the drain electrode of the NMOS tube MN0 and the drain electrode of the NMOS tube MN1 are connected to the first terminal A, the source electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN2 and one end of the first capacitor C0 are connected, the source electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN3 and one end of the second capacitor C1 are connected, the source electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN3, the other end of the first capacitor C0 and the other end of the second capacitor C1 are connected to the second terminal B, the grid electrode of the NMOS tube MN0 and the grid electrode of the NMOS tube MN3 are connected with a phase clock switch signal Sw0, and the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 are connected with another phase clock switch signal Sw1.
Therefore, if the oscillation frequency is f clk, the period is T clk, the capacitance values of the first capacitor and the second capacitor are C s, the on time of the two-phase non-overlapping clock switch signal is T clk/2, the charge amount is Q, the current is I, and the reference voltage is V ref, the equivalent impedance Z between the first terminal and the second terminal is calculated as follows:
Q＝CS*Vref，
Next, referring to fig. 6, in an embodiment of the present invention, the clock frequency-current conversion module includes an NMOS transistor MN4, a PMOS transistor MP5, an amplifier AMP0, and a switch capacitor equivalent resistor R0, where the switch capacitor equivalent resistor R0 is, for example, an equivalent impedance of the switch capacitor equivalent resistor module shown in fig. 5, and has a value Z, the gate of the NMOS transistor MN4 is connected to the output end of the amplifier, the source of the NMOS transistor MN4 is connected to the negative input end of the amplifier MP0 and one end of the switch capacitor equivalent resistor R0, the other end of the switch capacitor equivalent resistor R0 is grounded, the two-phase non-overlapping clock switch signals Sw0, sw1 are applied to the negative input end of the amplifier AMP0 through the switch capacitor equivalent resistor R0, the positive input end of the amplifier AMP0 is connected to a reference voltage V ref generated by the voltage current generation module, the drain of the NMOS transistor MN4 is connected to the drain of the PMOS transistor MP4 and the gate of the PMOS transistor MP4, the source of the PMOS transistor MP4 is connected to the drain of the PMOS transistor MP 62, and the drain of the PMOS transistor MP5 is connected to the drain of the power supply voltage of the PMOS transistor MP 5; then there is
Next, referring to fig. 7, in an embodiment of the present invention, the current comparing module includes an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, an NMOS transistor MN9, a PMOS transistor MP6, and a PMOS transistor MP7, wherein a drain of the NMOS transistor MN7 is connected to a bias current I bias, a source of the NMOS transistor MN5 is connected to a drain of the NMOS transistor MN6, a gate of the NMOS transistor MN5 is connected to a drain of the NMOS transistor MN6, a second bias voltage VSCN (taking an N-type casode device as an example) is generated at a gate of the NMOS transistor MN6, a source of the NMOS transistor MN6 is grounded, a drain of the NMOS transistor MN7 is connected to a reference current I ref, a gate of the NMOS transistor MN7 is connected to a drain of the NMOS transistor MN7, a source of the NMOS transistor MN8 is grounded, a drain of the NMOS transistor MN8 is connected to a drain of the NMOS transistor MN9, a gate of the NMOS transistor MN9 is connected to a PMOS transistor MP 9, a drain of the PMOS transistor MP 9 is connected to a drain of the PMOS transistor MP7, and a drain of the PMOS transistor MP7 is connected to a drain of the NMOS transistor MP 7. Therefore, the comparison of the reference current I ref and the proportional current I clk is realized, and the third bias voltage VBP (taking a P-type structure as an example, namely, the bias voltage of the P-type current source) can be led out between the NMOS tube MN9 and the PMOS tube MP 6.
Referring to fig. 8, after the comparison result is obtained, a third bias voltage VBP may be applied to the ring oscillator, that is, in one embodiment of the present invention, the clock oscillation module includes N inverting amplifiers A1 with sequentially input ends and output ends connected, N third capacitors C3, where the third capacitors C3 are in one-to-one correspondence with the inverting amplifiers A1, one end of each third capacitor C3 is connected to the output end of a corresponding one of the inverting amplifiers A1, the other end of each third capacitor C3 is grounded, one bias end of each inverting amplifier A1 is connected to the third bias voltage VBP, the other bias end is connected to the fourth bias voltage VBN, the output end of the nth inverting amplifier A1 is connected to one input end of the nand gate G1, the other input end of each of the inverting amplifiers enables EN, and the output end of the nand gate generates the initial signal CLK.
Therefore, the generation of the oscillation clock signal can be realized, and the current control or voltage control can be adopted according to the requirements.
Specifically, the clock oscillation frequency may be expressed as follows:
Iclk＝K0*Iref，Vref＝K2*R*Iref，
Iclk＝2Cs*fckl*Vref,
K0*Iref＝2Cs*fclk*K2*R*Iref,
where K 0、K1、K2 is a constant and is related only to the current mirror ratio and device ratio of the line design, independent of the absolute value of the device parameters. VDD is a power supply voltage, and R is a resistance value.
In summary, in the high-precision on-chip oscillator provided by the invention, the on-chip resistor is realized by using the switched capacitor equivalent resistor module and utilizing the clock output of the oscillator (namely, equivalent impedance is obtained), then voltage-current conversion is realized by utilizing the reference voltage, current proportional to the clock frequency is obtained, the proportional current is simply referred to as proportional current, then the reference current is compared with the proportional current, and the oscillation frequency of the initial signal of the clock oscillation module is dynamically controlled by utilizing the negative feedback of the comparison result, so that the high-precision on-chip clock output is realized.
The invention eliminates the requirement of the traditional high-precision on-chip oscillator on high-precision band-gap reference voltage and high-precision reference current, so that a band-gap reference source is not needed, the area of a silicon wafer can be reduced, the large static power consumption of the traditional corresponding structure is also eliminated, and the cost and the power consumption of a chip are reduced while the generation of a high-precision clock signal is realized. Specifically, compared with the prior art, the design structure of the invention saves two comparators, saves the power consumption of the two comparators, and saves the power consumption of a complex reference system.
In addition, the invention can realize clock signals in a wide frequency range. The oscillator clock period realized by the invention is not dependent on the charging time of the capacitor, but is only related to the delay of the ring oscillator, which is very small, so that a clock signal with a very wide frequency can be realized.
The invention can also correct clock accuracy in a variety of ways: clock frequency correction can be achieved, for example, by correcting the size of the divider resistor, the switch capacitance, and the proportion of the mirror current.
The invention realizes the dynamic adjustment of the clock frequency by a real-time dynamic feedback technology, and improves the interference capability of the clock against external factors such as power supply voltage, temperature and the like.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (9)
1. A high precision on-chip oscillator, comprising:
the device comprises a voltage and current generation module, a clock signal processing module, a switched capacitor equivalent resistance module, a clock frequency-current conversion module, a current comparison module and a clock oscillation module;
The clock signal processing module generates a two-phase non-overlapping switching signal according to an initial clock signal of the clock oscillation module, the two-phase non-overlapping switching signal is transmitted to the switch capacitor equivalent resistance module to obtain equivalent impedance, the equivalent impedance is combined with a reference voltage generated by the voltage current generation module to obtain a proportional current at the clock frequency-current conversion module, the proportional current and the reference current generated by the voltage current generation module obtain a comparison result at the current comparison module, and the comparison result is used for controlling the oscillation frequency of the initial signal of the clock oscillation module in a negative feedback manner;
The switch capacitor equivalent resistance module comprises a first capacitor and a second capacitor, wherein the first capacitor and the second capacitor are symmetrically arranged, and a full duplex switch capacitor circuit is realized under the control of two-phase non-overlapping clock switch signals;
The oscillation frequency is f clk, the period is T clk, the capacitance values of the first capacitor and the second capacitor are C s, the on time of the two-phase non-overlapping clock switch signal is T clk/2, the electric charge quantity is Q, the current is I, the reference voltage is V ref, and then the equivalent impedance Z of the switch capacitor equivalent resistance module is calculated as follows:
2. The high precision on-chip oscillator of claim 1, wherein the voltage-current generation module comprises: the NMOS tube MNAT, the NMOS tube MNAT1, the source electrode of the NMOS tube MNAT0 is grounded, the drain electrode is connected with the grid electrode, the drain electrode is also connected to one end of a plurality of resistors connected in series, the other ends of the plurality of resistors connected in series are connected with power supply voltage, reference voltage is led out from one node in the resistor string, the source electrode of the NMOS tube MNAT1 is grounded, the grid electrode is connected with the grid electrode of the NMOS tube MNAT0, the grid electrode of the PMOS tube MP0 and the grid electrode of the PMOS tube MP1 are connected to the drain electrode of the NMOS tube MNAT1, the source electrode of the PMOS tube MP0 and the source electrode of the PMOS tube MP1 are connected with power supply voltage, the drain electrode of the PMOS tube MP0 is connected with the source electrode of the PMOS tube MP2, the grid electrode of the PMOS tube MP2 and the grid electrode of the PMOS tube MP3 are connected with first bias voltage, and the drain electrode of the PMOS tube MP2 is connected with the drain electrode of the NMOS tube MNAT1, and thus reference current is led out from the drain electrode of the PMOS tube MP 3.
3. The high precision on-chip oscillator of claim 1 or 2, wherein the clock signal processing module generates an output clock signal having a duty cycle of 50% and generates the two-phase non-overlapping clock switching signal in dependence on the output clock signal.
4. The high precision on-chip oscillator of claim 3, wherein the clock signal processing module comprises a clock duty cycle adjustment module and a non-overlapping switching signal generation module, the clock duty cycle adjustment module generating an output clock signal having a duty cycle of 50%, the non-overlapping switching signal generation module generating the two-phase non-overlapping clock switching signal in dependence upon the output clock signal.
5. The high precision on-chip oscillator of claim 1, wherein the switched capacitor equivalent resistance module comprises a first terminal, a second terminal, an NMOS transistor MN0, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, a first capacitor, and a second capacitor; the drain electrode of the NMOS tube MN0 and the drain electrode of the NMOS tube MN1 are connected to the first terminal, the source electrode of the NMOS tube MN0, the drain electrode of the NMOS tube MN2 and one end of the first capacitor are connected, the source electrode of the NMOS tube MN1, the drain electrode of the NMOS tube MN3 and one end of the second capacitor are connected, the source electrode of the NMOS tube MN2, the source electrode of the NMOS tube MN3, the other end of the first capacitor and the other end of the second capacitor are connected to the second terminal, the grid electrode of the NMOS tube MN0 and the grid electrode of the NMOS tube MN3 are connected with one phase clock switch signal, and the grid electrode of the NMOS tube MN1 and the grid electrode of the NMOS tube MN2 are connected with the other phase clock switch signal.
6. The high-precision on-chip oscillator of claim 1, wherein the clock frequency-current conversion module comprises an NMOS tube MN4, a PMOS tube MP5, an amplifier and a switched capacitor equivalent resistor, wherein a gate of the NMOS tube MN4 is connected to an output end of the amplifier, a source of the NMOS tube MN4 is connected to a negative input end of the amplifier and one end of the switched capacitor equivalent resistor, the other end of the switched capacitor equivalent resistor is grounded, the two-phase non-overlapping clock switching signal is applied to the negative input end of the amplifier through the switched capacitor equivalent resistor, a positive input end of the amplifier is connected to a reference voltage Vref generated by the voltage-current generation module, a drain of the NMOS tube MN4 is connected to a drain and a gate of the PMOS tube MP4, a source of the PMOS tube MP4 is connected to a power supply voltage, a gate of the PMOS tube MP4 is also connected to a gate of the PMOS tube MP5, a source of the PMOS tube MP5 is connected to a power supply voltage, and the source of the PMOS tube MP5 outputs the proportional current; then there is
Wherein I clk is the proportional current.
7. The high-precision on-chip oscillator of claim 6, wherein the current comparison module comprises an NMOS transistor MN5, an NMOS transistor MN6, an NMOS transistor MN7, an NMOS transistor MN8, an NMOS transistor MN9, a PMOS transistor MP6 and a PMOS transistor MP7, wherein the drain electrode of the NMOS transistor MN7 is connected with a bias current, the source electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN6, the grid electrode of the NMOS transistor MN5 is connected with the drain electrode of the NMOS transistor MN6 and the grid electrode of the NMOS transistor MN6, a second bias voltage of the grid electrode of the NMOS transistor MN6 is generated, the source electrode of the NMOS transistor MN6 is grounded, the drain electrode of the NMOS transistor MN7 is connected with a reference current, the grid electrode of the NMOS transistor MN7 is connected with the drain electrode of the NMOS transistor MN7, the source electrode of the NMOS transistor MN8 is grounded, and the grid electrode of the NMOS transistor MN8 is connected with the grid electrode of the NMOS transistor MN7, the source of NMOS pipe MN8 is grounded, the drain electrode of NMOS pipe MN8 is connected with the source electrode of NMOS pipe MN9, the grid electrode of NMOS pipe MN9 is connected with the second bias voltage, the drain electrode of NMOS pipe MN9 is connected with the drain electrode of PMOS pipe MP6, the source electrode of PMOS pipe MP6 is connected with the power supply voltage, the grid electrode of PMOS pipe MP6 is connected with the grid electrode of PMOS pipe MP7, the source electrode of PMOS pipe MP7 is connected with the power supply voltage, the drain electrode of PMOS pipe MP7 is connected with the grid electrode of itself and grounded, and the proportional current is connected with the drain electrode of PMOS pipe MP7, so that the comparison of reference current and proportional current is realized, and the third bias voltage is led out between NMOS pipe MN9 and PMOS pipe MP 6.
8. The high-precision on-chip oscillator of claim 7, wherein the clock oscillation module comprises N inverting amplifiers connected in sequence with input terminals and output terminals, N third capacitors, wherein the third capacitors are in one-to-one correspondence with the inverting amplifiers,
One end of each third capacitor is connected with the output end of a corresponding phase-inverting amplifier, the other end of each third capacitor is grounded, the output end of the Nth phase-inverting amplifier is connected with one input end of a NAND gate, the other input end of the NAND gate is enabled, the output end of the NAND gate generates the initial signal, one bias end of each phase-inverting amplifier is connected with a third bias voltage, and the other bias end of each phase-inverting amplifier is connected with a fourth bias voltage.
9. The high precision on-chip oscillator of claim 8,
Iclk＝K0*Iref，Vref＝K2*R*Iref,Iclk＝2Cs*fckl*Vref，
K0*Iref＝2Cs*fclk*K2*R*Iref，
Wherein K0, K1 and K2 are constants, VDD is power supply voltage, and R is a resistor.
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| CN112671401B (en) * | 2020-12-31 | 2024-05-24 | 拓尔微电子股份有限公司 | Adjustable high-frequency oscillator CMOS circuit with adjusting precision and adjusting method |
| CN115529024B (en) * | 2022-11-30 | 2023-03-17 | 上海海栎创科技股份有限公司 | On-chip clock oscillator circuit and oscillation frequency control method |
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| CN208369560U (en) * | 2018-10-31 | 2019-01-11 | 上海海栎创微电子有限公司 | Oscillator on high-precision sheet |
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