CN114726315A - RC relaxation oscillation circuit and RC relaxation oscillator - Google Patents
RC relaxation oscillation circuit and RC relaxation oscillator Download PDFInfo
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- CN114726315A CN114726315A CN202210613867.9A CN202210613867A CN114726315A CN 114726315 A CN114726315 A CN 114726315A CN 202210613867 A CN202210613867 A CN 202210613867A CN 114726315 A CN114726315 A CN 114726315A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/02—Details
- H03B5/04—Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/20—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator
- H03B5/24—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
Abstract
The invention discloses an RC relaxation oscillation circuit and an RC relaxation oscillator, wherein the oscillation circuit comprises: a reference current generating circuit for generating a reference current; a current correction circuit for generating a correction current; a switched capacitor circuit for generating a comparison voltage; a reference voltage generating circuit that generates a reference voltage; a comparator circuit that generates a comparison signal; and a logic control circuit for outputting the clock signal. According to the RC relaxation oscillation circuit provided by the embodiment of the invention, the charging current is adjusted through the current correction circuit, so that the problem that the frequency of an oscillation signal is greatly influenced by process errors is solved; the invention compensates the time constant of the oscillating circuit and the delay time of the comparator circuit, thereby solving the problem that the frequency of the oscillating signal generated by the oscillating circuit is greatly influenced by temperature. The invention reduces the influence of temperature and process error on the oscillation frequency by optimizing the traditional oscillation circuit, has simple circuit design and brings convenience to system application.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly to an RC relaxation oscillation circuit and an RC relaxation oscillator.
Background
In the TEG interface circuit, in order to generate a stable clock signal to control the operation of the switching tube, an oscillation circuit needs to be designed to generate a stable oscillation signal. Commonly used oscillation circuits include quartz crystal oscillation circuits, ring oscillation circuits, LC oscillation circuits, RC relaxation oscillation circuits, and the like. Although the quartz crystal oscillation circuit has extremely high stability, an external crystal oscillator is required, which undoubtedly increases the circuit area, the size and the cost of a product; the ring oscillator circuit has a simple structure, but has high dependence on external conditions such as a power supply, temperature and the like; the LC oscillating circuit is often applied to the occasion with higher frequency, the clock signal required by the TEG interface circuit is generally about 100kHz, and the LC oscillating circuit needs to use an inductor, which increases the circuit area. Therefore, the RC relaxation oscillation circuit is the preferred circuit for generating the oscillation signal by the TEG interface circuit.
At present, an RC relaxation oscillation circuit is widely used as a clock generation circuit in a TEG interface circuit, but the RC relaxation oscillation circuit is sensitive to temperature and process errors. The oscillation period of the RC relaxation oscillation circuit is mainly determined by three factors, namely a resistor R, a capacitor C and the delay time of a comparator, however, the three factors are very susceptible to temperature and process errors, and therefore, the conventional RC relaxation oscillation circuit needs to be optimized.
Therefore, based on the above analysis, the prior art has the following disadvantages: quartz crystal oscillation circuits, ring oscillation circuits and LC oscillation circuits are not suitable for TEG interface circuits; the traditional RC relaxation oscillation circuit is sensitive to external conditions such as temperature, process errors and the like, and the resistor R, the capacitor C and the delay time of the comparator are easily influenced.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art that is already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide an RC relaxation oscillation circuit and an RC relaxation oscillator, which can provide stable clock signals, have a clock oscillation period not influenced by external factors such as temperature, process errors and the like, have simple circuit design and bring convenience to system application.
To achieve the above object, an embodiment of the present invention provides an RC relaxation oscillation circuit, including: the circuit comprises a reference current generating circuit, a current correcting circuit, a switched capacitor circuit, a reference voltage generating circuit, a comparator circuit and a logic control circuit.
The reference current generating circuit is used for generating a reference current; the current correction circuit is used for generating an adjustable correction current according to the reference current; the switch capacitor circuit is used for generating comparison voltage according to the correction current; the reference voltage generating circuit is used for generating an adjustable reference voltage; the comparator circuit generates a comparison signal according to the comparison voltage and the reference voltage; the logic control circuit outputs a clock signal according to the comparison signal, and controls the switching of the switch in the switched capacitor circuit through the clock signal so as to alternately charge or discharge the capacitor in the switched capacitor circuit.
In one or more embodiments of the present invention, the current correction circuit includes a plurality of adjusting units, each of the adjusting units includes an adjusting tube and a controllable switch tube, a gate of the adjusting tube is connected to the reference current generating circuit, a source of the adjusting tube is connected to the power supply, a drain of the adjusting tube is connected to a source of the controllable switch tube, the gate of the controllable switch tube is used as the control terminal, and the drain of the controllable switch tube is connected to the comparator circuit and the switched capacitor circuit.
In one or more embodiments of the present invention, if the adjusting unit is provided in plurality, the current mirror ratio between the adjusting tubes is proportionally set.
In one or more embodiments of the present invention, four groups of the adjusting units are provided, the adjusting transistors include a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, and the controllable switch transistor includes a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor;
the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected and connected with a reference current generating circuit, the source electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected with a power supply, the drain electrode of the first MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the second MOS tube is connected with the source electrode of the sixth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the seventh MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the eighth MOS tube, the grid electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are all used as control ends, and the drain electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with a comparator circuit and a switch capacitor circuit.
In one or more embodiments of the present invention, the current mirror ratio of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor is 1: 2: 4: 8.
in one or more embodiments of the invention, the switched-capacitor circuit includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch, and a fourth switch;
the first end of the first switch is connected with the first end of the third switch and is connected with the current correction circuit, the second end of the first switch, the first end of the second switch and the first end of the first capacitor are connected, the second end of the second switch is grounded, the second end of the first capacitor is grounded, the second end of the third switch, the first end of the second capacitor and the first end of the fourth switch are connected, the second end of the second capacitor is grounded, the second end of the fourth switch is grounded, and the first switch, the second switch, the third switch and the fourth switch are controlled by a clock signal to be turned on or turned off.
In one or more embodiments of the present invention, the reference voltage generating circuit includes a ninth MOS transistor and a plurality of resistors;
the source electrode of the ninth MOS tube is connected with the power supply, the grid electrode of the ninth MOS tube is connected with the reference current generating circuit, the drain electrode of the ninth MOS tube is connected with the comparator circuit, and the resistor is connected between the drain electrode of the ninth MOS tube and the ground in series.
In one or more embodiments of the present invention, the resistors are provided in two and are a first resistor and a second resistor, respectively, and the first resistor and the second resistor are a positive temperature coefficient resistor and a negative temperature coefficient resistor, respectively.
In one or more embodiments of the invention, the oscillation period of the RC relaxation oscillation circuit is:
r1 is a first resistor, R2 is a second resistor, C is a capacitor of the switched capacitor circuit,
is the delay time of the comparator circuit,
is a time constant and the temperature coefficient of the time constant is positive, the temperature coefficient of the delay time of the comparator circuit CMP is negative.
The invention also discloses an RC relaxation oscillator which comprises the RC relaxation oscillation circuit.
Compared with the prior art, according to the RC relaxation oscillation circuit and the RC relaxation oscillator, the charging current of the switch capacitance circuit is corrected and adjusted by generating the adjustable correction current through the current correction circuit, and the problem that the frequency of an oscillation signal generated by the RC relaxation oscillation circuit is greatly influenced by process errors is solved; according to the invention, the time constant of the RC relaxation oscillation circuit and the delay time of the comparator circuit are compensated through the reference voltage generating circuit, so that the problem that the frequency of an oscillation signal generated by the RC relaxation oscillation circuit is greatly influenced by temperature is solved. The invention reduces the influence of temperature and process error on the oscillation frequency by optimizing the traditional RC relaxation oscillation circuit, has simple circuit design and brings convenience to system application.
Drawings
Fig. 1 is a circuit schematic of an RC relaxation oscillation circuit according to an embodiment of the present invention.
Fig. 2 is a circuit schematic of a current correction circuit according to an embodiment of the present invention.
Fig. 3 is a circuit schematic of a switched-capacitor circuit according to an embodiment of the invention.
FIG. 4 is a circuit schematic of a reference voltage circuit according to an embodiment of the present invention.
Detailed Description
Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
As shown in fig. 1, an RC relaxation oscillation circuit includes: a reference current generating circuit 10, a current correcting circuit 20, a switched capacitor circuit 30, a reference voltage generating circuit 40, a comparator circuit CMP, and a logic control circuit 50.
An output terminal of the reference current generating circuit 10 is connected to an input terminal VP of the current correcting circuit 20. An output terminal of the current correction circuit 20 is connected to an input terminal Vin of the switched capacitor circuit 30 and a first input terminal of a comparator circuit CMP, and an output terminal of the reference voltage generation circuit 40 is connected to a second input terminal of the comparator circuit CMP. The first input terminal of the comparator circuit CMP is a positive input terminal, and the second input terminal of the comparator circuit CMP is a negative input terminal. In other embodiments, the first input terminal of the comparator circuit CMP is a negative input terminal and the second input terminal of the comparator circuit CMP is a positive input terminal.
The logic control circuit 50 in this embodiment is a D flip-flop. The output of the comparator circuit CMP is connected to the clk input of the logic control circuit 50, the D input of the logic control circuit 50 is connected to the Q-output and to the switched capacitor circuit 30, and the Q output of the logic control circuit 50 is also connected to the switched capacitor circuit 30.
As shown in fig. 1, the reference current generating circuit 10 is used to generate a reference current Iref. The reference current Iref in this embodiment is a nanoamp positive temperature coefficient reference current, and the total current of the RC relaxation oscillation circuit can be reduced.
As shown in fig. 1, the current correction circuit 20 is configured to generate an adjustable correction current I5 according to a reference current Iref. The correction current I5 is used to supply the switched-capacitor circuit 30.
As shown in fig. 2, the current modification circuit 20 includes a plurality of adjusting units 21, and the adjusting units 21 include adjusting tubes and controllable switching tubes. The grid electrode of the adjusting tube is connected with the reference current generating circuit 10, the source electrode of the adjusting tube is connected with a power supply VDD, and the drain electrode of the adjusting tube is connected with the source electrode of the controllable switch tube. The gate of the controllable switch transistor is used as the control terminal, and the drain of the controllable switch transistor is connected to the first input terminal of the comparator circuit CMP and the input terminal Vin of the switched capacitor circuit 30. If the adjusting unit 21 is provided in plural, the current mirror ratio between the adjusting tubes is set in proportion.
Further, the adjusting units 21 in the present embodiment are provided in four sets. The regulating tube comprises a first MOS tube MP1, a second MOS tube MP2, a third MOS tube MP3 and a fourth MOS tube MP4, and the controllable switching tube comprises a fifth MOS tube MP5, a sixth MOS tube MP6, a seventh MOS tube MP7 and an eighth MOS tube MP 8. The first MOS transistor MP1 and the fifth MOS transistor MP5 form a group of adjusting units 21, the second MOS transistor MP2 and the sixth MOS transistor MP6 form a group of adjusting units 21, the third MOS transistor MP3 and the seventh MOS transistor MP7 form a group of adjusting units 21, and the fourth MOS transistor MP4 and the eighth MOS transistor MP8 form a group of adjusting units 21.
Specifically, the gates of the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3 and the fourth MOS transistor MP4 are connected to the output terminal of the reference current generating circuit 10, and the gates of the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3 and the fourth MOS transistor MP4 are connected to form the input terminal VP for receiving the reference current Iref.
The sources of the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3 and the fourth MOS transistor MP4 are connected to a power supply VDD. The drain electrode of the first MOS transistor MP1 is connected to the source electrode of the fifth MOS transistor MP5, the drain electrode of the second MOS transistor MP2 is connected to the source electrode of the sixth MOS transistor MP6, the drain electrode of the third MOS transistor MP3 is connected to the source electrode of the seventh MOS transistor MP7, and the drain electrode MP4 of the fourth MOS transistor is connected to the source electrode of the eighth MOS transistor MP 8.
The drains of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the seventh MOS transistor MP7, and the eighth MOS transistor MP8 are connected to the first input terminal of the comparator circuit CMP. The drains of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the seventh MOS transistor MP7, and the eighth MOS transistor MP8 are connected to the input terminal Vin of the switched capacitor circuit 30, so as to output the correction current I5 to the switched capacitor circuit 30.
As shown in fig. 2, the correction current I5= I1+ I2+ I3+ I4, where I1 is a current flowing through the first MOS transistor MP1, I2 is a current flowing through the second MOS transistor MP2, I3 is a current flowing through the third MOS transistor MP3, and I4 is a current flowing through the fourth MOS transistor MP 4. The current mirror proportion of the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3 and the fourth MOS transistor MP4 is k: 2 k: 4 k: 8 k, wherein k is larger than or equal to 1, and the current mirror proportion of each MOS tube is adjusted by adjusting the width-length ratio of each MOS tube. K =1 in this embodiment, that is, the current mirror proportion of the first MOS transistor MP1, the second MOS transistor MP2, the third MOS transistor MP3, and the fourth MOS transistor MP4 is 1: 2: 4: 8, available I4=2 × I3=4 × I2=8 × I1, wherein the current mirror ratio of the first MOS transistor MP1 to the reference current Iref is 1: 1, I1= Iref.
The gates of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the seventh MOS transistor MP7 and the eighth MOS transistor MP8 are all used as control terminals. In this embodiment, the gate of the fifth MOS transistor MP5 is connected to the first enable signal EN1, the gate of the sixth MOS transistor MP6 is connected to the second enable signal EN2, the gate of the seventh MOS transistor MP7 is connected to the third enable signal EN3, and the gate of the eighth MOS transistor MP8 is connected to the fourth enable signal EN 4.
The fifth MOS transistor MP5 is controlled to be turned on and off by adjusting the first enable signal EN1, the sixth MOS transistor MP6 is controlled to be turned on and off by adjusting the second enable signal EN2, the seventh MOS transistor MP7 is controlled to be turned on and off by adjusting the third enable signal EN3, and the eighth MOS transistor MP8 is controlled to be turned on and off by adjusting the fourth enable signal EN 4. Under different process angles, one or more of the fifth MOS transistor MP5, the sixth MOS transistor MP6, the seventh MOS transistor MP7 and the eighth MOS transistor MP8 are turned on by adjusting the first enable signal EN1, the second enable signal EN2, the third enable signal EN3 and the fourth enable signal EN4, so as to change and adjust the correction current I5.
As shown in fig. 1, the switched capacitor circuit 30 is configured to generate a comparison voltage Vramp according to the correction current, where the comparison voltage Vramp is a sawtooth wave.
As shown in fig. 3, the switched capacitor circuit 30 includes a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.
A first terminal of the first switch S1 and a first terminal of the third switch S3 are connected to form an input terminal Vin and are connected to an output terminal of the current modification circuit 20 and a first input terminal of the comparator circuit CMP to provide a comparison voltage Vramp to the comparator circuit CMP. The second terminal of the first switch S1, the first terminal of the second switch S2 and the first terminal of the first capacitor C1 are connected, the second terminal of the second switch S2 is grounded, and the second terminal of the first capacitor C1 is grounded. The second terminal of the third switch S3, the first terminal of the second capacitor C2 and the first terminal of the fourth switch S4 are connected, the second terminal of the second capacitor C2 is grounded, and the second terminal of the fourth switch S4 is grounded.
The first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 are controlled to be turned on or off by a clock signal output from the logic control circuit 50, the first switch S1 and the fourth switch S4 are connected to the Q output terminal of the logic control circuit 50 to receive the clock signal clk +, and the second switch S2 and the third switch S3 are connected to the Q output terminal and the D output terminal of the logic control circuit 50 to receive the clock signal clk-.
The first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are switched by a clock signal, so that the first capacitor C1 and the second capacitor C2 are alternately charged or discharged. When the first switch S1 and the fourth switch S4 are closed and the second switch S2 and the third switch S3 are opened, the first capacitor C1 is charged by the correction circuit I5, and the second capacitor C2 is discharged to the ground; when the second switch S2 and the third switch S3 are closed and the first switch S1 and the fourth switch S4 are opened, the second capacitor C2 is charged by the correction circuit I5, and the first capacitor C1 is discharged to the ground, so that the comparison voltage Vramp is obtained by alternately charging and discharging.
As shown in FIG. 1, a reference voltage generation circuit 40 is used to generate an adjustable reference voltage
Reference electricityThe voltage Vref is used to supply the comparator circuit CMP.
As shown in fig. 4, the reference voltage generating circuit 40 includes a ninth MOS transistor MP9 and a plurality of resistors.
Specifically, the source of the ninth MOS transistor MP9 is connected to the power supply VDD, and the gate of the ninth MOS transistor MP9 is connected to the output terminal of the reference current generating circuit 10 to receive the reference current Iref. The drain of the ninth MOS transistor MP9 is connected to the second input terminal of the comparator circuit CMP to supply the comparator circuit CMP with the reference voltage Vref. The resistor is connected in series between the drain of the ninth MOS transistor MP9 and ground.
The resistors in this embodiment are two resistors, namely a first resistor R1 and a second resistor R2, and the first resistor R1 and the second resistor R2 are a positive temperature coefficient resistor and a negative temperature coefficient resistor, respectively. In this embodiment, the first resistor R1 is a positive temperature coefficient resistor, and the second resistor R2 is a negative temperature coefficient resistor. A first end of the first resistor R1 is connected to the drain of the ninth MOS transistor MP9, a second end of the first resistor R1 is connected to a first end of the second resistor R2, and a second end of the second resistor is grounded. The first resistor R1 has a positive terminal for generating the reference voltage Vref and a negative terminal. The first terminal of the second resistor R2 is the positive terminal and the second terminal of the second resistor R2 is the negative terminal. The first resistor R1 and the second resistor R2 are connected in series, so that the whole resistance value and the temperature coefficient can be adjusted, and the size and the temperature coefficient of the reference voltage Vref can be adjusted.
As shown in fig. 1, the comparator circuit CMP generates a comparison signal from the comparison voltage Vramp and the reference voltage Vref. The logic control circuit 50 generates a clock signal according to the comparison signal, and triggers the logic control circuit 50 when the comparison signal rises, so that the D trigger is the turnover of the Q output end and the Q-output end.
The oscillation period of the RC relaxation oscillation circuit in this embodiment is:
r1 is a first resistor, R2 is a second resistor, C is a first capacitor C1 or a second capacitor C2,
is the delay time of the comparator circuit CMP.
In the present embodiment
Is a time constant and the temperature coefficient of the time constant is positive, and the temperature coefficient of the delay time of the comparator circuit CMP is negative, so that the temperature coefficient of the oscillation cycle of the entire RC relaxation oscillation circuit is small.
In this embodiment, the time constant is realized by the resistor R with adjustable resistance value and temperature coefficient and the reference voltage Vref with adjustable size and temperature coefficient
Delay time of the sum comparator circuit CMP
Compensation of (2).
The embodiment also discloses an RC relaxation oscillator, which comprises the RC relaxation oscillation circuit.
The adjustable correction current is generated by the current correction circuit to correct and adjust the charging current of the switch capacitor circuit, so that the problem that the frequency of an oscillation signal generated by an RC relaxation oscillation circuit is greatly influenced by process errors is solved; the reference voltage generating circuit is used for compensating the time constant of the RC relaxation oscillation circuit and the delay time of the comparator circuit CMP, so that the problem that the frequency of an oscillation signal generated by the RC relaxation oscillation circuit is greatly influenced by temperature is solved. The invention reduces the influence of temperature and process error on the oscillation frequency by optimizing the traditional RC relaxation oscillation circuit, has simple circuit design and brings convenience to system application.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. An RC relaxation oscillation circuit, comprising:
a reference current generating circuit for generating a reference current;
the current correction circuit is used for generating an adjustable correction current according to the reference current;
the switch capacitor circuit is used for generating a comparison voltage according to the correction current;
a reference voltage generating circuit for generating an adjustable reference voltage;
a comparator circuit for generating a comparison signal based on the comparison voltage and the reference voltage; and
and the logic control circuit is used for outputting a clock signal according to the comparison signal and controlling the switching of the switch in the switched capacitor circuit through the clock signal so as to alternately charge or discharge the capacitor in the switched capacitor circuit.
2. The RC relaxation oscillation circuit as claimed in claim 1, wherein said current modification circuit comprises a plurality of adjusting units, said adjusting units comprise adjusting tubes and controllable switching tubes, gates of said adjusting tubes are connected to the reference current generation circuit, sources of said adjusting tubes are connected to the power supply, drains of said adjusting tubes are connected to sources of the controllable switching tubes, gates of said controllable switching tubes are used as control terminals, drains of said controllable switching tubes are connected to the comparator circuit and the switched capacitor circuit.
3. The RC relaxation oscillation circuit of claim 2 wherein if the adjusting unit is provided in plurality, the current mirror ratio between the adjusting tubes is set in proportion.
4. The RC relaxation oscillation circuit of claim 3, wherein four sets of the regulating units are provided, the regulating transistors comprise a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, and the controllable switching transistor comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor;
the grid electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected and connected with a reference current generating circuit, the source electrodes of the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are connected with a power supply, the drain electrode of the first MOS tube is connected with the source electrode of the fifth MOS tube, the drain electrode of the second MOS tube is connected with the source electrode of the sixth MOS tube, the drain electrode of the third MOS tube is connected with the source electrode of the seventh MOS tube, the drain electrode of the fourth MOS tube is connected with the source electrode of the eighth MOS tube, the grid electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are all used as control ends, and the drain electrodes of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube are connected with a comparator circuit and a switch capacitor circuit.
5. The RC relaxation oscillation circuit of claim 4 wherein the current mirror ratio of the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor is 1: 2: 4: 8.
6. the RC relaxation oscillation circuit of claim 1, wherein the switched-capacitor circuit comprises a first capacitor, a second capacitor, a first switch, a second switch, a third switch, and a fourth switch;
the first end of the first switch is connected with the first end of the third switch and is connected with the current correction circuit, the second end of the first switch, the first end of the second switch and the first end of the first capacitor are connected, the second end of the second switch is grounded, the second end of the first capacitor is grounded, the second end of the third switch, the first end of the second capacitor and the first end of the fourth switch are connected, the second end of the second capacitor is grounded, the second end of the fourth switch is grounded, and the first switch, the second switch, the third switch and the fourth switch are controlled by a clock signal to be turned on or turned off.
7. The RC relaxation oscillation circuit of claim 1 wherein said reference voltage generating circuit comprises a ninth MOS transistor and a number of resistors;
the source electrode of the ninth MOS tube is connected with the power supply, the grid electrode of the ninth MOS tube is connected with the reference current generating circuit, the drain electrode of the ninth MOS tube is connected with the comparator circuit, and the resistor is connected between the drain electrode of the ninth MOS tube and the ground in series.
8. The RC relaxation oscillation circuit of claim 7 wherein the resistors are provided in two and are a first resistor and a second resistor, respectively, the first resistor and the second resistor being a positive temperature coefficient resistor and a negative temperature coefficient resistor, respectively.
9. The RC relaxation oscillation circuit of claim 8 wherein an oscillation period of the RC relaxation oscillation circuit is:
r1 is the first resistor, R2 is the second resistor, C is the capacitor of the switched capacitor circuit,
is the delay time of the comparator circuit and,
is a time constantThe temperature coefficient of the time constant is positive, and the temperature coefficient of the delay time of the comparator circuit CMP is negative.
10. An RC relaxation oscillator characterized by comprising an RC relaxation oscillation circuit as claimed in any one of claims 1 to 9.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117200756A (en) * | 2023-11-08 | 2023-12-08 | 成都爱旗科技有限公司 | Relaxation oscillator with adjustable temperature coefficient and temperature coefficient adjusting method thereof |
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| CN117200756B (en) * | 2023-11-08 | 2024-02-02 | 成都爱旗科技有限公司 | Relaxation oscillator with adjustable temperature coefficient and temperature coefficient adjusting method thereof |
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