CN112532247B

CN112532247B - Asynchronous progressive register analog-to-digital converter

Info

Publication number: CN112532247B
Application number: CN202010004029.2A
Authority: CN
Inventors: 曾华俊
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2019-09-18
Filing date: 2020-01-03
Publication date: 2023-06-30
Anticipated expiration: 2040-01-03
Also published as: CN112532247A; TW202114355A; TWI726421B

Abstract

The invention provides an asynchronous progressive register analog-to-digital converter, which comprises an analog signal input end for receiving an analog signal; the sampling and maintaining circuit samples the analog signal to obtain and maintain a sampling voltage; the difference amplifier amplifies the difference between the sampling voltage and a conversion voltage to output positive and negative output voltage signals; the comparison latch circuit compares the positive and negative output voltage signals to generate and latch a comparison result, and when a steady state signal is received, the comparison latch circuit outputs the comparison result. The progressive register responds to the comparison result to store and adjust a digital test value. The digital-to-analog converter is used for converting the digital test value into a conversion voltage; the comparator compares the positive output voltage signal with the negative output voltage signal to output a steady state signal.

Description

Asynchronous progressive register analog-to-digital converter

Technical Field

The present invention relates to an asynchronous progressive register analog-to-digital converter, and more particularly, to an asynchronous progressive register analog-to-digital converter capable of dynamically determining a delay time required for each bit conversion.

Background

In the circuit design of the conventional Synchronous (Synchronous) step-up (Successive Approximation Register, SAR) analog-to-digital converter (ADC), correction (calibration) is performed before the Synchronous step-up ADC is formally operated, so as to avoid errors caused by non-ideal effects of the step-up ADC itself. However, with the demand for High speed (High speed), high performance (High performance), and low power consumption (low power) of the step-by-step analog-to-digital converter, an Asynchronous step-by-step analog-to-digital converter has been developed.

Referring to FIG. 1, a prior art asynchronous step-by-step ADC is shown. The progressive register (SAR) 13 receives a clock CLK and includes a register value 131. The progressive register 13 gradually approximates an analog signal 101 by constantly changing the register value 131. For example, when compared to an analog signal 101 of 0.312V, the register value 131 in the progressive register 13 may begin at 0.5, then 0.25, then 0.375, then 0.313, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312. When the conversion is completed, the progressive register 13 outputs a conversion completion signal EOC (End of Conversion). The progressive register 13 outputs the current register value 131 to a digital-to-analog converter (DAC) 14. The digital-to-analog converter receives a reference voltage VREF and converts the received register value 131 into a converted voltage VDAC according to the reference voltage VREF.

The analog signal 101 is applied to the sample-and-hold circuit (Sample and HoldCircuit) 16 via an analog signal input VIN, which samples and holds the voltage value of the analog signal 101. For example, a capacitor of the sample-and-hold circuit may be charged by the voltage of the analog signal 101, and then isolated from the analog signal 101, thereby maintaining the voltage value of the input analog signal 101. A sampling voltage 161 of the input voltage sampled by the sample-and-hold circuit 16 is applied to the negative input terminal of the comparator 11. The switching voltage VDAC is applied to the positive input of the comparator 11.

The comparator 11 compares the converted voltage VDAC with the sampling voltage 161 of the analog signal 101, and when the converted voltage VDAC is higher than the sampling voltage 161, the comparator 11 generates an output signal 111 with a high level, which indicates that the register value in the progressive register 13 is too high. After receiving the output signal of the comparator 11, the pulse generator 12 generates a pulse signal 121 corresponding to the level of the output signal to the progressive register 13, so that the register value of the progressive register 13 can be reduced or increased. For example, when the comparator 11 outputs a high level output signal, the pulse signal is used to control the register value of the progressive register 13 to decrease; when the comparator 11 outputs a low level output signal, the pulse signal is used to control the increment of the register value of the progressive register 13.

In practical applications, since the gain (gain) of the amplifier (OP) and the Comparator (Comparator) is limited, when the difference between the two input signals is small, the amplifier and the Comparator need more reaction time to generate amplified signals, which causes a metastable state (meta-state) of the amplifier and the Comparator, and if the output signal of the Comparator is received during the metastable state, an error signal may be received, which may cause the analog-to-digital converter to output an incorrect result. In addition, when switching to different bits, the metastable state time of the amplifier and the comparator is different due to the difference between the sampling voltage 161 and the switching voltage VDAC, so the asynchronous step-by-step register adc in the prior art is added with a delay adjustment module 15, which comprises a dynamic delay unit 151 and a fixed delay unit 152.

As shown in fig. 1, the delay adjustment module 15 is electrically connected between the pulse generator 12 and the trigger terminal of the comparator 11. When the pulse generator 12 generates the control signal 121 to the progressive register 13, the progressive register 13 updates the register value 131, the new register value 131 is converted by the digital-to-analog converter (DAC) 14 to generate the converted voltage VDAC, and then the comparator 11 compares the converted voltage VDAC with the sampling voltage 161. Since the metastable time length of the comparison by the comparator 11 is not determined, in order to avoid receiving the erroneous output signal 111, the pulse generator 12 outputs the control signal 121 and also generates the trigger signal 122 to the delay adjustment module 15, and after the delay of the dynamic delay unit 151 and the fixed delay unit 152, the trigger signal 122 is input to the trigger end of the comparator 11, and the trigger comparator 11 outputs the output signal 111 to ensure that the output signal 111 is not affected by the metastable state.

The dynamic delay unit 151 sets different delay times corresponding to the conversion of different bits, which has the disadvantage of excessively complicated design.

Disclosure of Invention

An objective of the present invention is to provide an asynchronous (asynchronous) step-by-step register (SAR) analog-to-digital converter (ADC) for dynamically determining a delay time required for each bit conversion, thereby reducing a circuit design difficulty of the asynchronous step-by-step register ADC and effectively increasing a sampling speed of the ADC.

In order to achieve the above objective, the present invention provides an asynchronous step-by-step register analog-to-digital converter, which comprises an analog signal input terminal, a sample-and-hold circuit, a differential amplifier, a comparator, a comparison latch circuit, a step-by-step register and a digital-to-analog converter. The analog signal input end is used for receiving an analog signal. The sample-and-hold circuit is used for sampling the analog signal to obtain and hold a sampling voltage. The difference amplifier is used for amplifying the difference between the sampling voltage and a conversion voltage so as to output a positive output voltage signal and a negative output voltage signal. When the difference between the positive output voltage signal and the negative output voltage signal reaches a preset voltage threshold value, the comparator outputs a steady-state signal. The comparison latch circuit continuously compares the positive output voltage signal and the negative output voltage signal of the difference amplifier to generate and latch a comparison result. When the comparison latch circuit receives the steady-state signal, the comparison latch circuit outputs a comparison result. A step-by-step register (SAR) stores and adjusts a digital test value (digital test value) in response to the comparison. The digital-to-analog converter is used for converting the digital test value into a converted voltage.

According to an embodiment of the present invention, the output of the differential amplifier has a metastable state (meta-stable state).

According to an embodiment of the present invention, the comparison latch circuit enters a metastable state when the output of the difference amplifier is the metastable state.

According to an embodiment of the present invention, the asynchronous step-by-step register analog-to-digital converter further comprises a fixed delay unit coupled between the comparison latch circuit and the differential amplifier, wherein the fixed delay unit receives a trigger signal output by the comparison latch circuit and delays the trigger signal for a fixed time to output the trigger signal to the differential amplifier so as to trigger the differential amplifier to operate.

According to an embodiment of the present invention, the differential amplifier may include a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth NMOS transistor, wherein the sources of the first NMOS transistor and the second NMOS transistor are coupled to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor is grounded, the drain of the third PMOS transistor is coupled to the drain of the first NMOS transistor, the drain of the fourth PMOS transistor is coupled to the drain of the second NMOS transistor, the sources of the third PMOS transistor and the fourth PMOS transistor are coupled to a power voltage terminal, the gates of the first NMOS transistor receive the sampling voltage, the gates of the second NMOS transistor receive the switching voltage, the gates of the third PMOS transistor and the fourth PMOS transistor are coupled to the gates of the fourth PMOS transistor, and the gates of the fifth PMOS transistor receive a clock signal.

According to an embodiment of the present invention, the comparison latch circuit may include a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, and a twelfth NMOS transistor, a drain of the ninth NMOS transistor being coupled to a drain of the eleventh NMOS transistor, a drain of the seventh PMOS transistor, and a gate of the tenth NMOS transistor, a drain of the tenth NMOS transistor being coupled to a drain of the twelfth PMOS transistor, a drain of the eighth PMOS transistor, and a gate of the ninth NMOS transistor, a gate of the eleventh NMOS transistor being coupled to a drain of the third PMOS transistor, a gate of the twelfth NMOS transistor being coupled to a drain of the fourth PMOS transistor, a gate of the ninth NMOS transistor being coupled to a gate of the seventh PMOS transistor, a gate of the tenth NMOS transistor being coupled to a gate of the eighth PMOS transistor, a drain of the seventh PMOS transistor being coupled to a source of the PMOS transistor, and a steady state signal receiving the source and the source of the PMOS transistor.

According to an embodiment of the present invention, when the level of the steady-state signal changes to turn on the sixth PMOS transistor, the voltage output on the drain of the ninth NMOS transistor is used as the comparison result.

Drawings

FIG. 1 is a block diagram of a prior art asynchronous step-up register analog-to-digital converter according to the present invention.

FIG. 2 is a block diagram of an asynchronous progressive register analog-to-digital converter according to the present invention.

FIG. 3 is a circuit diagram of an embodiment of a comparison latch circuit of the present invention.

Reference numerals:

101. 201: analog signal

11. 28: comparator with a comparator circuit

111: output signal

281: steady state signal

12. 22: pulse generator

121. 271: control signal

122: trigger signal

13. 23: progressive register

131: register value

14. 24: digital-to-analog converter

15: delay adjustment module

151: dynamic delay unit

152. 252: fixed delay unit

16. 26: sample-and-hold circuit

161. 261: sampling voltage

21: differential amplifier

211: positive output voltage signal

212: negative output voltage signal

231: register value

27: comparison latch circuit

CLK, CLK1: clock signal

D0, D1, dn-1, dn, D0 to Dn: bit position

EOC: conversion completion signal

VREF: reference voltage

VDAC: conversion voltage

VIN: analog signal input terminal

M1, M2, M5, M9, M10, M11, M12: NMOS transistor

M3, M4, M6, M7, M8: PMOS transistor

Detailed Description

The following detailed description of embodiments of the present invention will be given with reference to the drawings and examples, by which the implementation process of how the technical means are applied to solve the technical problems and achieve the technical effects can be fully understood and implemented.

Referring to FIG. 2, an asynchronous progressive register analog-to-digital converter is shown. As shown in fig. 2, the asynchronous step-up register analog-to-digital converter of the present invention may comprise an analog signal input terminal VIN, a sample-and-hold circuit 26, a difference amplifier 21, a comparator 28, a comparison latch circuit 27, a step-up register 23, and a digital-to-analog converter 24. Wherein the comparator 28 is arranged to detect the meta-stable state of the output of the difference amplifier 21.

The analog signal input terminal VIN is used for receiving the analog signal 201, and the sample-and-hold circuit 26 is used for sampling the analog signal 201 to obtain and hold the sampled voltage 261. In one embodiment, the sample-and-hold circuit 26 may have a capacitor that is charged through the voltage of the analog signal 201, and then isolates the capacitor from the analog signal 201 (isolate), thereby allowing the capacitor to maintain the voltage value of the analog signal 201.

The capacitor maintains a voltage input to the positive input of the differential amplifier 21, and the negative input of the differential amplifier 21 receives a switching voltage VDAC. The difference amplifier 21 amplifies the difference between the sampling voltage 161 and the converted voltage VDAC to output a positive output voltage signal 211 and a negative output voltage signal 212. The generation of the switching voltage VDAC is described in detail in the following paragraphs.

The positive output voltage signal 211 and a negative output voltage signal 212 are transmitted to the comparison latch circuit 27, and the comparison latch circuit 27 continuously compares the positive output voltage signal 211 and the negative output voltage signal 212 to generate and latch (latch) a comparison result. When the comparison latch circuit 27 receives a steady signal 281 from the comparator 28, the comparison latch circuit 27 outputs a control signal 271 corresponding to the comparison result to the progressive register 23.

The step-by-step register 23 stores a digital test value (digital test value), adjusts a digital test value in response to the control signal 271, and outputs the digital test value to the digital-to-analog converter 24. As shown in fig. 2, the digital-to-analog converter 24 includes n bits D0 … Dn, n being a positive integer greater than 1. The digital-to-analog converter 24 converts the digital test value into a converted voltage VDAC, which is converted into an analog voltage signal.

For example, when the sampling voltage 261 is 0.312V, the digital test value stored in the step-by-step register 23 may be initially 0.5, the digital test value of 0.5 is converted into the converted voltage VDAC of 0.5V by the digital-to-analog converter 24, and the difference between the sampling voltage 261 of 0.312V and the converted voltage VDAC of 0.5V is amplified by the difference amplifier 21. Because 0.312V is smaller than 0.5V, the positive output voltage signal 211 and the negative output voltage signal 212 outputted by the differential amplifier 21 form a negative level, so that the comparison latch circuit 27 outputs a control signal 271 representing a reduced digital test value, and the step-by-step register 23 further reduces the digital test value to 0.25.

Similarly, since 0.312V is smaller than 0.5V, the positive output voltage signal 211 and the negative output voltage signal 212 outputted by the differential amplifier 21 form a positive level, so that the comparison latch circuit 27 outputs a control signal 271 representing the digital test value, and the progressive register 23 further increases the digital test value to 0.375. And so on, the digital test values are then adjusted to 0.313, then 0.281, then 0.296, then 0.304, then 0.308, then 0.31, then 0.311, and finally 0.312. When the conversion is completed, the progressive register 23 outputs a conversion completion signal EOC (End of Conversion). The number of adjustments of the digital test value is related to the number of bits of the digital test value.

During the above operation, since the voltage difference between the sampling voltage 261 and the converted voltage VDAC is different, the metastable state time of the comparison latch circuit 27 is also different due to the metastable state of the output of the amplifier 21. In order to avoid the comparison latch circuit 27 outputting the wrong control signal 271 after entering the metastable state according to the output of the positive output voltage signal 211 and the negative output voltage signal 212 of the amplifier 21 in the metastable state, the present invention uses the comparator 28 to determine whether the output of the amplifier 21 can make the comparison latch circuit 27 deviate from the metastable state and output the correct signal. In one embodiment, when the difference between the positive output voltage signal 211 and the negative output voltage signal 212 is large enough, the comparator 28 can be enabled to output the steady-state signal 281, and the comparison latch circuit 27 is driven to compare the positive output voltage signal 211 and the negative output voltage signal 212 of the amplifier 21 and send the correct comparison result to the step-by-step register 23.

In addition, the asynchronous step-up register analog-to-digital converter of the present invention may further comprise a fixed delay unit 252 coupled between the comparison latch circuit 27 and the differential amplifier 21, wherein the fixed delay unit 252 may receive a trigger signal outputted from the comparison latch circuit 27 and delay the trigger signal for a fixed time to output the trigger signal to the differential amplifier 21 to trigger the differential amplifier 21 to operate.

Referring to fig. 3, a circuit diagram of an embodiment of a comparison latch circuit according to the present invention is shown. As shown in fig. 3, in this embodiment, the differential amplifier 21 includes a first NMOS transistor M1, a second NMOS transistor M2, a third PMOS transistor M3, a fourth PMOS transistor M4, and a fifth NMOS transistor M5. The source of the first NMOS transistor M1 and the source of the second NMOS transistor M2 are coupled to the drain of the fifth NMOS transistor M5, the source of the fifth NMOS transistor M5 is grounded, the drain of the third PMOS transistor M3 is coupled to the drain of the first NMOS transistor M1, the drain of the fourth PMOS transistor M4 is coupled to the drain of the second NMOS transistor M2, the sources of the third PMOS transistor M3 and the fourth PMOS transistor M4 are coupled to a power supply voltage terminal, the gate of the first NMOS transistor M1 receives the sampling voltage 261, the gate of the second NMOS transistor M2 receives the switching voltage VDAC, the gate of the third PMOS transistor M3 is coupled to the gate of the fourth PMOS transistor M4, and the gates of the third PMOS transistor M3, the fourth PMOS transistor M4, and the fifth NMOS transistor M5 receive a clock signal CLK1.

The voltages on the drain of the third PMOS transistor M3 and the drain of the fourth PMOS transistor M4 are the positive output voltage signal 211 and the negative output voltage signal 212, respectively, as an amplifier. It should be noted that the above-described circuit is merely illustrative, and not limiting, and any circuit that can implement the amplifier function can be used in the present invention.

As shown in fig. 3, in one embodiment, the comparison latch circuit 27 may include a sixth PMOS transistor M6, a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth NMOS transistor M9, a tenth NMOS transistor M10, an eleventh NMOS transistor M11, and a twelfth NMOS transistor M12. The source of the ninth NMOS transistor M9, the tenth NMOS transistor M10, the eleventh NMOS transistor M11, and the twelfth NMOS transistor M12 are grounded, the drain of the ninth NMOS transistor M9 is coupled to the drain of the eleventh NMOS transistor M11, the drain of the seventh PMOS transistor M7, and the gate of the tenth NMOS transistor M10, the drain of the tenth NMOS transistor M10 is coupled to the drain of the twelfth NMOS transistor M12, the drain of the eighth PMOS transistor M8, and the gate of the ninth NMOS transistor M9, the gate of the eleventh NMOS transistor M11 is coupled to the drain of the third PMOS transistor M3, the gate of the twelfth NMOS transistor M12 is coupled to the drain of the fourth PMOS transistor M4, the gate of the ninth NMOS transistor M9 is coupled to the gate of the seventh PMOS transistor M7, the gate of the tenth NMOS transistor M10 is coupled to the gate of the eighth PMOS transistor M8, the source of the sixth PMOS transistor M6 is coupled to the power supply voltage terminal, the drain is coupled to the drain of the seventh PMOS transistor M7, and the source of the eighth PMOS transistor M8, and the steady state signal receiving source 281.

When the level of the steady signal 281 changes to turn on the sixth PMOS transistor, the voltage on the drain of the ninth NMOS transistor is output as the control signal 271 representing the comparison result. It should be noted that the above-described circuit is merely illustrative, and not limiting, and any circuit that can implement the amplifier function can be used in the present invention.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather, may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims

1. An asynchronous progressive register analog-to-digital converter, comprising:

an analog signal input end for receiving an analog signal;

a sampling and maintaining circuit for sampling the analog signal to obtain and maintain a sampling voltage;

a difference amplifier for amplifying the difference between the sampling voltage and a conversion voltage to output a positive output voltage signal and a negative output voltage signal;

a comparator for outputting a steady-state signal when the difference between the positive output voltage signal and the negative output voltage signal reaches a preset voltage threshold value;

a comparison latch circuit for continuously comparing the positive output voltage signal and the negative output voltage signal of the differential amplifier to generate and latch a comparison result, and outputting the comparison result when the comparison latch circuit receives the steady-state signal;

a step-by-step register SAR for storing and adjusting a digital test value in response to the comparison result; and

a digital-to-analog converter for converting the digital test value into the converted voltage.

2. The analog-to-digital converter of claim 1, wherein the output of the differential amplifier has a metastable state.

3. The analog-to-digital converter of claim 2, wherein the comparison latch circuit enters the metastable state when the output of the differential amplifier is the metastable state.

4. The analog-to-digital converter of claim 1, further comprising a fixed delay unit coupled between the comparison latch circuit and the differential amplifier, the fixed delay unit receiving a trigger signal output from the comparison latch circuit and delaying the trigger signal for a fixed time before outputting the trigger signal to the differential amplifier to trigger the differential amplifier to operate.

5. The analog-to-digital converter of claim 1, wherein the differential amplifier comprises a first NMOS transistor, a second NMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, the sources of the first NMOS transistor and the second NMOS transistor being coupled to the drain of the fifth NMOS transistor, the source of the fifth NMOS transistor being grounded, the drain of the third PMOS transistor being coupled to the drain of the first NMOS transistor, the drain of the fourth PMOS transistor being coupled to the drain of the second NMOS transistor, the sources of the third PMOS transistor and the fourth PMOS transistor being coupled to a supply voltage terminal, the gates of the first PMOS transistor receiving the sampling voltage, the gates of the second NMOS transistor receiving the switching voltage, the gates of the third PMOS transistor and the fourth PMOS transistor being coupled to the gate of the fourth PMOS transistor, the gates of the third PMOS transistor and the fifth PMOS transistor receiving a clock signal.

6. The analog-to-digital converter of claim 5, wherein the comparison latch circuit comprises a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, the source of the ninth NMOS transistor, the eleventh NMOS transistor and the twelfth NMOS transistor being grounded, the drain of the ninth NMOS transistor being coupled to the drain of the eleventh NMOS transistor, the drain of the seventh PMOS transistor and the gate of the tenth NMOS transistor, the drain of the tenth NMOS transistor being coupled to the drain of the twelfth PMOS transistor, the gate of the eleventh NMOS transistor being coupled to the drain of the ninth NMOS transistor, the gate of the eleventh NMOS transistor being coupled to the drain of the third PMOS transistor, the gate of the twelfth NMOS transistor being coupled to the drain of the fourth NMOS transistor, the drain of the seventh PMOS transistor being coupled to the drain of the PMOS transistor, the drain of the seventh PMOS transistor being coupled to the drain of the NMOS transistor.

7. The analog-to-digital converter of claim 6, wherein when the level of the steady signal changes to turn on the sixth PMOS transistor, the voltage output on the drain of the ninth NMOS transistor is used as the comparison result.