CN102130668A - Time-delay circuit - Google Patents
Time-delay circuit Download PDFInfo
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- CN102130668A CN102130668A CN2010100273227A CN201010027322A CN102130668A CN 102130668 A CN102130668 A CN 102130668A CN 2010100273227 A CN2010100273227 A CN 2010100273227A CN 201010027322 A CN201010027322 A CN 201010027322A CN 102130668 A CN102130668 A CN 102130668A
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Abstract
The invention discloses a time-delay circuit. In the invention, a first PMOS (P-channel Metal Oxide Semiconductor) tube, a second NMOS (N-channel metal oxide semiconductor) tube, a first current source circuit, a second power supply circuit and a first capacitor form a first capacitance charge and discharge switching circuit; a third PMOS tube, a fourth NMOS tube, a third current source circuit, a fourth current source circuit and a second capacitor form a second capacitance charge and discharge switching circuit; and an input signal is output sequentially through the first capacitance charge and discharge switching circuit, a first buffer, the second capacitance charge and discharge switching circuit and a second buffer or a phase inverter. The time-delay circuit eliminates the influence of process offsets by utilizing the time delay of the two capacitance charge and discharge switching circuits to mutually compensate so as to ensure that the time delay is more precise.
Description
Technical field
The present invention relates to semiconductor integrated circuit, particularly a kind of delay circuit.
Background technology
The application of delay circuit in a lot of integrated circuit IPs (Intellectual Property) is very extensive, accurate delay circuit can improve the performance of integrated circuit IP, the rate of finished products of raising wafer, particularly in NVM (Non-Volatile Memory nonvolatile memory) field, delay circuit can improve the reading speed of NVM accurately.
Traditional delay circuit is directly to utilize the delay accumulation of inverter to produce required time-delay (as shown in Figure 1), or utilizes reference current source that capacitor charge and discharge is produced required time-delay (as shown in Figure 2).Because the turnover voltage of buffer or inverter is subjected to the influence of supply voltage and process deviation very big), so delay circuit shown in Figure 1 is very sensitive to process deviation, and delay circuit shown in Figure 2 is very sensitive to supply voltage.Therefore traditional time-delay that delay circuit produced is bigger in the different condition lower deviation, and the time-delay precision is not high.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of delay circuit, can produce the less time-delay of deviation accurately.
For solving the problems of the technologies described above, delay circuit of the present invention comprises P transistor npn npn the one PMOS pipe, N transistor npn npn the 2nd NMOS pipe, P transistor npn npn the 3rd PMOS pipe, N transistor npn npn the 4th NMOS pipe, first buffer, second buffer or inverter, first electric capacity, second electric capacity, first current source circuit, second current source circuit, the 3rd current source circuit, the 4th current source circuit;
The grid short circuit of the grid of a described PMOS pipe, the 2nd NMOS pipe is used to connect the input signal end, the source shorted of same the 2nd NMOS pipe of the drain electrode of the one PMOS pipe also connects the input of first buffer and an end of first electric capacity, the source electrode of a described PMOS pipe connects supply voltage through first current source circuit, described the 2nd NMOS pipe drains through the second current source circuit ground connection other end ground connection of described first electric capacity;
The grid short circuit of the grid of described the 3rd PMOS pipe, the 4th NMOS pipe is in the output of first buffer, the source shorted of same the 4th NMOS pipe of the drain electrode of the 3rd PMOS pipe also connects the input of second buffer or inverter and an end of second electric capacity, the source electrode of described the 3rd PMOS pipe connects supply voltage through the 3rd current source circuit, the drain electrode of described the 4th NMOS pipe is through the 4th current source circuit ground connection, the other end ground connection of described second electric capacity, the output of described second buffer or inverter is as the delay circuit output;
The one PMOS pipe, the 2nd NMOS pipe, first current source circuit, second current source circuit, first electric capacity are formed the first capacitor charge and discharge switching circuit, and the 3rd PMOS pipe, the 4th NMOS pipe, the 3rd current source circuit, the 4th current source circuit, second electric capacity are formed the second capacitor charge and discharge switching circuit; The charge and discharge time-delay of described two capacitor charge and discharge switching circuits is much larger than rising, the decline time-delay of first buffer, second buffer or inverter; The rising and the decline turnover voltage of described first buffer, second buffer or inverter are identical; The electric current of described second current source circuit is directly proportional with supply voltage; The electric current of described the 4th current source circuit is directly proportional with supply voltage; Described first electric capacity equals the ratio of second electric capacity with the 3rd current source current with the ratio of second current source current; Described first electric capacity equals the ratio of second electric capacity with the 4th current source current with the ratio of first current source current.
The charge and discharge time-delay of described two capacitor charge and discharge switching circuits is more than or equal to 10 times of the rising of described first buffer, second buffer or inverter, the time-delay that descends.
Delay circuit of the present invention, utilize two sections capacitor charge and discharge switching circuit time-delays influence of compensation elimination process deviation mutually, and the current source circuit that is directly proportional with supply voltage of utilization is eliminated the influence of supply voltage to capacitor charge and discharge method produces one section time-delay that has nothing to do with supply voltage and process deviation, can make time-delay more accurate, reduced by the influence of supply voltage and process deviation, thus can improve integrated circuit IP performance (as the reading speed that improves NVM IP etc.), improve the rate of finished products of wafer.
Description of drawings
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is a kind of traditional delay circuit;
Fig. 2 is another kind of traditional delay circuit;
Fig. 3 is delay circuit one an execution mode schematic diagram of the present invention;
Fig. 4 is the sequential chart of delay circuit shown in Figure 3;
Fig. 5 is another execution mode schematic diagram of delay circuit of the present invention.
Embodiment
Delay circuit one execution mode of the present invention comprises P transistor npn npn the one PMOS pipe M1, N transistor npn npn the 2nd NMOS pipe M2, P transistor npn npn the 3rd PMOS pipe M3, N transistor npn npn the 4th NMOS pipe M4, first buffer, second buffer, first capacitor C 1, second capacitor C 2, first current source circuit, second current source circuit, the 3rd current source circuit, the 4th current source circuit as shown in Figure 3;
The grid short circuit of a described PMOS pipe M1, the 2nd NMOS pipe M2 is used to connect input signal end in, the drain electrode of the one PMOS pipe M1 is managed the source shorted of M2 and is met the input A of the first buffer M1 and an end of first capacitor C 1 with the 2nd NMOS, the source electrode of described PMOS pipe M1 meets supply voltage VDD through first current source circuit, described the 2nd NMOS pipe M2 drains through the second current source circuit ground connection other end ground connection of described first capacitor C 1;
The grid short circuit of the grid of described the 3rd PMOS pipe M3, the 4th NMOS pipe M4 is in the output B of first buffer, the drain electrode of the 3rd PMOS pipe M3 is managed the source shorted of M4 and is met the input C of second buffer and an end of second capacitor C 2 with the 4th NMOS, the source electrode of described the 3rd PMOS pipe M3 meets supply voltage VDD through the 3rd current source circuit, described the 4th NMOS pipe M4 drain electrode is through the 4th current source circuit ground connection, the other end ground connection of described second capacitor C 2, the output of described buffer is as delay circuit output out;
The one PMOS pipe M1, the 2nd NMOS pipe M2, first current source circuit, second current source circuit, first capacitor C 1 are formed the first capacitor charge and discharge switching circuit; When input signal end in becomes low level by high level, the one PMOS pipe M1 conducting, the 2nd NMOS pipe M2 disconnects, 1 charging of 1 pair first capacitor C of the first current source circuit electric current I, first buffer output high level after the input A of first buffer level reaches its rising turnover voltage V1, the charging time-delay of the first capacitor charge and discharge switching circuit is T1 (promptly the voltage on first electric capacity is charged to the time of the first buffer rising turnover voltage V1 by 0V); When input signal end in becomes high level by low level, the one PMOS pipe M1 disconnects, the 2nd NMOS pipe M2 conducting, first capacitor C 1 is discharged over the ground by the second current source circuit electric current I 2, the first buffer output low level after the input A of first buffer level reaches its decline turnover voltage V1 ', the discharge time-delay of the first capacitor charge and discharge switching circuit is T1 ' (promptly the voltage on first electric capacity is discharged into the time of the first buffer decline turnover voltage V1 ' by supply voltage VDD);
In like manner, the 3rd PMOS pipe M3, the 4th NMOS pipe M4, the 3rd current source circuit, the 4th current source circuit, second capacitor C 2 are formed the second capacitor charge and discharge switching circuit; The charging time-delay of the second capacitor charge and discharge switching circuit is T2 (promptly the voltage on second electric capacity is charged to the time of the second buffer rising turnover voltage V2 by 0V), and the discharge time-delay of the second capacitor charge and discharge switching circuit is T2 ' (promptly the voltage on second electric capacity is discharged into the time of the second buffer decline turnover voltage V2 ' by supply voltage VDD);
The decline time-delay of first buffer is T3, and the time-delay of rising is T3 ', and the decline time-delay of second buffer is T4, and the time-delay of rising is T4 ';
Wherein, the charge and discharge of described two capacitor charge and discharge switching circuits time-delays (T1, T1 ', T2, T2 ') are much larger than the rising of described first buffer, the time-delay that descends (T3 ', T3) and the rising of described second buffer, the time-delay that descends (T4 ', T4), according to the specific requirement of delay circuit precision, the charge and discharge of capacitor charge and discharge switching circuit time-delays can be for more than or equal to the rising of buffer, the time-delay that descends 10 times or greater than the rising of buffer, the time-delay that descends 100 times or greater than the rising of buffer, the time-delay that descends 1500 times; The rising of described first buffer, two buffers of second buffer and the identical V1=V1 ' of decline turnover voltage=V2=V2 '; The described second current source circuit electric current I 2 is with supply voltage VDD be directly proportional (I2=VDD/R, R are constant); Described the 4th current source circuit electric current I 4 is with supply voltage VDD be directly proportional (I4=VDD/R ', R ' is a constant); Described first capacitor C 1 equals the ratio (C2/I3=C1/I2) of second capacitor C 2 with the 3rd current source current I3 with the ratio of the second current source current I2; Described first capacitor C 1 equals the ratio (C1/I1-C2/I4) of second capacitor C 2 with the 4th current source current I4 with the ratio of the first current source current I1.
The sequential of delay circuit shown in Figure 3 as shown in Figure 4.Input signal end in rising edge to the time-delay Trise of delay circuit output out rising edge is:
T
rise＝T1’+T2+T3+T4’
Input signal end in trailing edge is to the time-delay T of delay circuit output out trailing edge
FallFor:
T
fall＝T1+T2’+T3’+T4
Because the charge and discharge of two capacitor charge and discharge switching circuits time-delays (T1, T1 ', T2, T2 ') are much larger than the rising of two buffers, the time-delay that descends (T3 ', T3, T4 ', T4), therefore
T
rise≈T1’+T2＝C1*(VDD-V1)/I2+C2*V1/I3＝VDD*C1/I2+V1*(C2/I3-C1/I2)
T
Fall≈ T1+T2 '=C1*V1/I1+C2* (VDD-V1)/I4=VDD*C2/I4+V1* (C1/I1-C2/I4) is because C2/I3=C1/I2, C1/I1-C2/I4, and I2=VDD/R, I4=VDD/R ' therefore can get:
T
rise≈VDD*C1/(VDD/R)＝C1*R
T
fall≈VDD*C2/(VDD/R’)＝C2*R’
As seen input signal end in rising edge is to the time-delay T of delay circuit output out rising edge
RiseAnd input signal end in trailing edge is to the time-delay T of delay circuit output out trailing edge
FallAll do not have direct relation with supply voltage VDD and turnover voltage, the deviation of time-delay can be smaller.
Another execution mode of delay circuit of the present invention as shown in Figure 4, the difference of delay circuit shown in Figure 4 and delay circuit shown in Figure 3 is, second buffer among Fig. 3 is replaced with an inverter, the drain electrode of the 3rd PMOS pipe M3 is managed the source shorted of M4 and is met the input C of described inverter and an end of second capacitor C 2 with the 4th NMOS, and the output of described inverter is as delay circuit output out.The charge and discharge time-delays (T1, T1 ', T2, T2 ') of described two capacitor charge and discharge switching circuits are much larger than rising, the decline time-delay of described inverter, according to the specific requirement of delay circuit precision, the charge and discharge of capacitor charge and discharge switching circuit time-delays can be for more than or equal to the rising of described inverter, the time-delay that descends 10 times or greater than the rising of inverter, the time-delay that descends 100 times or greater than the rising of inverter, the time-delay that descends 1500 times; The rising and the decline turnover voltage of described first buffer, inverter are identical.Making second buffer into inverter can obtain, with the irrelevant input signal end in rising edge of supply voltage VDD and process deviation to the time-delay of delay circuit output out trailing edge and the time-delay that has nothing to do with supply voltage VDD and process deviation from input signal end in trailing edge to delay circuit output out rising edge.
Delay circuit of the present invention, utilize two sections capacitor charge and discharge switching circuit time-delays influence of compensation elimination process deviation mutually, and the current source circuit that is directly proportional with supply voltage VDD of utilization is eliminated the influence of supply voltage to capacitor charge and discharge method produces one section time-delay that has nothing to do with supply voltage and process deviation, can make time-delay more accurate, reduced by the influence of supply voltage and process deviation, thus improve integrated circuit IP performance (as the reading speed that improves NVM IP etc.), improve the rate of finished products of wafer.
Claims (4)
1. delay circuit, it is characterized in that, comprise P transistor npn npn the one PMOS pipe, N transistor npn npn the 2nd NMOS pipe, P transistor npn npn the 3rd PMOS pipe, N transistor npn npn the 4th NMOS pipe, first buffer, second buffer or inverter, first electric capacity, second electric capacity, first current source circuit, second current source circuit, the 3rd current source circuit, the 4th current source circuit;
The grid short circuit of the grid of a described PMOS pipe, the 2nd NMOS pipe is used to connect the input signal end, the source shorted of same the 2nd NMOS pipe of the drain electrode of the one PMOS pipe also connects the input of first buffer and an end of first electric capacity, the source electrode of a described PMOS pipe connects supply voltage through first current source circuit, described the 2nd NMOS pipe drains through the second current source circuit ground connection other end ground connection of described first electric capacity;
The grid short circuit of the grid of described the 3rd PMOS pipe, the 4th NMOS pipe is in the output of first buffer, the source shorted of same the 4th NMOS pipe of the drain electrode of the 3rd PMOS pipe also connects the input of second buffer or inverter and an end of second electric capacity, the source electrode of described the 3rd PMOS pipe connects supply voltage through the 3rd current source circuit, the drain electrode of described the 4th NMOS pipe is through the 4th current source circuit ground connection, the other end ground connection of described second electric capacity, the output of described second buffer or inverter is as the delay circuit output;
The one PMOS pipe, the 2nd NMOS pipe, first current source circuit, second current source circuit, first electric capacity are formed the first capacitor charge and discharge switching circuit, and the 3rd PMOS pipe, the 4th NMOS pipe, the 3rd current source circuit, the 4th current source circuit, second electric capacity are formed the second capacitor charge and discharge switching circuit; The charge and discharge time-delay of described two capacitor charge and discharge switching circuits is much larger than rising, the decline time-delay of first buffer, second buffer or inverter; The rising and the decline turnover voltage of described first buffer, second buffer or inverter are identical; The electric current of described second current source circuit is directly proportional with supply voltage; The electric current of described the 4th current source circuit is directly proportional with supply voltage; Described first electric capacity equals the ratio of second electric capacity with the 3rd current source current with the ratio of second current source current; Described first electric capacity equals the ratio of second electric capacity with the 4th current source current with the ratio of first current source current.
2. delay circuit according to claim 1 is characterized in that, the charge and discharge time-delay of described two capacitor charge and discharge switching circuits is more than or equal to 10 times of the rising of described first buffer, second buffer or inverter, the time-delay that descends.
3. delay circuit according to claim 1 is characterized in that, the charge and discharge time-delay of described two capacitor charge and discharge switching circuits is more than or equal to 100 times of the rising of described first buffer, second buffer or inverter, the time-delay that descends.
4. delay circuit according to claim 1 is characterized in that, the charge and discharge time-delay of described two capacitor charge and discharge switching circuits is more than or equal to 1500 times of the rising of described first buffer, second buffer or inverter, the time-delay that descends.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN2010100273227A CN102130668A (en) | 2010-01-20 | 2010-01-20 | Time-delay circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010100273227A CN102130668A (en) | 2010-01-20 | 2010-01-20 | Time-delay circuit |
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Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102299701A (en) * | 2011-08-23 | 2011-12-28 | 北京兆易创新科技有限公司 | Time-delay unit circuit |
| CN102790606A (en) * | 2012-06-07 | 2012-11-21 | 杭州东城图像技术有限公司 | Digital controlled analog modulation circuit |
| CN103066962A (en) * | 2012-12-21 | 2013-04-24 | 上海宏力半导体制造有限公司 | Time-delay circuit |
| WO2013167027A2 (en) * | 2013-03-04 | 2013-11-14 | 中兴通讯股份有限公司 | Power switching circuit and terminal |
| CN105515549A (en) * | 2014-09-26 | 2016-04-20 | 原景科技股份有限公司 | Single trigger circuit |
| CN107241087A (en) * | 2017-05-27 | 2017-10-10 | 上海吉锝芯微电子有限公司 | A kind of delay circuit |
| CN108055024A (en) * | 2018-01-31 | 2018-05-18 | 电子科技大学 | A kind of compact delay circuit |
| CN108347232A (en) * | 2017-01-25 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | Delay circuit and memory circuit |
| CN108806744A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of delay generation circuit and nonvolatile memory read timing sequence generating circuit |
| CN110798184A (en) * | 2019-12-02 | 2020-02-14 | 深圳清华大学研究院 | Time delay circuit unit |
| CN110971221A (en) * | 2018-09-29 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit |
| CN114583676A (en) * | 2022-03-29 | 2022-06-03 | 拓尔微电子股份有限公司 | Circuit and method for reducing output voltage overshoot of LDO (low dropout regulator) |
| CN114978134A (en) * | 2022-05-06 | 2022-08-30 | 上海韬润半导体有限公司 | Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator |
| CN117544140A (en) * | 2024-01-09 | 2024-02-09 | 杭州米芯微电子有限公司 | Delay circuit and chip stable along with power supply voltage change |
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| US20050195010A1 (en) * | 2004-02-10 | 2005-09-08 | Stmicroelectronics S.R.L. | Time-delay circuit |
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| CN101242172A (en) * | 2007-02-08 | 2008-08-13 | 佛山市顺德区顺达电脑厂有限公司 | Delay circuit |
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| US20050195010A1 (en) * | 2004-02-10 | 2005-09-08 | Stmicroelectronics S.R.L. | Time-delay circuit |
| US20080180154A1 (en) * | 2007-01-30 | 2008-07-31 | Andigilog, Inc | Digital delay circuit |
| CN101242172A (en) * | 2007-02-08 | 2008-08-13 | 佛山市顺德区顺达电脑厂有限公司 | Delay circuit |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102299701A (en) * | 2011-08-23 | 2011-12-28 | 北京兆易创新科技有限公司 | Time-delay unit circuit |
| CN102790606A (en) * | 2012-06-07 | 2012-11-21 | 杭州东城图像技术有限公司 | Digital controlled analog modulation circuit |
| CN102790606B (en) * | 2012-06-07 | 2015-11-18 | 杭州东城图像技术有限公司 | Numerically controlled analog modulation circuit |
| CN103066962A (en) * | 2012-12-21 | 2013-04-24 | 上海宏力半导体制造有限公司 | Time-delay circuit |
| CN103066962B (en) * | 2012-12-21 | 2016-03-09 | 上海华虹宏力半导体制造有限公司 | delay circuit |
| WO2013167027A2 (en) * | 2013-03-04 | 2013-11-14 | 中兴通讯股份有限公司 | Power switching circuit and terminal |
| WO2013167027A3 (en) * | 2013-03-04 | 2014-02-06 | 中兴通讯股份有限公司 | Power switching circuit and terminal |
| CN105515549A (en) * | 2014-09-26 | 2016-04-20 | 原景科技股份有限公司 | Single trigger circuit |
| CN108347232A (en) * | 2017-01-25 | 2018-07-31 | 中芯国际集成电路制造(上海)有限公司 | Delay circuit and memory circuit |
| CN108806744A (en) * | 2017-05-05 | 2018-11-13 | 中芯国际集成电路制造(上海)有限公司 | A kind of delay generation circuit and nonvolatile memory read timing sequence generating circuit |
| CN108806744B (en) * | 2017-05-05 | 2020-11-27 | 中芯国际集成电路制造(上海)有限公司 | Delay generating circuit and nonvolatile memory read timing generating circuit |
| CN107241087B (en) * | 2017-05-27 | 2023-06-02 | 上海吉锝芯微电子有限公司 | Time delay circuit |
| CN107241087A (en) * | 2017-05-27 | 2017-10-10 | 上海吉锝芯微电子有限公司 | A kind of delay circuit |
| CN108055024A (en) * | 2018-01-31 | 2018-05-18 | 电子科技大学 | A kind of compact delay circuit |
| CN110971221A (en) * | 2018-09-29 | 2020-04-07 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit |
| CN110971221B (en) * | 2018-09-29 | 2023-10-24 | 中芯国际集成电路制造(上海)有限公司 | Time delay circuit |
| CN110798184A (en) * | 2019-12-02 | 2020-02-14 | 深圳清华大学研究院 | Time delay circuit unit |
| CN110798184B (en) * | 2019-12-02 | 2023-02-10 | 深圳清华大学研究院 | Time delay circuit unit |
| CN114583676B (en) * | 2022-03-29 | 2023-09-12 | 拓尔微电子股份有限公司 | Circuit and method for reducing LDO output voltage overshoot |
| CN114583676A (en) * | 2022-03-29 | 2022-06-03 | 拓尔微电子股份有限公司 | Circuit and method for reducing output voltage overshoot of LDO (low dropout regulator) |
| CN114978134A (en) * | 2022-05-06 | 2022-08-30 | 上海韬润半导体有限公司 | Switch buffer circuit, temperature compensation control circuit and voltage-controlled oscillator |
| CN117544140A (en) * | 2024-01-09 | 2024-02-09 | 杭州米芯微电子有限公司 | Delay circuit and chip stable along with power supply voltage change |
| CN117544140B (en) * | 2024-01-09 | 2024-04-12 | 杭州米芯微电子有限公司 | Along with the change of power supply voltage Stable time delay circuit and chip |
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Effective date of registration: 20140110 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20110720 |