CN106990367A - SoC on-chip power supply noise monitoring systems - Google Patents
SoC on-chip power supply noise monitoring systems Download PDFInfo
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- CN106990367A CN106990367A CN201710364643.8A CN201710364643A CN106990367A CN 106990367 A CN106990367 A CN 106990367A CN 201710364643 A CN201710364643 A CN 201710364643A CN 106990367 A CN106990367 A CN 106990367A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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- G01R31/40—Testing power supplies
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Abstract
The present invention relates to a kind of SoC on-chip power supplies noise monitoring system, including dropping equipment, difference sampling hold circuit and signal processing apparatus, the input positive pole and input negative pole connection dropping equipment of difference sampling hold circuit, output cathode and output negative pole the connection signal processing apparatus of difference sampling hold circuit.Dropping equipment is depressured and converted to the SoC on-chip power supply signals of access, obtain differential signal and input to difference sampling hold circuit, differential signal is converted into discrete voltage signal and exported to signal processing apparatus by difference sampling hold circuit, and signal processing apparatus carries out Treatment Analysis to discrete voltage signal and obtains supply voltage data.By directly being sampled and being analyzed to power supply voltage signal, the change of supply voltage is reflected without the delay of indirect measuring circuit, monitoring in real time and size and the change of analysis SoC on-chip power supply voltages can be achieved, monitoring accuracy is high.
Description
Technical field
The present invention relates to microelectronics technology, more particularly to a kind of SoC on-chip power supplies noise monitoring system.
Background technology
With the development of microelectric technique, integrated level, complexity and the work of integrated circuit especially on-chip system (SoC)
Speed is all being greatly improved, and its reliability is attracted wide attention.SoC can be by switching noise, electromagnetic interference, voltage when working
The influence of the various parasitics such as source change, crosstalk, ground bounce and Substrate Coupling Noise, or when SoC is operated in
When very in rugged environment, it can be influenceed by thunder and lightning, radiation and violent temperature change etc., these factors can make inside SoC
There is obvious change and fluctuated in some crucial voltage signals, and the irregular working of chip can be caused when serious, signal is influenceed
Integrality, can more likely cause SoC to fail.The problem of in order to avoid or slow down the above, to SoC noise signals, it is necessary to enter
The accurate measurement of row, to the interference suffered by SoC could accurately analyze and predict when chip the shape of irregular working occurs
State.
SoC power supply signals are almost joined directly together with all modules in circuit, working condition of its fluctuating change to SoC
Influence be especially apparent, therefore, in the SoC courses of work, while being monitored to its power supply noise, help to maintain SoC works
Make in stably state, and prevent mains fluctuations excessive to chip cause damage.Traditional SoC power supply noise monitoring methods
It is that one of circuit module is by several delay unit groups very sensitive to mains voltage variations using two circuit modules
Mains voltage variations very insensitive delay unit are made up of several into, another circuit module.When same signal point
An obvious phase difference can not be produced after two circuit modules, by the size for measuring this phase, it is possible to monitor
Go out mains voltage variations whether there is, i.e. track collapse constantly too high or too low beyond certain scope, or supply voltage.It is this
Method can only detect supply voltage is whether there is more than certain scope, can not accurately measure the size of supply voltage, exist
Monitor the low shortcoming of accuracy.
The content of the invention
Based on this, it is necessary in view of the above-mentioned problems, providing a kind of monitoring accuracy high SoC on-chip power supply noise monitoring system
System.
A kind of SoC on-chip power supplies noise monitoring system, including dropping equipment, difference sampling hold circuit and signal processing device
Put, the input positive pole and input negative pole of the difference sampling hold circuit connect the dropping equipment, and the difference sampling is kept
The output cathode and output negative pole of circuit connect the signal processing apparatus,
The dropping equipment is used to the SoC on-chip power supply signals of access are depressured and converted, and obtains differential signal simultaneously
Input is to the difference sampling hold circuit, and the difference sampling hold circuit is used to the differential signal being converted into discrete electrical
Press signal and export to the signal processing apparatus, the signal processing apparatus is used to handle the discrete voltage signal
Analysis obtains supply voltage data.
Above-mentioned SoC on-chip power supplies noise monitoring system, dropping equipment the SoC on-chip power supplies signal of access is carried out decompression and
Conversion, obtains differential signal and inputs to difference sampling hold circuit, difference sampling hold circuit by differential signal be converted into from
Dissipate voltage signal and export to signal processing apparatus, signal processing apparatus carries out Treatment Analysis to discrete voltage signal and obtains power supply
Voltage data.By directly being sampled and being analyzed to power supply voltage signal, reflect electricity without the delay of indirect measuring circuit
The change of source voltage, can be achieved monitoring in real time and size and the change of analysis SoC on-chip power supply voltages, and monitoring accuracy is high.
Brief description of the drawings
Fig. 1 is the structure chart of SoC on-chip power supply noise monitoring systems in an embodiment；
Fig. 2 is the schematic diagram of dropping equipment in an embodiment；
Fig. 3 is the schematic diagram of difference sampling hold circuit in an embodiment；
Fig. 4 is the schematic diagram of the first bootstrapped switch in an embodiment；
Fig. 5 is the schematic diagram of operational amplifier in an embodiment；
Fig. 6 is the schematic diagram of the not overlapping clock of three-phase in an embodiment；
Fig. 7 is the clock pulses figure of the not overlapping clock of three-phase in an embodiment；
Fig. 8 is the structure chart of signal processing apparatus in an embodiment；
Fig. 9 is the structure chart of signal processing apparatus in another embodiment.
Embodiment
In one embodiment, a kind of SoC on-chip power supplies noise monitoring system, as shown in figure 1, including dropping equipment 100,
Difference sampling hold circuit 200 and signal processing apparatus 300, the input positive pole Vin+ of difference sampling hold circuit 200 and input
Negative pole Vin- connections dropping equipment 110, output cathode Vout+ and output negative pole the Vout- connection of difference sampling hold circuit 200
Signal processing apparatus 300.Dropping equipment 100 is used to the SoC on-chip power supply signals of access are depressured and converted, and obtains difference
Signal is simultaneously inputted to difference sampling hold circuit 200, and difference sampling hold circuit 200 is used to differential signal being converted into discrete electrical
Press signal and export to signal processing apparatus 300, signal processing apparatus 300 is used to obtain discrete voltage signal progress Treatment Analysis
To supply voltage data.
Power supply signal Vin_noise for the circuit change to be monitored power supply signal.It is defeated due to subsequent conditioning circuit module
Go out scope to be limited by circuit structure and power supply voltage swing, it is impossible to handle the excessive signal of voltage magnitude, therefore electricity
Source signal Vin_noise, which will first pass through dropping equipment 100 and voltage magnitude is reduced and is converted into differential signal and is input to difference, to be adopted
Sample holding circuit 200.In addition, difference sampling hold circuit 200 can also stable connection voltage source VDD_quiet, using stable electricity
Potential source VDD_quiet powers.The power supply signal of consecutive variations is converted into discrete voltage signal by difference sampling hold circuit 200
Output, then by follow-up signal processing apparatus 300 discrete signal is handled and analyzed the situation of change of power supply signal.
Signal processing apparatus 300 can be stored in memory or according to supply voltage number after processing obtains supply voltage data
According to early warning analysis is carried out, SoC system stalls are controlled when supply voltage occurs abnormal.
The specific structure of dropping equipment 100 and decompression mode be not unique, in one embodiment, as shown in Fig. 2 decompression
Device 100 includes divider resistance component 120 and first switch pipe NM104.The connection difference sampling of divider resistance component 120 keeps electricity
Road 200 and first switch pipe NM104 input；First switch pipe NM104 control end connection difference sampling hold circuit
200, first switch pipe NM104 output head grounding.
First switch pipe NM104 can be metal-oxide-semiconductor or triode etc., in the present embodiment, and first switch pipe NM104 is N ditches
Road metal-oxide-semiconductor.The concrete structure of divider resistance component 120 is not also unique, in one embodiment, with continued reference to Fig. 2, divider resistance
Component 120 includes first resistor R101, second resistance R102 and 3rd resistor R103.First resistor R101, second resistance R102
With 3rd resistor R103 series connection, first resistor R101 other ends access power supply signal Vin_noise, the 3rd resistor R103 other ends
Connect first switch pipe NM104 input；First resistor R101 and second resistance R102 common port connection difference sampling are protected
The common port connection difference sampling for holding input the positive pole Vin+, second resistance R102 and 3rd resistor R103 of circuit 200 keeps electricity
The input negative pole Vin- on road 200.
Dropping equipment 100 carries out partial pressure using resistance R101, R102 and R103 of three series connection, and in view of subordinate
Input/output bound, using interlaminated resistance R102 both end voltage as the differential input voltage of next stage, protects dropping equipment 100
The linearisation of height is held in order to avoid introducing non-linear distortion in pressure reduction.The magnitude of resistance R101, R102 and R103 resistance can
Reasonably selected according to the actual requirements, resistance is too small to bring unnecessary quiescent dissipation, and reduces the negative of voltage source
Carry, observation circuit is inherently had a great impact to voltage signal change.Second resistance R102 both end voltages are specifically and subordinate
The sampling capacitance of difference sampling hold circuit 200 is joined directly together, equivalent electric by resistance R101, R102, R103 and sampling into one
Hold the RC loops of composition, in the case where the capacitance amount of exhausting of sampling capacitance is small, if resistance is larger, sampling process can be influenceed
The stabilization time of middle input signal and cause larger dynamic error, limit the operating rate and precision of integrated circuit.In decompression
The switch controlled in device 100 in one NMOS tube work of series connection, control dropping equipment 100 is turned in sampling process, kept
Journey reduces unnecessary power consumption when breaking.The breadth length ratio of NMOS tube will the amount of exhausting it is big, make the equivalent resistance of NMOS tube far small
In the value of resistance, it is set to can be ignored to the linearity error that circuit is brought.
The specific structure of difference sampling hold circuit 200 and sample mode are nor unique, in one embodiment, such as
Shown in Fig. 3, difference sampling hold circuit 200 includes the bootstrapping of the first bootstrapped switch (Boostrapped Switch) 220, second and opened
Close 240, operational amplifier 260, three-phase and do not overlap clock 280, the first controlling switch S201, the second controlling switch S202, the 3rd
Controlling switch S203, the 4th controlling switch S204, the 5th controlling switch S205, the 6th controlling switch S206, the 7th controlling switch
S207, the first electric capacity C207, the second electric capacity C208, the 3rd electric capacity C209 and the 4th electric capacity C210, three-phase do not overlap clock 280 and wrapped
Include the first clock end, second clock end and the 3rd clock end.Specifically, three-phase does not overlap the access inceptive impulse signal of clock 280
CLKin, and clock signal clk 1, CLK2 and CLK3 are exported by the first clock end, second clock end and the 3rd clock end respectively.
Accordingly, first switch pipe NM104 control end connection three-phase does not overlap the first clock end of clock 280 in dropping equipment 100.
The input Vin of first bootstrapped switch 220 as difference sampling hold circuit 200 input positive pole Vin+, specifically
Connect the common port of first resistor R101 and second resistance R102 in dropping equipment 100, the output end of the first bootstrapped switch 220
Vout passes through the in-phase input end of the first electric capacity C207 concatenation operations amplifier 260, the control end connection of the first bootstrapped switch 220
Three-phase does not overlap the first clock end of clock 280；The input Vin of second bootstrapped switch 240 is used as difference sampling hold circuit
Second resistance R102 and 3rd resistor R103 common port in 200 input negative pole Vin-, specific connection dropping equipment 100, the
The output end vo ut of two bootstrapped switches 240 is by the inverting input of the second electric capacity C208 concatenation operations amplifier 260, and second certainly
The control end connection three-phase for lifting switch 240 does not overlap the first clock end of clock 280；First controlling switch S201 one end connection the
The output end vo ut of one bootstrapped switch 220, the other end connects the output end vo ut of the second bootstrapped switch 240, the first controlling switch
S201 control end connection three-phase does not overlap the 3rd clock end of clock 280；The output negative pole of operational amplifier 260 and output are just
Pole connects signal processing apparatus respectively as the output cathode Vout+ and output negative pole Vout- of difference sampling hold circuit 200
300。
Second controlling switch S202, the 3rd controlling switch S203 and the 4th controlling switch S204 are sequentially connected in series rear two ends and connected
Meet first kind control voltage end Vin_bias；Second controlling switch S202 and the 3rd controlling switch S203 common port concatenation operation
The in-phase input end of amplifier 260, the 3rd controlling switch S203 and the 4th controlling switch S204 common port concatenation operation amplification
The inverting input of device；Second controlling switch S202 control end, the 3rd controlling switch S203 control end and the 4th control is opened
The control end for closing S204 is all connected with the second clock end that three-phase does not overlap clock 280.
5th controlling switch S205, the 6th controlling switch S206 and the 7th controlling switch S207 are sequentially connected in series rear two ends and connected
Meet Equations of The Second Kind control voltage end Vout_bias；5th controlling switch S205 and the 6th controlling switch S206 common port connection fortune
The output negative pole of amplifier is calculated, and passes through the in-phase input end of the 3rd electric capacity C209 concatenation operation amplifiers；6th controlling switch
The output cathode of S206 and the 7th controlling switch S207 common port concatenation operation amplifier, and pass through the 4th electric capacity C210 connections
The inverting input of operational amplifier, the 5th controlling switch S205 control end and the 7th controlling switch S207 control end connect
Connect the first clock end that three-phase does not overlap clock 280.
Sampling hold circuit can all be influenceed by clock feedthrough and channel charge injection, in high speed applications, due to wanting
It using the pipe that breadth length ratio is larger, can become apparent the phenomenon that clock feedthrough and channel charge inject.In the present embodiment, difference
The principle that sampling hold circuit 200 is sampled by using switching capacity bottom plate, will be by clock feedthrough and channel charge injection institute
The error of generation is converted into fixed imbalance, and is eliminated by differential configuration.Sampled using difference and switching capacity bottom plate
Structure, effectively eliminates error, reaches higher precision.Changed greatly simultaneously as the power supply signal gathered is one
Signal, therefore difference sampling hold circuit 200 is using the switching capacity sample circuit of charge redistribution type, suppresses operational amplifier
The skew of 260 common mode inputs, keeps amplifier to be operated in amplification region.Three-phase does not overlap clock 280 and produces three clock signals
CLK1, CLK2 and CLK3, wherein, rising edge of a pulse of the rising edge of a pulse earlier than clock signal clk 1 of clock signal clk 2, and
The pulse falling edge of clock signal clk 2 is later than the pulse falling edge of clock signal clk 1；Clock signal clk 3 is in clock signal
Low level state is in when CLK1 and clock signal clk 2 is high level.First bootstrapped switch 220, the second bootstrapped switch 240,
Five controlling switch S205 and the 7th controlling switch S207 subject clock signals CLK1 controls, the second controlling switch S202, the 3rd control
Switch S203 and the 4th controlling switch S204 subject clock signals CLK2 controls, the first controlling switch S201 subject clock signals CLK3 controls
System.By three tunnel clock signal control correspondence switch on and off, so as to adjust the state of difference sampling hold circuit 200, make difference
The power supply voltage signal of change is periodically converted into discrete voltage signal by sampling hold circuit 200.
The main function of first bootstrapped switch 220 and the second bootstrapped switch 240 is that reduction difference sampling hold circuit 200 is defeated
Enter the conducting resistance in loop, and make change and change of the conducting resistance resistance not with input voltage, improve the work of integrated circuit
Make speed and precision.First bootstrapped switch 220 is similar with the structure of the second bootstrapped switch 240, is with the first bootstrapped switch 220
Example, in one embodiment, as shown in figure 4, the first bootstrapped switch 220 includes second switch pipe PM201a, the 3rd switching tube
PM202a, the 4th switching tube PM203a, the 5th switching tube NM204a, the 6th switching tube NM205a, the 7th switching tube NM206a,
Eight switching tube NM207a, the 9th switching tube NM208a, the tenth switching tube NM209a, the 5th electric capacity C210a and the first phase inverter F0.
Second switch pipe PM201a control end and the 7th switching tube NM206a control end be all connected with three-phase not overlap when
First clock end of clock 280, second switch pipe PM201a input stable connection voltage source VDD_quiet, second switch pipe
PM201a output end connects the 7th switching tube NM206a input, and the 7th switching tube NM206a output end connection the 9th is opened
Close pipe NM208a input；3rd switching tube PM202a input stable connection voltage source VDD_quiet, the 3rd switching tube
PM202a output end connects the 4th switching tube PM203a input, and passes through the switching tube of the 5th electric capacity C210a connections the 8th
NM207a input, and the 7th switching tube NM206a and the 9th switching tube NM208a common port；First phase inverter F0's
Input connection three-phase does not overlap the first clock end of clock 280, and the first phase inverter F0 output end connects the 6th switching tube
The control end of NM205a control end and the 8th switching tube NM207a, the 8th switching tube NM207a output head grounding.
4th switching tube PM203a control end connection second switch pipe PM201a's and the 7th switching tube NM206a is public
End, the 4th switching tube PM203a output end connect the 3rd switching tube PM202a control end and the 5th switching tube NM204a it is defeated
Enter end；5th switching tube NM204a output end connects the 6th switching tube NM205a input, the 5th switching tube NM204a's
Control end stable connection voltage source VDD_quiet, the 6th switching tube NM205a output head grounding；9th switching tube NM208a's
The control end of control end and the tenth switching tube NM209a, is all connected with the 4th switching tube PM203a and the 5th switching tube NM204a public affairs
End altogether, the 9th switching tube NM208a output end connects the tenth switching tube NM209a input, the 9th switching tube NM208a and
Tenth switching tube NM209a common port is used as the input Vin of the first bootstrapped switch 220, the tenth switching tube NM209a output
Hold the output end vo ut as the first bootstrapped switch 220.
Each switching tube can be specifically metal-oxide-semiconductor or triode etc., in the present embodiment, and second switch pipe PM201a, the 3rd open
Pass pipe PM202a and the 4th switching tube PM203a is P-channel metal-oxide-semiconductor, the 5th switching tube NM204a, the 6th switching tube NM205a, the
Seven switching tube NM206a, the 8th switching tube NM207a, the 9th switching tube NM208a and the tenth switching tube NM209a are N-channel MOS
Pipe.
Specifically, when clock signal CLK1 is low level, the 8th switching tube NM207a and the 3rd switching tube PM202a are led
Logical, the 5th electric capacity C210a both end voltages are charged to voltage VDD by power supply, and now the 4th switching tube PM203a and the 9th is opened
Close pipe NM208a to disconnect, the 5th switching tube NM204a and the 6th switching tube NM205a conductings, the tenth switching tube NM209a gate voltages
For 0V, equivalent to open circuit；When clock signal CLK2 is high level, the 8th switching tube NM207a and the 3rd switching tube PM202a are disconnected
Open, the 4th switch PM203a and the 9th switching tube NM208a conductings, the 5th switching tube NM204a and the 6th switching tube NM205a are disconnected
Open, the 5th electric capacity C210a is connected in parallel on the tenth switching tube NM209a grid ends and input Vin, by the tenth switching tube NM209a grid
Source voltage is raised to VDD, reduces its conducting resistance, and does not change with the change of input voltage.
In one embodiment, operational amplifier 260 uses the fully differential folded common source and common grid inputted with N-channel MOS pipe
Operational amplifier, using cascode structure, can improve operational amplifier 200b output resistance, improve gain, reduce difference
The gain error of sampling hold circuit 200, improves system accuracy, and the structure of folding cascade operational amplifier is defeated
Enter scope larger, frequency characteristic is good, higher operating rate can be reached.Specifically, as shown in figure 5, operational amplifier 260 includes
Fully differential folded common source and common grid discharge circuit 262 and switched-capacitor CMFB circuit 264, fully differential folded common source and common grid amplifier
Circuit 262 connects the first bootstrapped switch 220, the second bootstrapped switch 240 and signal processing apparatus 300, switched-capacitor CMFB
The connection fully differential folded common source and common grid of circuit 264 discharge circuit 262 and three-phase do not overlap clock 280.Switched-capacitor CMFB
Circuit 264 is used for the output common mode voltage for stablizing operational amplifier 260.
In the present embodiment, fully differential folded common source and common grid discharge circuit 262 includes NMOS tube NM201b, NMOS tube
NM202b, NMOS tube NM203b, PMOS PM204b, PMOS PM205b, PMOS PM206b, PMOS PM207b, NMOS
Pipe NM208b, NMOS tube NM209b, NMOS tube NM210b, NMOS tube NM211b, electric capacity CL1 and electric capacity CL2.
NMOS tube NM201b grid is used as the in-phase input end of operational amplifier 260, NMOS tube NM203b grid work
For the inverting input of operational amplifier 260, NMOS tube NM202b grid Access Control voltage Vbias1, NMOS tube NM202b
Source ground, NMOS tube NM202b drain electrode connection NMOS tube NM201b source electrode and NMOS tube NM203b source electrode.PMOS
Pipe PM204b grid connection PMOS PM205b grid, PMOS PM204b source electrode and PMOS PM205b source electrode are equal
Stable connection voltage source VDD_quiet, PMOS PM204b drain electrode connection PMOS PM206b source electrode, PMOS PM205b
Drain electrode connection PMOS PM207b source electrode, PMOS PM206b grid connection PMOS PM207b grid, PMOS
PM206b drain electrode connection NMOS tube NM208b drain electrode, PMOS PM207b drain electrode connection NMOS tube NM209b drain electrode,
NMOS tube NM208b grid connection NMOS tube NM209b grid, NMOS tube NM208b source electrode connection NMOS tube NM210b's
Drain electrode, NMOS tube NM209b source electrode connection NMOS tube NM211b drain electrode, NMOS tube NM210b grid connection NMOS tube
NM211b grid, NMOS tube NM210b source electrode and NMOS tube NM211b source grounding.PMOS PM204b and PMOS
Pipe PM205b common port connecting valve electric capacity common mode feedback circuit 264, PMOS PM204b and PMOS PM206b's is public
End connection NMOS tube NM201b drain electrode, PMOS PM205b and PMOS PM207b common port connection NMOS tube NM203b's
Drain electrode.PMOS PM206b and NMOS tube NM208b common port as difference sampling hold circuit 200 output negative pole
Vout-, and be grounded by electric capacity CL1, PMOS PM207b and NMOS tube NM209b common port are used as difference sampling holding electricity
The output cathode Vout+ on road 200, and be grounded by electric capacity CL2.
Further, switched-capacitor CMFB circuit 264 includes electric capacity C212b, electric capacity C213b, electric capacity C214b, electricity
Hold C215b, switch S216b, switch S217b, switch S218b, switch S219b, switch S220b and switch S221b.That connects opens
Close the switch S218b and switch S221b of S216b and switch S219b, the switch S217b connected and switch S220b and series connection simultaneously
Connection, switchs S216b and switch S219b common port by electric capacity C214b connecting valves S217b and switch S220b common port,
The common port for switching S217b and switch S220b passes through electric capacity C215b connecting valves S218b and switch S221b common port；Open
The output cathode Vout+ of S216b other end connection difference sampling hold circuit 200 is closed, and passes through electric capacity C212b connecting valves
The S217b other end, switch S219b other end connection Equations of The Second Kind control voltage end Vout_bias；Switch the S217b other ends
PMOS PM204b and PMOS PM205b common port is connected, and passes through the electric capacity C213b connecting valves S218b other end；
The other end for switching S220b connects the 3rd class control voltage end Vdmfb_bias；The connection difference sampling of the S218b other ends is switched to protect
Hold the output negative pole Vout+ of circuit 200, switch S221b other end connection Equations of The Second Kind control voltage end Vout_bias.Switch
S216b, switch S217b and switch S218b control end connection three-phase do not overlap the 3rd clock end of clock 280, switch
S219b, switch S220b and switch S221b control end connection three-phase do not overlap the first clock end of clock 280.
The main function of the non-overlapping clock 280 of three-phase is to produce the non-overlapping clock of two phase place, and three-phase does not overlap clock
280 concrete structure is not also unique, in one embodiment, as shown in fig. 6, the not overlapping clock 280 of three-phase is same including first
Phase device T1, second are with phase device T2, the second phase inverter F1, the 3rd phase inverter F2, the 4th phase inverter F3, the 5th phase inverter F4, the 6th
Phase inverter F5, the first NAND gate NAND1, the second NAND gate NAND2, the first delayer DELAY1 and the second delayer DELAY2.
First accesses inceptive impulse signal CLKin with phase device T1 input and the second phase inverter F1 input, the
Together phase device T1 output end connects the first NAND gate NAND1 first input end, and the first NAND gate NAND1 output end passes through
The phase inverter F2 of first delayer DELAY1 connections the 3rd input, the second phase inverter F1 output end connects the second NAND gate
NAND2 first input end, the second NAND gate NAND2 output end passes through the phase inverter F3 of the second delayer DELAY2 connections the 4th
Input, the first NAND gate NAND1 the second input connection the second delayer DELAY2 and the 4th phase inverter F3 it is public
End, the second NAND gate NAND1 the second input connects the first delayer DELAY1 and the 3rd phase inverter F2 common port.
5th phase inverter F4 input connects the 3rd phase inverter F2 output end, the 5th phase inverter F4 output end conduct
Three-phase does not overlap the first clock end of clock 280, for exporting clock signal clk 1；Second with phase device T2 input connection the
One delayer DELAY1 and the 3rd phase inverter F2 common port, second with phase device T2 output end be used as three-phase not overlap clock
280 second clock end, for exporting clock signal clk 2；Hex inverter F5 input connects the defeated of the 4th phase inverter F3
Go out end, hex inverter F5 output end does not overlap the 3rd clock end of clock 280 as three-phase, for exporting clock signal
CLK3.Three-phase non-overlapping clock 280 access inceptive impulse signal CLKin, by inside with phase device, phase inverter, NAND gate and
The effect of delayer, exports three tunnel clock signals.Such as the sequential that Fig. 7 is clock signal clk 1, CLK2 and CLK3 in the present embodiment
Figure.It is appreciated that the form for the three tunnel clock signals that the non-overlapping clock 280 of three-phase is exported is nor uniquely, only need to meet
Differential signal is converted into discrete voltage signal by controllable difference sampling hold circuit 200.
The specific structure of signal processing apparatus 300 and signal processing are nor unique, in one embodiment, such as
Shown in Fig. 8, signal processing apparatus 300 includes analog-digital converter 310, memory 320 and arithmetic processor 330, analog-digital converter
310 connection difference sampling hold circuits 200 and memory 320, the connection memory 320 of arithmetic processor 330.
When SoC on-chip power supply noise monitoring systems are applied in fairly large on-chip system, analog-digital converter 310 is by electricity
The discrete signal of source voltage is converted into data signal and is stored in memory 320, then data are carried out by arithmetic processor 330
Analysis and processing, reach the change analyzed under supply voltage is disturbed, prediction and the effect of the working condition of supervisory circuit.
In another embodiment, as shown in figure 9, signal processing apparatus 300 includes voltage comparator 340, counter 350
With pre-warning signal generation circuit 360, the connection difference of voltage comparator 340 sampling hold circuit 200 and counter 350, counter
350 connection pre-warning signal generation circuits 360.
Voltage comparator 340 can be one or more, and the discrete signal of supply voltage is input into several voltage ratios
Compared with device 340, and the result of voltage comparator 340 is counted using counter 350, when supply voltage is within a period of time
When constantly too high or too low, pre-warning signal is produced by pre-warning signal generation circuit 360, pre-warning signal is sent to SoC
On-chip system makes system stalls, improves SoC on-chip system safeties in operation.
It is appreciated that signal processing apparatus 300 can also include analog-digital converter 310, memory 320, calculation process simultaneously
Device 330, voltage comparator 340, counter 350 and pre-warning signal generation circuit 360, utilize analog-digital converter 310, memory
320 and arithmetic processor 330 conversion storage and data analysis is carried out to discrete signal, while utilizing voltage comparator 340, counting
Device 350 and pre-warning signal generation circuit 360 carry out voltage ratio compared with timing and early warning monitoring.
Above-mentioned SoC on-chip power supplies noise monitoring system, by directly being sampled and being analyzed to power supply voltage signal, without
The delay of indirect measuring circuit reflects the change of supply voltage, and monitoring in real time and analysis SoC on-chip power supply voltages can be achieved
Size and change, monitoring accuracy are high.
Each technical characteristic of embodiment described above can be combined arbitrarily, to make description succinct, not to above-mentioned reality
Apply all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, the scope of this specification record is all considered to be.
Embodiment described above only expresses the several embodiments of the present invention, and it describes more specific and detailed, but simultaneously
Can not therefore it be construed as limiting the scope of the patent.It should be pointed out that coming for one of ordinary skill in the art
Say, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Scope.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
1. a kind of SoC on-chip power supplies noise monitoring system, it is characterised in that including dropping equipment, difference sampling hold circuit and
Signal processing apparatus, the input positive pole and input negative pole of the difference sampling hold circuit connect the dropping equipment, the difference
The output cathode and output negative pole of sampling hold circuit is divided to connect the signal processing apparatus,
The dropping equipment is used to the SoC on-chip power supply signals of access are depressured and converted, and obtains differential signal and inputs
To the difference sampling hold circuit, the difference sampling hold circuit is used to the differential signal being converted into discrete voltage letter
Number and export to the signal processing apparatus, the signal processing apparatus is used to carry out Treatment Analysis to the discrete voltage signal
Obtain supply voltage data.
2. SoC on-chip power supplies noise monitoring system according to claim 1, it is characterised in that the dropping equipment includes
Divider resistance component and first switch pipe,
The divider resistance component connects the input of the difference sampling hold circuit and the first switch pipe；Described first
The control end of switching tube connects the difference sampling hold circuit, the output head grounding of the first switch pipe.
3. SoC on-chip power supplies noise monitoring system according to claim 2, it is characterised in that the divider resistance component
Including first resistor, second resistance and 3rd resistor,
The first resistor, the second resistance and 3rd resistor series connection, the first resistor other end access power supply letter
Number, the 3rd resistor other end connects the input of the first switch pipe；The first resistor and the second resistance
Common port connects the common port company of the input positive pole of the difference sampling hold circuit, the second resistance and the 3rd resistor
Connect the input negative pole of the difference sampling hold circuit.
4. SoC on-chip power supplies noise monitoring system according to claim 1, it is characterised in that the difference sampling is kept
Circuit includes the first bootstrapped switch, the second bootstrapped switch, operational amplifier, three-phase and does not overlap clock, the first controlling switch, second
Controlling switch, the 3rd controlling switch, the 4th controlling switch, the 5th controlling switch, the 6th controlling switch, the 7th controlling switch,
One electric capacity, the second electric capacity, the 3rd electric capacity and the 4th electric capacity, the three-phase, which does not overlap clock, includes the first clock end, second clock
End and the 3rd clock end,
The input of first bootstrapped switch is as the input positive pole of the difference sampling hold circuit, and described first, which boots, opens
The output end of pass passes through the in-phase input end of operational amplifier described in first capacitance connection, the control of first bootstrapped switch
End processed connects the first clock end that the three-phase does not overlap clock；The input of second bootstrapped switch is adopted as the difference
The input negative pole of sample holding circuit, the output end of second bootstrapped switch passes through operation amplifier described in second capacitance connection
The inverting input of device, the control end of second bootstrapped switch connects the first clock end that the three-phase does not overlap clock；Institute
The output end that first controlling switch one end connects first bootstrapped switch is stated, the other end connects the defeated of second bootstrapped switch
Go out end, the control end of first controlling switch connects the 3rd clock end that the three-phase does not overlap clock；The operation amplifier
Output cathode and output negative pole of the output negative pole and output cathode of device respectively as the difference sampling hold circuit；
Second controlling switch, the 3rd controlling switch and the 4th controlling switch are sequentially connected in series rear two ends and are all connected with
One class control voltage end；The common port of second controlling switch and the 3rd controlling switch connects the operational amplifier
In-phase input end, the common port of the 3rd controlling switch and the 4th controlling switch connects the anti-phase of the operational amplifier
Input；The control end of second controlling switch, the control end of the 3rd controlling switch and the 4th controlling switch
Control end is all connected with the second clock end that the three-phase does not overlap clock；
5th controlling switch, the 6th controlling switch and the 7th controlling switch are sequentially connected in series rear two ends and are all connected with
Two class control voltage ends；The common port of 5th controlling switch and the 6th controlling switch connects the operational amplifier
Output negative pole, and pass through the in-phase input end of operational amplifier described in the 3rd capacitance connection；6th controlling switch and
The common port of 7th controlling switch connects the output cathode of the operational amplifier, and passes through the 4th capacitance connection institute
The inverting input of operational amplifier is stated, the control end of the 5th controlling switch and the control end of the 7th controlling switch are equal
Connect the first clock end that the three-phase does not overlap clock.
5. SoC on-chip power supplies noise monitoring system according to claim 4, it is characterised in that first bootstrapped switch
Opened including second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th
Guan Guan, the 9th switching tube, the tenth switching tube, the 5th electric capacity and the first phase inverter,
The control end of the second switch pipe and the control end of the 7th switching tube are all connected with the three-phase and do not overlap clock
First clock end, the input stable connection voltage source of the second switch pipe, the output end connection institute of the second switch pipe
The input of the 7th switching tube is stated, the output end of the 7th switching tube connects the input of the 9th switching tube；Described
The input of three switching tubes connects the steady voltage source, and the output end of the 3rd switching tube connects the 4th switching tube
Input, and by the input of the 8th switching tube described in the 5th capacitance connection, and the 7th switching tube and described
The common port of 9th switching tube；The input of first phase inverter connects the first clock end that the three-phase does not overlap clock,
The output end of first phase inverter connects the control end of the 6th switching tube and the control end of the 8th switching tube, described
The output head grounding of 8th switching tube；
The control end of 4th switching tube connects the common port of the second switch pipe and the 7th switching tube, the described 4th
The output end of switching tube connects the control end of the 3rd switching tube and the input of the 5th switching tube；5th switch
The output end of pipe connects the input of the 6th switching tube, and the control end of the 5th switching tube connects the burning voltage
Source, the output head grounding of the 6th switching tube；The control end of 9th switching tube and the control end of the tenth switching tube,
It is all connected with the common port of the 4th switching tube and the 5th switching tube, the output end connection of the 9th switching tube described the
The input of ten switching tubes, the common port of the 9th switching tube and the tenth switching tube is used as first bootstrapped switch
Input, the output end of the tenth switching tube as first bootstrapped switch output end.
6. SoC on-chip power supplies noise monitoring system according to claim 5, it is characterised in that the second switch pipe, institute
It is P-channel metal-oxide-semiconductor to state the 3rd switching tube and the 4th switching tube, the 5th switching tube, the 6th switching tube, described the
Seven switching tubes, the 8th switching tube, the 9th switching tube and the tenth switching tube are N-channel MOS pipe.
7. SoC on-chip power supplies noise monitoring system according to claim 4, it is characterised in that the operational amplifier bag
Include fully differential folded common source and common grid discharge circuit and switched-capacitor CMFB circuit, the fully differential folded common source and common grid amplifier
Circuit connects first bootstrapped switch, second bootstrapped switch and the signal processing apparatus, the switching capacity common mode
Feedback circuit connects the fully differential folded common source and common grid discharge circuit and the three-phase and does not overlap clock.
8. SoC on-chip power supplies noise monitoring system according to claim 4, it is characterised in that when the three-phase is not overlapped
Clock includes first with phase device, second with phase device, the second phase inverter, the 3rd phase inverter, the 4th phase inverter, the 5th phase inverter, the 6th
Phase inverter, the first NAND gate, the second NAND gate, the first delayer and the second delayer,
Described first accesses inceptive impulse signal, described first with the input of phase device and the input of second phase inverter
Output end with phase device connects the first input end of first NAND gate, and the output end of first NAND gate passes through described the
One delayer connects the input of the 3rd phase inverter, and the output end of second phase inverter connects second NAND gate
First input end, the output end of second NAND gate connects the input of the 4th phase inverter by second delayer
End, the second input of first NAND gate connects the common port of second delayer and the 4th phase inverter, described
Second input of the second NAND gate connects the common port of first delayer and the 3rd phase inverter；
The input of 5th phase inverter connects the output end of the 3rd phase inverter, and the output end of the 5th phase inverter is made
The first clock end of clock is not overlapped for the three-phase, described second with input connection first delayer of phase device and institute
State the common port of the 3rd phase inverter, described second does not overlap the second clock of clock as the three-phase with the output end of phase device
End, the input of the hex inverter connects the output end of the 4th phase inverter, and the output end of the hex inverter is made
The 3rd clock end of clock is not overlapped for the three-phase.
9. SoC on-chip power supplies noise monitoring system according to claim 1, it is characterised in that the signal processing apparatus
Including analog-digital converter, memory and arithmetic processor, the analog-digital converter connects the difference sampling hold circuit and institute
Memory is stated, the arithmetic processor connects the memory.
10. SoC on-chip power supplies noise monitoring system according to claim 1, it is characterised in that the signal processing apparatus
Including voltage comparator, counter and pre-warning signal generation circuit, the voltage comparator connects the difference sampling and keeps electricity
Road and the counter, the counter connect the pre-warning signal generation circuit.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108061850A (en) * | 2017-12-19 | 2018-05-22 | 许昌学院 | A kind of on piece signal monitoring system |
| CN108090384A (en) * | 2017-11-06 | 2018-05-29 | 大唐微电子技术有限公司 | A kind of metal line detector and chip |
| CN109302179A (en) * | 2018-09-03 | 2019-02-01 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sample logic Circuit with tolerance |
| CN117147950A (en) * | 2023-11-01 | 2023-12-01 | 广东科信电子有限公司 | Automatic detection circuit for chip power supply voltage |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514491A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Layered power source noise monitoring device of ultra large scale integrated circuit and system |
| CN1645154A (en) * | 2004-01-21 | 2005-07-27 | 发那科株式会社 | Noise detection device |
| US20070164754A1 (en) * | 2006-01-18 | 2007-07-19 | International Business Machines Corporation | On-chip high frequency power supply noise sensor |
| CN103293484A (en) * | 2013-06-06 | 2013-09-11 | 天津力神电池股份有限公司 | Method for quickly evaluating performance of lithium ion batteries by testing quantities of released heat |
| CN103608687A (en) * | 2011-06-22 | 2014-02-26 | Nxp股份有限公司 | Noise sensor |
-
2017
- 2017-05-22 CN CN201710364643.8A patent/CN106990367B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1514491A (en) * | 2002-12-31 | 2004-07-21 | �Ҵ���˾ | Layered power source noise monitoring device of ultra large scale integrated circuit and system |
| CN1645154A (en) * | 2004-01-21 | 2005-07-27 | 发那科株式会社 | Noise detection device |
| US20070164754A1 (en) * | 2006-01-18 | 2007-07-19 | International Business Machines Corporation | On-chip high frequency power supply noise sensor |
| CN103608687A (en) * | 2011-06-22 | 2014-02-26 | Nxp股份有限公司 | Noise sensor |
| CN103293484A (en) * | 2013-06-06 | 2013-09-11 | 天津力神电池股份有限公司 | Method for quickly evaluating performance of lithium ion batteries by testing quantities of released heat |
Non-Patent Citations (1)
| Title |
|---|
| 刘宇韬 等: "一种基于GRO TDC的高精度片上电源噪声监测方法", 《微电子学》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108090384A (en) * | 2017-11-06 | 2018-05-29 | 大唐微电子技术有限公司 | A kind of metal line detector and chip |
| CN108061850A (en) * | 2017-12-19 | 2018-05-22 | 许昌学院 | A kind of on piece signal monitoring system |
| CN109302179A (en) * | 2018-09-03 | 2019-02-01 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sample logic Circuit with tolerance |
| CN109302179B (en) * | 2018-09-03 | 2022-04-19 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sampling logic tolerance circuit |
| CN117147950A (en) * | 2023-11-01 | 2023-12-01 | 广东科信电子有限公司 | Automatic detection circuit for chip power supply voltage |
| CN117147950B (en) * | 2023-11-01 | 2024-01-09 | 广东科信电子有限公司 | Automatic detection circuit for chip power supply voltage |
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