CN106990367B - SoC on-chip power supply noise monitoring system - Google Patents
SoC on-chip power supply noise monitoring system Download PDFInfo
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- CN106990367B CN106990367B CN201710364643.8A CN201710364643A CN106990367B CN 106990367 B CN106990367 B CN 106990367B CN 201710364643 A CN201710364643 A CN 201710364643A CN 106990367 B CN106990367 B CN 106990367B
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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Abstract
The present invention relates to a kind of SoC on-chip power supply noise monitoring systems, including dropping equipment, difference sampling hold circuit and signal processing apparatus, the input anode of difference sampling hold circuit connects dropping equipment, the output cathode and output negative pole connection signal processing unit of difference sampling hold circuit with input cathode.Dropping equipment is depressured and is converted to the SoC on-chip power supply signal of access, it obtains differential signal and is input to difference sampling hold circuit, difference sampling hold circuit converts discrete voltage signal for differential signal and exports to signal processing apparatus, and signal processing apparatus carries out processing analysis to discrete voltage signal and obtains supply voltage data.By directly being sampled and being analyzed to power supply voltage signal, the variation of supply voltage is reflected without the delay of indirect measuring circuit, it can be achieved that real-time monitoring and the size and variation of analyzing SoC on-chip power supply voltage, monitoring accuracy are high.
Description
Technical field
The present invention relates to microelectronics technologies, more particularly to a kind of SoC on-chip power supply noise monitoring system.
Background technique
With the development of microelectric technique, integrated level, complexity and the work of integrated circuit especially system on chip (SoC)
Speed is all greatly improving, and reliability attracts wide attention.SoC will receive switching noise, electromagnetic interference, voltage when working
The influence of the various parasitics such as source variation, crosstalk, ground bounce and Substrate Coupling Noise, or when SoC work exists
When very in rugged environment, the influence such as thunder and lightning, radiation and violent temperature change will receive, these factors can make inside SoC
There is apparent variation and fluctuation in the voltage signal of certain keys, will lead to the irregular working of chip when serious, influences signal
Integrality, be more likely to will lead to SoC failure.In order to the problem more than avoiding or slowing down, need to SoC noise signal into
The accurate measurement of row, accurately could be analyzed and be predicted when chip the shape of irregular working occurs to the interference suffered by SoC
State.
SoC power supply signal is almost connected directly with all modules in circuit, the working condition of its fluctuating change to SoC
Influence be especially apparent, therefore, be monitored in the SoC course of work, while to its power supply noise, help to maintain SoC work
Make in steadily state, and prevents mains fluctuations are excessive from damaging to chip.Traditional SoC power supply noise monitoring method
It is using two circuit modules, one of circuit module is by several delay unit groups very sensitive to mains voltage variations
At another circuit module is made of several delay units very insensitive to mains voltage variations.When the same signal point
An apparent phase difference can not be generated after two circuit modules, by the size for measuring this phase, so that it may monitor
Mains voltage variations are constantly too high or too low whether there is or not certain range or supply voltage is exceeded out, i.e. track collapse.It is this
Method can only detect supply voltage whether there is or not being more than certain range, can not accurately measure the size of supply voltage, exist
Monitor the low disadvantage of accuracy.
Summary of the invention
Based on this, it is necessary in view of the above-mentioned problems, providing a kind of SoC on-chip power supply noise monitoring system that monitoring accuracy is high
System.
A kind of SoC on-chip power supply noise monitoring system, including dropping equipment, difference sampling hold circuit and signal processing device
It sets, the input anode of the difference sampling hold circuit connects the dropping equipment with input cathode, and the difference sampling is kept
The output cathode of circuit connects the signal processing apparatus with output negative pole,
The dropping equipment obtains differential signal simultaneously for the SoC on-chip power supply signal of access to be depressured and converted
It is input to the difference sampling hold circuit, the difference sampling hold circuit is used to convert discrete electrical for the differential signal
It presses signal and exports to the signal processing apparatus, the signal processing apparatus is for handling the discrete voltage signal
Analysis obtains supply voltage data.
Above-mentioned SoC on-chip power supply noise monitoring system, dropping equipment to the SoC on-chip power supply signal of access carry out decompression and
Conversion, obtain differential signal and be input to difference sampling hold circuit, difference sampling hold circuit by differential signal be converted into from
It dissipates voltage signal and exports to signal processing apparatus, signal processing apparatus carries out processing analysis to discrete voltage signal and obtains power supply
Voltage data.By directly being sampled and being analyzed to power supply voltage signal, reflect electricity without the delay of indirect measuring circuit
The variation of source voltage is, it can be achieved that real-time monitoring and the size and variation of analyzing SoC on-chip power supply voltage, monitoring accuracy are high.
Detailed description of the invention
Fig. 1 is the structure chart of SoC on-chip power supply noise monitoring system in an embodiment；
Fig. 2 is the schematic diagram of dropping equipment in an embodiment；
Fig. 3 is the schematic diagram of difference sampling hold circuit in an embodiment；
Fig. 4 is the schematic diagram of the first bootstrapped switch in an embodiment；
Fig. 5 is the schematic diagram of operational amplifier in an embodiment；
Fig. 6 is the schematic diagram of the not overlapping clock of three-phase in an embodiment；
Fig. 7 is the clock pulses figure of the not overlapping clock of three-phase in an embodiment；
Fig. 8 is the structure chart of signal processing apparatus in an embodiment；
Fig. 9 is the structure chart of signal processing apparatus in another embodiment.
Specific embodiment
In one embodiment, a kind of SoC on-chip power supply noise monitoring system, as shown in Figure 1, include dropping equipment 100,
Difference sampling hold circuit 200 and signal processing apparatus 300, the input anode Vin+ of difference sampling hold circuit 200 and input
Cathode Vin- connection dropping equipment 110, the output cathode Vout+ of difference sampling hold circuit 200 is connected with output negative pole Vout-
Signal processing apparatus 300.Dropping equipment 100 obtains difference for the SoC on-chip power supply signal of access to be depressured and converted
Signal is simultaneously input to difference sampling hold circuit 200, and difference sampling hold circuit 200 is used to convert discrete electrical for differential signal
It presses signal and exports to signal processing apparatus 300, signal processing apparatus 300 is used to carry out discrete voltage signal processing to analyze
To supply voltage data.
Power supply signal Vin_noise for the circuit variation to be monitored power supply signal.It is defeated due to subsequent conditioning circuit module
Range is limited by circuit structure and power supply voltage swing out, can not handle the excessive signal of voltage magnitude, therefore electricity
Source signal Vin_noise, which will first pass through dropping equipment 100, to be reduced voltage magnitude and is converted into differential signal and is input to difference to adopt
Sample holding circuit 200.In addition, difference sampling hold circuit 200 can also stable connection voltage source VDD_quiet, using stablize electricity
Potential source VDD_quiet power supply.Difference sampling hold circuit 200 converts the power supply signal of consecutive variations to discrete voltage signal
It exports, then discrete signal is handled and analyzed by subsequent signal processing apparatus 300 situation of change of power supply signal.
Signal processing apparatus 300 can be stored in memory after processing obtains supply voltage data, be also possible to according to supply voltage number
According to early warning analysis is carried out, SoC system stalls are controlled when supply voltage occurs abnormal.
The specific structure of dropping equipment 100 and decompression mode be not unique, in one embodiment, as shown in Fig. 2, decompression
Device 100 includes divider resistance component 120 and first switch tube NM104.Divider resistance component 120 connects difference sampling and keeps electricity
The input terminal on road 200 and first switch tube NM104；The control terminal of first switch tube NM104 connects difference sampling hold circuit
The output end of 200, first switch tube NM104 are grounded.
First switch tube NM104 can be metal-oxide-semiconductor or triode etc., and in the present embodiment, first switch tube NM104 is N ditch
Road metal-oxide-semiconductor.The specific structure of divider resistance component 120 is not also unique, in one embodiment, with continued reference to Fig. 2, divider resistance
Component 120 includes first resistor R101, second resistance R102 and 3rd resistor R103.First resistor R101, second resistance R102
It connects with 3rd resistor R103, the first resistor R101 other end accesses power supply signal Vin_noise, the 3rd resistor R103 other end
Connect the input terminal of first switch tube NM104；First resistor R101 connects difference sampling with the common end of second resistance R102 and protects
Input the anode Vin+, second resistance R102 for holding circuit 200 connect difference sampling with the common end of 3rd resistor R103 and keep electricity
The input cathode Vin- on road 200.
Dropping equipment 100 is divided using three concatenated resistance R101, R102 and R103, and in view of junior
Input/output bound protects dropping equipment 100 using the both end voltage of interlaminated resistance R102 as the differential input voltage of next stage
The linearisation of height is held in order to avoid introducing non-linear distortion in pressure reduction.The magnitude of resistance R101, R102 and R103 resistance value can
It is reasonably selected according to actual needs, resistance value is too small to bring unnecessary quiescent dissipation, and reduces the negative of voltage source
It carries, observation circuit is made inherently to have a great impact to voltage signal variation.Second resistance R102 both end voltage is specifically and junior
The sampling capacitance of difference sampling hold circuit 200 is connected directly, equivalent electric by resistance R101, R102, R103 and sampling at one
The circuit RC for holding composition, if resistance is larger, will affect sampling process in the case where the capacitance amount of exhausting of sampling capacitance is small
The stabilization time of middle input signal and biggish dynamic error is caused, limits the operating rate and precision of integrated circuit.It is being depressured
Make the switch controlled in one NMOS tube of series connection in device 100, control dropping equipment 100 is connected in sampling process, kept
Cheng Dangzhong is disconnected, and reduces unnecessary power consumption.The breadth length ratio of NMOS tube will the amount of exhausting it is big, keep the equivalent resistance of NMOS tube far small
It in the value of resistance, can be ignored it to circuit bring linearity error.
The specific structure of difference sampling hold circuit 200 and sample mode are also not uniquely, in one embodiment, such as
Shown in Fig. 3, difference sampling hold circuit 200 includes that the bootstrapping of the first bootstrapped switch (Boostrapped Switch) 220, second is opened
It closes 240, operational amplifier 260, three-phase and does not overlap clock 280, the first control switch S201, the second control switch S202, third
Control switch S203, the 4th control switch S204, the 5th control switch S205, the 6th control switch S206, the 7th control switch
S207, first capacitor C207, the second capacitor C208, third capacitor C209 and the 4th capacitor C210, the not overlapping clock 280 of three-phase wrap
Include the first clock end, second clock end and third clock end.Specifically, the not overlapping clock 280 of three-phase accesses inceptive impulse signal
CLKin, and clock signal clk 1, CLK2 and CLK3 are exported by the first clock end, second clock end and third clock end respectively.
Accordingly, the control terminal of first switch tube NM104 connects the first clock end that three-phase does not overlap clock 280 in dropping equipment 100.
Input anode Vin+ of the input terminal Vin of first bootstrapped switch 220 as difference sampling hold circuit 200, specifically
Connect the common end of first resistor R101 and second resistance R102 in dropping equipment 100, the output end of the first bootstrapped switch 220
Vout passes through the non-inverting input terminal of first capacitor C207 connection operational amplifier 260, the control terminal connection of the first bootstrapped switch 220
First clock end of the not overlapping clock 280 of three-phase；The input terminal Vin of second bootstrapped switch 240 is as difference sampling hold circuit
200 input cathode Vin-, the specific common end for connecting second resistance R102 and 3rd resistor R103 in dropping equipment 100, the
The output end vo ut of two bootstrapped switches 240 passes through the inverting input terminal of the second capacitor C208 connection operational amplifier 260, and second certainly
Lift the first clock end of the not overlapping clock 280 of control terminal connection three-phase of switch 240；First one end control switch S201 connection the
The output end vo ut of one bootstrapped switch 220, the other end connect the output end vo ut of the second bootstrapped switch 240, the first control switch
The third clock end of the not overlapping clock 280 of control terminal connection three-phase of S201；The output negative pole of operational amplifier 260 and output are just
Output cathode Vout+ and output negative pole Vout- of the pole respectively as difference sampling hold circuit 200, connection signal processing unit
300。
Second control switch S202, third control switch S203 and the 4th control switch S204 are sequentially connected in series rear both ends and connect
Meet first kind control voltage end Vin_bias；Second control switch S202 connects operation with the common end of third control switch S203
The common end of the non-inverting input terminal of amplifier 260, third control switch S203 and the 4th control switch S204 connect operation amplifier
The inverting input terminal of device；The control terminal of second control switch S202, the control terminal of third control switch S203 and the 4th control are opened
The control terminal for closing S204 is all connected with the second clock end of the not overlapping clock 280 of three-phase.
5th control switch S205, the 6th control switch S206 and the 7th control switch S207 are sequentially connected in series rear both ends and connect
Meet the second class control voltage end Vout_bias；The common end of 5th control switch S205 and the 6th control switch S206 connects fortune
The output negative pole of amplifier is calculated, and passes through the non-inverting input terminal of third capacitor C209 connection operational amplifier；6th control switch
The common end of S206 and the 7th control switch S207 connect the output cathode of operational amplifier, and pass through the 4th capacitor C210 connection
The inverting input terminal of operational amplifier, the control terminal of the 5th control switch S205 and the control terminal of the 7th control switch S207 connect
Connect the first clock end of the not overlapping clock 280 of three-phase.
Sampling hold circuit can all be influenced by clock feedthrough and channel charge injection, in high speed applications, due to wanting
Using the biggish pipe of breadth length ratio, the phenomenon that clock feedthrough and channel charge can be made to inject, is become apparent.In the present embodiment, difference
The principle that sampling hold circuit 200 is sampled by using switching capacity bottom plate will inject institute by clock feedthrough and channel charge
The error of generation is converted into fixed imbalance, and is eliminated by differential configuration.It is sampled using difference and switching capacity bottom plate
Structure effectively eliminates error, reaches higher precision.It is changed greatly simultaneously as power supply signal collected is one
Signal, therefore difference sampling hold circuit 200 inhibits operational amplifier using the switching capacity sample circuit of charge redistribution type
The offset of 260 common mode inputs keeps amplifier work in amplification region.The not overlapping clock 280 of three-phase generates three clock signals
CLK1, CLK2 and CLK3, wherein the rising edge of a pulse of clock signal clk 2 earlier than clock signal clk 1 rising edge of a pulse, and
The pulse falling edge of clock signal clk 2 is later than the pulse falling edge of clock signal clk 1；Clock signal clk 3 is in clock signal
CLK1 and clock signal clk 2 are in low level state when being high level.First bootstrapped switch 220, the second bootstrapped switch 240,
Five control switch S205 and the 7th control switch S207 subject clock signal CLK1 control, the second control switch S202, third control
Switch S203 and the 4th control switch S204 subject clock signal CLK2 control, the first control switch S201 subject clock signal CLK3 control
System.Controlling corresponding switch on and off by three tunnel clock signals makes difference to adjust the state of difference sampling hold circuit 200
Sampling hold circuit 200 periodically converts the power supply voltage signal of variation to discrete voltage signal.
The main function of first bootstrapped switch 220 and the second bootstrapped switch 240 is that reduction difference sampling hold circuit 200 is defeated
Enter the conducting resistance in loop, and conducting resistance resistance value is made with the variation of input voltage and variation, not improve the work of integrated circuit
Make speed and precision.First bootstrapped switch 220 is similar with the structure of the second bootstrapped switch 240, is with the first bootstrapped switch 220
Example, in one embodiment, as shown in figure 4, the first bootstrapped switch 220 includes second switch PM201a, third switching tube
PM202a, the 4th switching tube PM203a, the 5th switching tube NM204a, the 6th switching tube NM205a, the 7th switching tube NM206a,
Eight switching tube NM207a, the 9th switching tube NM208a, the tenth switching tube NM209a, the 5th capacitor C210a and the first phase inverter F0.
The control terminal of second switch PM201a and the control terminal of the 7th switching tube NM206a be all connected with three-phase it is not overlapping when
First clock end of clock 280, the input terminal stable connection voltage source VDD_quiet of second switch PM201a, second switch
The output end of PM201a connects the input terminal of the 7th switching tube NM206a, and the output end connection the 9th of the 7th switching tube NM206a is opened
Close the input terminal of pipe NM208a；The input terminal stable connection voltage source VDD_quiet of third switching tube PM202a, third switching tube
The output end of PM202a connects the input terminal of the 4th switching tube PM203a, and passes through the 8th switching tube of the 5th capacitor C210a connection
The common end of the input terminal of NM207a and the 7th switching tube NM206a and the 9th switching tube NM208a；First phase inverter F0's
Input terminal connects the first clock end of the not overlapping clock 280 of three-phase, and the output end of the first phase inverter F0 connects the 6th switching tube
The control terminal of the control terminal of NM205a and the 8th switching tube NM207a, the output end ground connection of the 8th switching tube NM207a.
The control terminal connection second switch PM201a's and the 7th switching tube NM206a of 4th switching tube PM203a is public
End, the 4th switching tube PM203a output end connection third switching tube PM202a control terminal and the 5th switching tube NM204a it is defeated
Enter end；The output end of 5th switching tube NM204a connects the input terminal of the 6th switching tube NM205a, the 5th switching tube NM204a's
The output end of control terminal stable connection voltage source VDD_quiet, the 6th switching tube NM205a are grounded；9th switching tube NM208a's
The control terminal of control terminal and the tenth switching tube NM209a is all connected with the public affairs of the 4th switching tube PM203a and the 5th switching tube NM204a
End altogether, the output end of the 9th switching tube NM208a connect the input terminal of the tenth switching tube NM209a, the 9th switching tube NM208a and
Input terminal Vin of the common end of tenth switching tube NM209a as the first bootstrapped switch 220, the output of the tenth switching tube NM209a
Hold the output end vo ut as the first bootstrapped switch 220.
Each switching tube specifically can be metal-oxide-semiconductor or triode etc., and in the present embodiment, second switch PM201a, third are opened
Pass pipe PM202a and the 4th switching tube PM203a is P-channel metal-oxide-semiconductor, the 5th switching tube NM204a, the 6th switching tube NM205a, the
Seven switching tube NM206a, the 8th switching tube NM207a, the 9th switching tube NM208a and the tenth switching tube NM209a are N-channel MOS
Pipe.
Specifically, when clock signal CLK1 is low level, the 8th switching tube NM207a and third switching tube PM202a are led
Logical, the 5th capacitor C210a both end voltage is charged to voltage VDD by power supply, and the 4th switching tube PM203a and the 9th is opened at this time
It closes pipe NM208a to disconnect, the 5th switching tube NM204a and the 6th switching tube NM205a conducting, the tenth switching tube NM209a gate voltage
For 0V, it is equivalent to open circuit；When clock signal CLK2 is high level, the 8th switching tube NM207a and third switching tube PM202a are disconnected
It opens, the 4th switch PM203a and the 9th switching tube NM208a conducting, the 5th switching tube NM204a and the 6th switching tube NM205a are disconnected
It opens, the 5th capacitor C210a is connected in parallel on the tenth switching tube NM209a grid end and input terminal Vin, by the grid of the tenth switching tube NM209a
Source voltage is raised to VDD, reduces its conducting resistance, and do not change with the variation of input voltage.
In one embodiment, operational amplifier 260 uses the fully differential folded common source and common grid inputted with N-channel MOS pipe
Operational amplifier can improve the output resistance of operational amplifier 200b using cascode structure, improve gain, reduce difference
The gain error of sampling hold circuit 200 improves system accuracy, and the structure of folding cascade operational amplifier is defeated
It is larger to enter range, frequency characteristic is good, can reach higher operating rate.Specifically, as shown in figure 5, operational amplifier 260 includes
Fully differential folded common source and common grid operational amplifier circuit 262 and switched-capacitor CMFB circuit 264, fully differential folded common source and common grid amplifier
Circuit 262 connects the first bootstrapped switch 220, the second bootstrapped switch 240 and signal processing apparatus 300, switched-capacitor CMFB
Circuit 264 connects fully differential folded common source and common grid operational amplifier circuit 262 and three-phase and does not overlap clock 280.Switched-capacitor CMFB
Circuit 264 is used to stablize the output common mode voltage of operational amplifier 260.
In the present embodiment, fully differential folded common source and common grid operational amplifier circuit 262 includes NMOS tube NM201b, NMOS tube
NM202b, NMOS tube NM203b, PMOS tube PM204b, PMOS tube PM205b, PMOS tube PM206b, PMOS tube PM207b, NMOS
Pipe NM208b, NMOS tube NM209b, NMOS tube NM210b, NMOS tube NM211b, capacitor CL1 and capacitor CL2.
The grid of non-inverting input terminal of the grid of NMOS tube NM201b as operational amplifier 260, NMOS tube NM203b is made
For the inverting input terminal of operational amplifier 260, grid access control the voltage Vbias1, NMOS tube NM202b of NMOS tube NM202b
Source electrode ground connection, NMOS tube NM202b drain electrode connection NMOS tube NM201b source electrode and NMOS tube NM203b source electrode.PMOS
The grid of the grid connection PMOS tube PM205b of pipe PM204b, the source electrode of PMOS tube PM204b and the source electrode of PMOS tube PM205b are equal
The source electrode of the drain electrode connection PMOS tube PM206b of stable connection voltage source VDD_quiet, PMOS tube PM204b, PMOS tube PM205b
Drain electrode connection PMOS tube PM207b source electrode, PMOS tube PM206b grid connection PMOS tube PM207b grid, PMOS tube
The drain electrode of the drain electrode connection NMOS tube NM208b of PM206b, the drain electrode of the drain electrode connection NMOS tube NM209b of PMOS tube PM207b,
The grid of the grid connection NMOS tube NM209b of NMOS tube NM208b, the source electrode connection NMOS tube NM210b's of NMOS tube NM208b
Drain electrode, the drain electrode of the source electrode connection NMOS tube NM211b of NMOS tube NM209b, the grid of NMOS tube NM210b connect NMOS tube
The grid of NM211b, the source electrode of NMOS tube NM210b and the source grounding of NMOS tube NM211b.PMOS tube PM204b and PMOS
The common end connection switch capacitor common mode feedback circuit 264 of pipe PM205b, PMOS tube PM204b and PMOS tube PM206b's is public
The drain electrode of end connection NMOS tube NM201b, PMOS tube PM205b connect NMOS tube NM203b's with the common end of PMOS tube PM207b
Drain electrode.Output negative pole of the common end of PMOS tube PM206b and NMOS tube NM208b as difference sampling hold circuit 200
Vout-, and be grounded by capacitor CL1, the common end of PMOS tube PM207b and NMOS tube NM209b are sampled as difference keeps electricity
The output cathode Vout+ on road 200, and be grounded by capacitor CL2.
Further, switched-capacitor CMFB circuit 264 includes capacitor C212b, capacitor C213b, capacitor C214b, electricity
Hold C215b, switch S216b, switch S217b, switch S218b, switch S219b, switch S220b and switch S221b.It is concatenated to open
Close S216b and switch S219b, concatenated switch S217b and switch S220b and concatenated switch S218b and switch S221b simultaneously
The common end of connection, switch S216b and switch S219b pass through the common end of capacitor C214b connection switch S217b and switch S220b,
The common end of switch S217b and switch S220b passes through the common end of capacitor C215b connection switch S218b and switch S221b；It opens
The output cathode Vout+ of the other end connection difference sampling hold circuit 200 of S216b is closed, and passes through capacitor C212b connection switch
The other end of S217b, the other end of switch S219b connect the second class and control voltage end Vout_bias；The switch S217b other end
The common end of PMOS tube PM204b and PMOS tube PM205b are connected, and passes through the other end of capacitor C213b connection switch S218b；
The other end connection third class of switch S220b controls voltage end Vdmfb_bias；The switch S218b other end connects difference sampling and protects
The output negative pole Vout+ of circuit 200 is held, the other end of switch S221b connects the second class and controls voltage end Vout_bias.Switch
S216b, switch S217b and the control terminal of switch S218b connect the third clock end of the not overlapping clock 280 of three-phase, switch
S219b, switch S220b and the control terminal of switch S221b connect the first clock end of the not overlapping clock 280 of three-phase.
The main function of the non-overlapping clock 280 of three-phase is to generate the non-overlapping clock of two phase place, and three-phase does not overlap clock
280 specific structure is not unique, in one embodiment, as shown in fig. 6, the not overlapping clock 280 of three-phase includes first same
Phase device T1, second are the same as phase device T2, the second phase inverter F1, third phase inverter F2, the 4th phase inverter F3, the 5th phase inverter F4, the 6th
Phase inverter F5, the first NAND gate NAND1, the second NAND gate NAND2, the first delayer DELAY1 and the second delayer DELAY2.
First accesses inceptive impulse signal CLKin with the input terminal of phase device T1 and the input terminal of the second phase inverter F1, the
The output end of phase device T1 connects the first input end of the first NAND gate NAND1 together, and the output end of the first NAND gate NAND1 passes through
The output end of the input terminal of first delayer DELAY1 connection third phase inverter F2, the second phase inverter F1 connects the second NAND gate
The output end of the first input end of NAND2, the second NAND gate NAND2 passes through the 4th phase inverter F3 of the second delayer DELAY2 connection
Input terminal, the first NAND gate NAND1 the second input terminal connection the second delayer DELAY2 and the 4th phase inverter F3 it is public
End, the common end of the connection of the second input terminal the first delayer DELAY1 and third phase inverter F2 of the second NAND gate NAND1.
The output end of the input terminal connection third phase inverter F2 of 5th phase inverter F4, the output end conduct of the 5th phase inverter F4
First clock end of the not overlapping clock 280 of three-phase, for exporting clock signal clk 1；Second with phase device T2 input terminal connection the
The common end of one delayer DELAY1 and third phase inverter F2, second with phase device T2 output end as three-phase not overlap clock
280 second clock end, for exporting clock signal clk 2；The input terminal of hex inverter F5 connects the defeated of the 4th phase inverter F3
Outlet, third clock end of the output end of hex inverter F5 as the not overlapping clock 280 of three-phase, for exporting clock signal
CLK3.The non-overlapping clock 280 of three-phase accesses inceptive impulse signal CLKin, by inside with phase device, phase inverter, NAND gate and
The effect of delayer exports three tunnel clock signals.Such as the timing that Fig. 7 is clock signal clk 1, CLK2 and CLK3 in the present embodiment
Figure.It is appreciated that the form for the three tunnel clock signals that the non-overlapping clock 280 of three-phase exports is also not uniquely, only need to meet
Differential signal is converted discrete voltage signal by controllable difference sampling hold circuit 200.
The specific structure of signal processing apparatus 300 and signal processing are also not uniquely, in one embodiment, such as
Shown in Fig. 8, signal processing apparatus 300 includes analog-digital converter 310, memory 320 and arithmetic processor 330, analog-digital converter
310 connection difference sampling hold circuits 200 and memory 320, arithmetic processor 330 connect memory 320.
When SoC on-chip power supply noise monitoring system is applied in fairly large system on chip, analog-digital converter 310 will be electric
The discrete signal of source voltage is converted into digital signal and is stored in memory 320, then is carried out by arithmetic processor 330 to data
Analysis and processing reach the variation under analysis supply voltage is disturbed, predict and monitor the effect of the working condition of circuit.
In another embodiment, as shown in figure 9, signal processing apparatus 300 includes voltage comparator 340, counter 350
With pre-warning signal generation circuit 360, voltage comparator 340 connects difference sampling hold circuit 200 and counter 350, counter
350 connection pre-warning signal generation circuits 360.
Voltage comparator 340 can be one or more, and the discrete signal of supply voltage is input to several voltage ratios
Compared in device 340, and counted using result of the counter 350 to voltage comparator 340, when supply voltage whithin a period of time
When constantly excessively high or too low, pre-warning signal is generated by pre-warning signal generation circuit 360, pre-warning signal is sent to SoC
System on chip makes system stalls, improves SoC system on chip safety in operation.
It is appreciated that signal processing apparatus 300 can also include analog-digital converter 310, memory 320, calculation process simultaneously
Device 330, voltage comparator 340, counter 350 and pre-warning signal generation circuit 360, utilize analog-digital converter 310, memory
320 and arithmetic processor 330 to discrete signal carry out conversion storage and data analyze, while using voltage comparator 340, count
Device 350 and pre-warning signal generation circuit 360 carry out voltage and compare timing and early warning monitoring.
Above-mentioned SoC on-chip power supply noise monitoring system, by directly being sampled and being analyzed to power supply voltage signal, without
The variation of indirect measuring circuit being delayed to reflect supply voltage is, it can be achieved that real-time monitoring and analysis SoC on-chip power supply voltage
Size and variation, monitoring accuracy are high.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (9)
1. a kind of SoC on-chip power supply noise monitoring system, which is characterized in that including dropping equipment, difference sampling hold circuit and
The input anode of signal processing apparatus, the difference sampling hold circuit connects the dropping equipment, the difference with input cathode
The output cathode of sampling hold circuit is divided to connect the signal processing apparatus with output negative pole,
The dropping equipment obtains differential signal and inputs for the SoC on-chip power supply signal of access to be depressured and converted
To the difference sampling hold circuit, the difference sampling hold circuit is used to convert the differential signal in discrete voltage letter
Number and export to the signal processing apparatus, the signal processing apparatus is for carrying out processing analysis to the discrete voltage signal
Obtain supply voltage data；
The signal processing apparatus includes analog-digital converter, memory and arithmetic processor, described in the analog-digital converter connection
Difference sampling hold circuit and the memory, the arithmetic processor connect the memory.
2. SoC on-chip power supply noise monitoring system according to claim 1, which is characterized in that the dropping equipment includes
Divider resistance component and first switch tube,
The divider resistance component connects the input terminal of the difference sampling hold circuit and the first switch tube；Described first
The control terminal of switching tube connects the difference sampling hold circuit, the output end ground connection of the first switch tube.
3. SoC on-chip power supply noise monitoring system according to claim 2, which is characterized in that the divider resistance component
Including first resistor, second resistance and 3rd resistor,
The first resistor, the second resistance and 3rd resistor series connection, the first resistor other end access power supply letter
Number, the 3rd resistor other end connects the input terminal of the first switch tube；The first resistor and the second resistance
Common end connects the input anode of the difference sampling hold circuit, the common end company of the second resistance and the 3rd resistor
Connect the input cathode of the difference sampling hold circuit.
4. SoC on-chip power supply noise monitoring system according to claim 1, which is characterized in that the difference sampling is kept
Circuit includes that the first bootstrapped switch, the second bootstrapped switch, operational amplifier, three-phase do not overlap clock, the first control switch, second
Control switch, third control switch, the 4th control switch, the 5th control switch, the 6th control switch, the 7th control switch,
One capacitor, the second capacitor, third capacitor and the 4th capacitor, the not overlapping clock of the three-phase includes the first clock end, second clock
End and third clock end,
Input anode of the input terminal of first bootstrapped switch as the difference sampling hold circuit, first bootstrapping are opened
The output end of pass connects the non-inverting input terminal of the operational amplifier, the control of first bootstrapped switch by the first capacitor
End processed connects the first clock end of the not overlapping clock of the three-phase；The input terminal of second bootstrapped switch is adopted as the difference
The output end of the input cathode of sample holding circuit, second bootstrapped switch passes through operation amplifier described in second capacitance connection
The inverting input terminal of device, the control terminal of second bootstrapped switch connect the first clock end of the not overlapping clock of the three-phase；Institute
The output end that first control switch one end connects first bootstrapped switch is stated, the other end connects the defeated of second bootstrapped switch
Outlet, the control terminal of first control switch connect the third clock end of the not overlapping clock of the three-phase；The operation amplifier
Output cathode and output negative pole of the output negative pole and output cathode of device respectively as the difference sampling hold circuit；
Second control switch, the third control switch and the 4th control switch are sequentially connected in series rear both ends and are all connected with
One kind control voltage end；Second control switch connects the operational amplifier with the common end of the third control switch
Non-inverting input terminal, the third control switch connect the reverse phase of the operational amplifier with the common end of the 4th control switch
Input terminal；The control terminal of second control switch, the control terminal of the third control switch and the 4th control switch
Control terminal is all connected with the second clock end of the not overlapping clock of the three-phase；
5th control switch, the 6th control switch and the 7th control switch are sequentially connected in series rear both ends and are all connected with
Two classes control voltage end；5th control switch connects the operational amplifier with the common end of the 6th control switch
Output negative pole, and pass through the non-inverting input terminal of operational amplifier described in the third capacitance connection；6th control switch and
The common end of 7th control switch connects the output cathode of the operational amplifier, and passes through the 4th capacitance connection institute
The inverting input terminal of operational amplifier is stated, the control terminal of the 5th control switch and the control terminal of the 7th control switch are equal
Connect the first clock end of the not overlapping clock of the three-phase.
5. SoC on-chip power supply noise monitoring system according to claim 4, which is characterized in that first bootstrapped switch
It is opened including second switch, third switching tube, the 4th switching tube, the 5th switching tube, the 6th switching tube, the 7th switching tube, the 8th
Guan Guan, the 9th switching tube, the tenth switching tube, the 5th capacitor and the first phase inverter,
The control terminal of the second switch and the control terminal of the 7th switching tube are all connected with the not overlapping clock of the three-phase
The output end of first clock end, the input terminal stable connection voltage source of the second switch, the second switch connects institute
The input terminal of the 7th switching tube is stated, the output end of the 7th switching tube connects the input terminal of the 9th switching tube；Described
The input terminal of three switching tubes connects the steady voltage source, and the output end of the third switching tube connects the 4th switching tube
Input terminal, and pass through the input terminal of the 8th switching tube described in the 5th capacitance connection and the 7th switching tube and described
The common end of 9th switching tube；The input terminal of first phase inverter connects the first clock end of the not overlapping clock of the three-phase,
The output end of first phase inverter connects the control terminal of the 6th switching tube and the control terminal of the 8th switching tube, described
The output end of 8th switching tube is grounded；
The control terminal of 4th switching tube connects the common end of the second switch and the 7th switching tube, and the described 4th
The output end of switching tube connects the control terminal of the third switching tube and the input terminal of the 5th switching tube；5th switch
The output end of pipe connects the input terminal of the 6th switching tube, and the control terminal of the 5th switching tube connects the burning voltage
Source, the output end ground connection of the 6th switching tube；The control terminal of 9th switching tube and the control terminal of the tenth switching tube,
It is all connected with the common end of the 4th switching tube and the 5th switching tube, the output end connection of the 9th switching tube described the
The common end of the input terminal of ten switching tubes, the 9th switching tube and the tenth switching tube is as first bootstrapped switch
Input terminal, output end of the output end of the tenth switching tube as first bootstrapped switch.
6. SoC on-chip power supply noise monitoring system according to claim 5, which is characterized in that the second switch, institute
Stating third switching tube and the 4th switching tube is P-channel metal-oxide-semiconductor, the 5th switching tube, the 6th switching tube, described the
Seven switching tubes, the 8th switching tube, the 9th switching tube and the tenth switching tube are N-channel MOS pipe.
7. SoC on-chip power supply noise monitoring system according to claim 4, which is characterized in that the operational amplifier packet
Include fully differential folded common source and common grid operational amplifier circuit and switched-capacitor CMFB circuit, the fully differential folded common source and common grid amplifier
First bootstrapped switch described in circuit connection, second bootstrapped switch and the signal processing apparatus, the switching capacity common mode
Feed circuit connects the fully differential folded common source and common grid operational amplifier circuit and the three-phase and does not overlap clock.
8. SoC on-chip power supply noise monitoring system according to claim 4, which is characterized in that when the three-phase is not overlapping
Clock include first with phase device, second with phase device, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, the 6th
Phase inverter, the first NAND gate, the second NAND gate, the first delayer and the second delayer,
Described first accesses inceptive impulse signal with the input terminal of phase device and the input terminal of second phase inverter, and described first
Connect the first input end of first NAND gate with the output end of phase device, the output end of first NAND gate passes through described the
One delayer connects the input terminal of the third phase inverter, and the output end of second phase inverter connects second NAND gate
First input end, the output end of second NAND gate connect the input of the 4th phase inverter by second delayer
End, the second input terminal of first NAND gate connects the common end of second delayer and the 4th phase inverter, described
Second input terminal of the second NAND gate connects the common end of first delayer and the third phase inverter；
The input terminal of 5th phase inverter connects the output end of the third phase inverter, and the output end of the 5th phase inverter is made
For the first clock end of the not overlapping clock of the three-phase, described second the same as input terminal connection first delayer of phase device and institute
State the common end of third phase inverter, described second with phase device second clock of the output end as the not overlapping clock of the three-phase
End, the input terminal of the hex inverter connect the output end of the 4th phase inverter, and the output end of the hex inverter is made
For the third clock end of the not overlapping clock of the three-phase.
9. SoC on-chip power supply noise monitoring system according to claim 1, which is characterized in that the signal processing apparatus
It further include voltage comparator, counter and pre-warning signal generation circuit, the voltage comparator connects the difference sampling and keeps
Circuit and the counter, the counter connect the pre-warning signal generation circuit.
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| CN108090384B (en) * | 2017-11-06 | 2021-08-03 | 大唐微电子技术有限公司 | Metal wire detection device and chip |
| CN108061850A (en) * | 2017-12-19 | 2018-05-22 | 许昌学院 | A kind of on piece signal monitoring system |
| CN109302179B (en) * | 2018-09-03 | 2022-04-19 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sampling logic tolerance circuit |
| CN117147950B (en) * | 2023-11-01 | 2024-01-09 | 广东科信电子有限公司 | Automatic detection circuit for chip power supply voltage |
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