CN202906877U - Adc sampling circuit - Google Patents

Abstract

The utility model discloses an ADC sampling circuit, comprising an outer input end, a sampling circuit and an auxiliary circuit connected with the outer input end, a clock circuit and an outer output end connected with the sampling circuit, and a clock feed through circuit connected with the auxiliary circuit. The clock feed through circuit is also connected with the clock circuit and the outer output end separately. The ADC sampling circuit of the utility model enables the effect of a clock feed through effect on signal sampling and the harmonic distortion factor of the ADC sampling circuit to be reduced, and the linearity of a sampling field effect transistor, the sampling speed and the sampling precision of the ADC sampling circuit to be improved.

Description

The ADC sample circuit

Technical field

The utility model relates to the sample circuit field, relates more specifically to a kind of ADC sample circuit.

Background technology

At ADC(Analog-to-Digital Converter, A-D converter) in the circuit, for precision and the speed that guarantees ADC, the input sample end need to adopt the Bootstrap structure with the linearity that guarantees the input sample switch simultaneously to enlarge the signal input range.But when adopting the sample circuit of Bootstrap structure, the error that clock feedthrough is introduced is relevant with input signal, has introduced thus nonlinearity erron, and the amplifier of employing fully differential structure can not be eliminated the impact of clock feedthrough.

Wherein, please refer to Fig. 1, existing ADC sample circuit comprises clock circuit, sample circuit and capacitor C 0; Clock circuit produces clock pulse and exports sample circuit to by its output K0, with the sampling operation by clock pulse control sample circuit.Sample circuit comprises Bootstrap unit and field effect transistor M1, two inputs of Bootstrap unit are connected with output K0 and the external input terminals of clock circuit respectively, external input terminals input signal VIN is to an input of Bootstrap unit, thereby when K0 is output as high level, output V0 and the electrical potential difference between the input signal VIN of Bootstrap unit are constant voltage VC, be V0=VIN+VC, to improve the output voltage of V0; And when K0 is low level, V0=0, namely exporting V0 is low level, also namely by the output voltage V 0 of clock circuit control inputs signal VIN behind the Bootstrap unit.The output of Bootstrap unit is connected with the grid of field effect transistor M1, and the source electrode of field effect transistor M1 is connected with external input terminals, and when V0 was high level, field effect transistor M1 sampled to the input signal VIN of external input terminals, and by its drain electrode output VOUT.One end of capacitor C 0 is connected with the drain electrode of field effect transistor M1, other end ground connection, the voltage of the signal that obtains so that field effect transistor M1 is sampled keeps, also namely when the output K0 output low level of clock circuit and when making VO be low level, field effect transistor M1 has sampled the signal that obtains can be not influenced, and kept by capacitor C O.

In said process, the forward of setting outside input is input as VIN1, oppositely is input as VIN2.When the output for forward input VIN1 and K0 was converted to low level by high level, the V0 voltage of this moment dropped to 0 by high level VIN+VC, so that field effect transistor M1 has introduced clock feedthrough, its impact on sampled signal voltage is

$\mathrm{\Δ}{V}_{\mathrm{OUTP}}=-\frac{C_{P\_\mathrm{GD}\_M1}}{C_{P\_\mathrm{GD}\_M1}+C_0}(\mathrm{VIN}1+\mathrm{VC})---\left(1\right)$

C in the formula _{P_GD_M1}Parasitic capacitance when inputting for forward between field effect transistor M1 grid leak.

When circuit adopted the fully differential structure, oppositely the structure inputted of input and forward was identical, when then oppositely inputting VIN2, on the impact of sampled signal voltage was

$\mathrm{\Δ}{V}_{\mathrm{OUTN}}=-\frac{C_{N\_\mathrm{GD}\_M1}}{C_{N\_\mathrm{GD}\_M1}+C_0}(\mathrm{VIN}2+\mathrm{VC})---\left(2\right)$

Change low level into by high level, C owing to time pulse in the formula _{N_GD_M1}During for reverse input, the parasitic capacitance between field effect transistor M1 grid leak is because forward input structure of sample circuit when oppositely inputting is identical, so C _{N_GD_M1}=C _{P_GD_M1}=C _{GD_M1}

In conjunction with (1) formula and (2) formula, then the dynamic electric voltage of difference sampled output signal is

$\mathrm{\Δ}{V}_{\mathrm{DIFF}}=\mathrm{\Δ}{V}_{\mathrm{OUTP}}-\mathrm{\Δ}{V}_{\mathrm{OUTN}}=-\frac{C_{\mathrm{GD}\_M1}}{C_{\mathrm{GD}\_M1}+C_0}(\mathrm{VIN}1-\mathrm{VIN}2)---\left(3\right)$

By (3) formula as seen, the clock feed-through effect that parasitic capacitance is introduced between field effect transistor M1 grid leak is directly proportional with differential input signal to the error that the difference sampled output signal brings, and dynamic electric voltage to change be non-linear, simultaneously can't be by differential configuration elimination itself.In addition, the parasitic capacitance of field effect transistor M1 is larger, input signal amplitude is larger, and it is non-linear more obvious that this clock feed-through effect is introduced, and has a strong impact on the precision of difference sampled output signal.

Therefore, be necessary to provide a kind of improved ADC sample circuit to overcome defects.

The utility model content

The purpose of this utility model provides a kind of ADC sample circuit, described ADC sample circuit has reduced the impact of clock feed-through effect on signal sampling, improved the linearity of sampling field effect transistor, reduced the total harmonic distortion of ADC sample circuit, and improved sample rate, improved the sampling precision of ADC sample circuit.

For achieving the above object, the utility model provides a kind of ADC sample circuit, this sample circuit, comprise an external input terminals, one sample circuit and the auxiliary circuit that links to each other with described external input terminals, one clock circuit that links to each other with described sample circuit and outside output, a clock feedthrough circuit that links to each other with described auxiliary circuit, described clock feedthrough circuit also link to each other with outside output with described clock circuit respectively.

Preferably, described clock circuit has the first output and the second output, and the clock pulse of described the first output and the second output output complementation; Described sample circuit is sampled to the signal of external input terminals input under the control of the clock pulse of the first output output of described clock circuit, and the signal that obtains of will sampling exports outside output to; Described auxiliary circuit is sampled to the signal of external input terminals input under the control of described sample circuit, and the signal that obtains of will sampling is preserved; Described clock feedthrough compensated circuit is under the clock control of the second output output of described clock circuit, the signal that described auxiliary circuit sampling obtains is processed, thereby produce one with described sample circuit in the transient state bucking voltage of dynamic electric voltage opposite direction, and export described transient state bucking voltage to outside output.

Preferably, described sample circuit comprises the first Bootstrap unit and the first field effect transistor, two inputs of described the first Bootstrap unit are connected with the first output and the external input terminals of described clock circuit respectively, the output of described the first Bootstrap unit is connected with the grid of described the first field effect transistor, the source electrode of described the first field effect transistor is connected with external input terminals, the signal after the drain electrode output sampling of described the first field effect transistor.

Preferably, described ADC sample circuit also comprises the first electric capacity, and an end of described the first electric capacity is connected with the drain electrode of described the first field effect transistor, and other end ground connection is preserved with signal and voltage that described sample circuit sampling is obtained.

Preferably, described auxiliary circuit comprises the second field effect transistor and the second electric capacity, the grid of described the second field effect transistor is connected with the grid of described the first field effect transistor, its source electrode is connected with external input terminals, described the second field effect transistor is sampled to the signal of external input terminals input under the control of described sample circuit, described the second electric capacity one end is connected with the drain electrode of described the second field effect transistor, other end ground connection, the signal and the voltage thereof that obtain to preserve described the second field effect transistor sampling.

Preferably, described clock feedthrough compensated circuit comprises the 3rd field effect transistor and the second Bootstrap unit, two inputs of described the second Bootstrap unit are connected with the second output of described clock circuit and an end of the second electric capacity respectively, described the second Bootstrap unit output is connected with the grid of described the 3rd field effect transistor, and the drain electrode of described the 3rd field effect transistor all is connected with outside output with source electrode.

Preferably, a described field effect transistor has identical parameter with the second field effect transistor.

Preferably, the grid leak parasitic capacitance of described the 3rd field effect transistor equates with the grid leak parasitic capacitance of the first field effect transistor with the gate-source parasitic capacitance sum.

Compared with prior art, ADC sample circuit of the present utility model is by the sampling of described auxiliary circuit to external input signal, and the signal after will sampling inputs to described clock feedthrough compensated circuit, described clock feedthrough compensated circuit is by the pulse control of clock circuit, the signal that sampling obtains to auxiliary circuit is processed, and produce one with sample circuit in the transient state bucking voltage of dynamic electric voltage opposite direction, and export described transient state bucking voltage to outside output, thereby described transient state bucking voltage can partly or entirely be offset clock feed-through effect in the sample circuit effectively on the impact of signal sampling, improved the linearity of sampling field effect transistor, reduced the total harmonic distortion of ADC sample circuit, and improved sample rate, improved the sampling precision of adc circuit.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Description of drawings

Fig. 1 is the circuit theory diagrams of prior art ADC sample circuit.

Fig. 2 is the structured flowchart of the utility model ADC sample circuit.

Fig. 3 is the circuit theory diagrams of the utility model ADC sample circuit.

Embodiment

With reference now to accompanying drawing, embodiment of the present utility model is described.As mentioned above, the utility model provides a kind of ADC sample circuit, and described ADC sample circuit has improved the linearity of sampling field effect transistor, has reduced the total harmonic distortion of ADC sample circuit, has improved sample rate, and has improved the sampling precision of adc circuit.

Please refer to Fig. 2, the utility model ADC sample circuit comprises an external input terminals, one sample circuit and the auxiliary circuit that links to each other with described external input terminals, one clock circuit that links to each other with described sample circuit and outside output, the one clock feedthrough circuit that links to each other with described auxiliary circuit, described clock feedthrough circuit also link to each other with outside output with described clock circuit respectively.Wherein, the pulse of described clock circuit output clock also is connected with described sample circuit and clock feedthrough compensating circuit respectively, thereby described clock circuit controls described sample circuit by clock pulse and clock feedthrough compensating circuit carries out work; Described sample circuit is connected with external input terminals and outside output, under the control of described clock pulse, the signal of external input terminals input sampled, and through outside output output sampled signal; Described auxiliary circuit is connected with described sample circuit, external input terminals and clock feedthrough compensating circuit respectively, described auxiliary circuit is sampled to the signal of external input terminals input under the control of described sample circuit, and the preservation sampled result inputs to sampled signal described clock feedthrough compensated circuit simultaneously; Described clock feedthrough compensated circuit is connected with outside output, and the signal that under the control of described clock pulse the auxiliary circuit sampling is obtained is processed, produce one with sample circuit in the transient state bucking voltage of dynamic electric voltage opposite direction, and this transient state bucking voltage exported to outside output; The transient state bucking voltage stack of the sampled signal of described sample circuit sampling output and dynamic electric voltage and the output of described clock feedthrough compensated circuit is by described output output, thereby described transient state bucking voltage can effectively reduce even offset the clock feed-through effect of sample circuit generation to the impact of whole circuit structure, therefore improve sample rate, and improved the sampling precision of ADC sample circuit.

Particularly, please again in conjunction with reference to figure 3.As preferred implementation of the present utility model, described ADC sample circuit also comprises the first resistance C1.Wherein, described clock circuit has the first output K1 and the second output K2, and the clock pulse of described the first output K1 and the second output K2 output complementation; That is to say, when described the first output K1 is output as high level, described the second output K2 output low level; And the saltus step of two output level also is opposite, and when the level of described the first output K1 output was low level by the high level saltus step, this moment, the level of described the second output K2 output was high level by low transition.Described sample circuit comprises the first Bootstrap unit and the first field effect transistor MS; Described auxiliary circuit comprises the second field effect transistor MSA and the second capacitor C 2, and described the first field effect transistor MS has identical parameter with the second field effect transistor MSA; Described clock feedthrough compensated circuit comprises the second Bootstrap unit and the 3rd field effect transistor MD; In preferred implementation of the present utility model, described the first Bootstrap unit and the second Bootstrap cellular construction and function are identical, and are well known to the skilled person, and are not described in detail in this.

The physical circuit annexation of the utility model ADC sample circuit preferred embodiments is as follows: two inputs of described the first Bootstrap unit are connected with the first output K1 and the external input terminals of described clock circuit respectively, an input of external input terminals input signal VINP to the first Bootstrap unit; The output of the first Bootstrap unit is connected with the grid of the first field effect transistor MS, and the voltage of the output of described the first Bootstrap unit output is V1; The source electrode of the first field effect transistor MS is connected with external input terminals, and its drain electrode is connected the drain electrode output signal VOUTB of the first field effect transistor MS with outside output; Drain electrode at the first field effect transistor M1 also is connected with the first capacitor C 1, the other end ground connection of described the first capacitor C 1.The grid of described the second field effect transistor MSA is connected with the grid of the first field effect transistor MS, and its source electrode is connected with external input terminals, and output signal VOUTA; Described the second capacitor C 2 one ends are connected other end ground connection with the drain electrode of described the second field effect transistor MSA; Two inputs of described the second Bootstrap unit are connected with the second output K2 and second capacitor C 2 of described clock circuit respectively; The output of the second Bootstrap unit is connected with the grid of the 3rd field effect transistor MD, and output voltage V 2, and the drain electrode of described the 3rd field effect transistor MD all is connected with outside output with source electrode.

In the practical application of the utility model ADC sample circuit, circuit adopts the fully differential structure, and oppositely input circuit is identical with forward input circuit structure, be structure shown in Figure 3, difference only is that in reverse input circuit, the signal VINP of input input is reverse signal, and in the forward input circuit, the signal VINP of input input is forward signal.

Please again in conjunction with reference to figure 2-3, the operation principle of the utility model ADC sample circuit is described.

The function of Bootstrap unit is that output exceeds a fixing voltage VC than input when its control clock is high level, and the control clock is output as low level (voltage is 0) when being low level.So, in the utility model, when K1 is high level, when K2 is low level, output voltage V 1 and the electrical potential difference between the input signal VINP of the first Bootstrap unit are constant voltage VC, be V1=VINP+VC, V1 is high level, and the output voltage of the second Bootstrap unit that is to say the grid voltage V2=0 of the 3rd field effect transistor MD; At this moment, the first field effect transistor MS samples to the input signal VINP of external input terminals, and by the output output signal VOUTB in its drain electrode, described output signal VOUTB is stored on described the first capacitor C 1, so that output signal VOUTB can not change because of the variation of the output K1 output low level of clock circuit; And the second field effect transistor MSA conducting is also sampled to VINP, and by the output output signal VOUTA in its drain electrode, and VOUTA=VOUTB=VINP, wherein, described output signal VOUTA is stored on described the second capacitor C 2, so that output signal VOUTA can not change because of the variation of the output K1 output low level of clock circuit.Similarly, when K2 is high level, when K1 is low level, signal VOUTA can input to described the second Bootstrap unit, and output voltage V 2 and the electrical potential difference between the input signal VOUTA of the second Bootstrap unit are constant voltage VC, be V2=VOUTA+VC, namely V2 is high level, the grid voltage V1=0 of the first field effect transistor MS.

Wherein, the equiva lent impedance of the first field effect transistor MS is

$R_{\mathrm{MS}}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(V1-\mathrm{VINP}-\mathrm{VTH})}=\frac{1}{k{(W/L)}_{\mathrm{MS}}(\mathrm{VC}-\mathrm{VTH})}---\left(1\right)$

K is the constant relevant with technique in the formula (1), (W/L) _MSBe the breadth length ratio of the first field effect transistor MS, VTH is the threshold voltage of MS, because VC is constant voltage, can find out R by formula (1) _MSImpedance be constant, thereby improved the linearity of the first field effect transistor MS equiva lent impedance, simultaneously because the first capacitor C 1 be the homeostasis value, guaranteed that the first field effect transistor MS is that constant T1(is time constant T1=R to the time that input signal VINP samples _MS* C1), so that the first field effect transistor MS can carry out stable sampling to input signal VINP.

In the forward input circuit, when K1 is converted to low level by high level, also be that K2 is high level by low transition, the V1 voltage of this moment drops to 0 level by high level VINP+VC, V1=0, namely exporting V1 is low level, so that described the first field effect transistor MS and the second field effect transistor MSA all can not sample to input signal VINP, also namely by the sampling to input signal VINP of clock circuit control sample circuit and auxiliary circuit.In this process, the first field effect transistor MS of sample circuit has introduced clock feedthrough, clock feed-through effect so that the change in voltage that is present among the output signal VOUTB be

$\mathrm{\Δ}{V}_{\mathrm{OUTP}}=-\frac{C_{P\_\mathrm{GD}\_\mathrm{MS}}}{C_{P\_\mathrm{GD}\_\mathrm{MS}}+C_{P-1}}(\mathrm{VINP}+\mathrm{VC})---\left(2\right)$

C in the formula _{P_GD_MS}Be the parasitic capacitance between forward end the first field effect transistor MS grid leak, C _P-1Be the electric capacity of the first capacitor C 1 in the forward input circuit, VINP is the magnitude of voltage of forward input circuit, and is changed to low level owing to the K1 level is changed to from high level, so change in voltage Δ V _OUTPBe negative value.

When circuit adopted the fully differential structure, oppositely input circuit was identical with forward input circuit structure, and then the change in voltage in the sample circuit output signal of reverse input circuit is

$\mathrm{\Δ}{V}_{\mathrm{OUTN}}=-\frac{C_{N\_\mathrm{GD}\_\mathrm{MS}}}{C_{N\_\mathrm{GD}\_\mathrm{MS}}+C_{N-1}}(\mathrm{VINN}+\mathrm{VC})---\left(3\right)$

C in the formula _{N_GD_MS}Be the parasitic capacitance between the first field effect transistor MS grid leak in the negater circuit, VINN is the magnitude of voltage of oppositely inputting, C _{N_1}Be the electric capacity of the first capacitor C 1 of negater circuit, because the forward input is identical with the structure of reverse input circuit, so C _{N_GD_MS}=C _{P_GD_MS}=C _{GD_MS}, C _{N_1}=C _{P_1}=C ₁

In conjunction with (2) formula and (3) formula, then the dynamic electric voltage of difference sampled output signal is

$\mathrm{\Δ}{V}_{\mathrm{DIFF}}=\mathrm{\Δ}{V}_{\mathrm{OUTP}}-\mathrm{\Δ}{V}_{\mathrm{OUTP}}=-\frac{C_{\mathrm{GD}\_\mathrm{MS}}}{C_{\mathrm{GD}\_\mathrm{MS}}+C_1}(\mathrm{VINP}-\mathrm{VINN})---\left(4\right)$

By (4) formula as seen, the clock feed-through effect that the first field effect transistor MS grid of sample circuit-drain terminal parasitic capacitance is introduced is directly proportional with differential input signal to the error that the difference sampled output signal brings, and is nonlinear, and can't eliminates by differential configuration.And the parasitic capacitance of the first field effect transistor MS is larger, input signal amplitude is larger, and it is non-linear more obvious that this clock feed-through effect is introduced.

K1 is converted to the low level while by high level, and K2 is high level by low transition; At this moment, output voltage V 2 and the electrical potential difference between the input signal VOUTA of the second Bootstrap unit are constant voltage VC, be V2=VOUTA+VC, and because VOUTA=VOUTB=VINP, thereby the input signal of the input signal of described the second Bootstrap unit and the first Bootstrap unit is identical, also be so that size and the V1 of output voltage V 2 are identical at this moment, thereby the voltage V1 when voltage V2 is high level with K1 when K2 is high level is identical, but opposite direction; This moment, the output V2 of the second grid voltage boostrap circuit was

V2＝VOUTA+VC＝VINP+VC （5）

The parasitic capacitance of setting the grid end of the 3rd field effect transistor MD in the clock feedthrough compensated circuit in the forward input circuit is C _{P_G_MD}, then the output voltage that causes of clock feedthrough compensated circuit is changed to

$\mathrm{\Δ}{V}_{\mathrm{OUTP}\_F}=\frac{C_{P\_G\_\mathrm{MD}}}{C_{P\_G\_\mathrm{MD}}+C_1}(\mathrm{VINP}+\mathrm{VC})---\left(6\right)$ In the same oppositely input circuit, the output voltage that the clock feedthrough compensated circuit causes is changed to

$\mathrm{\Δ}{V}_{\mathrm{OUTN}\_F}=\frac{C_{N\_G\_\mathrm{MD}}}{C_{N\_G\_\mathrm{MD}}+C_1}(\mathrm{VINN}+\mathrm{VC})---\left(7\right)$

C in the formula _{N_G_MD}Grid parasitic capacitance for the 3rd field effect transistor MD in the reverse input circuit.Because be the circuit symmetrical structure, so

C _{N_G_MD}=C _{P_G_MD}=C _{G_MD}, then in the difference channel structure, the transient state bucking voltage of clock feedthrough compensated circuit output is

$\mathrm{\Δ}{V}_{\mathrm{DIFF}\_F}=\mathrm{\Δ}{V}_{\mathrm{OUTP}\_F}-\mathrm{\Δ}{V}_{\mathrm{OUTP}\_F}=\frac{C_{G\_\mathrm{MD}}}{C_{G\_\mathrm{MD}}+C_1}(\mathrm{VINP}-\mathrm{VINN})---\left(8\right)$

In the utility model, because the grid leak parasitic capacitance of described the 3rd field effect transistor MD equates with the grid leak parasitic capacitance of gate-source parasitic capacitance sum with the first field effect transistor MS, then the parasitic capacitance of described the 3rd field effect transistor MD is half of parasitic capacitance of the first field effect transistor MS, that is to say parasitic capacitance C _{G_MD}=C _{GD_MS}, in substitution (4) formula and (8) formula, can draw the 3rd field effect transistor MD externally output produced a transient state bucking voltage with formula (4) equal and opposite in direction, opposite direction.And the signal VOUTP of outside output output, to be exported by the sampled signal of described sample circuit sampling output and the transient state bucking voltage stack of dynamic electric voltage and the output of described clock feedthrough compensated circuit, thereby transient state bucking voltage that described clock feedthrough compensated circuit produces has been offset dynamic electric voltage that the first field effect transistor MS produces because of clock feed-through effect to the impact of sampled output signal in the difference sampled output signal, do not affect simultaneously the normal output of sampled signal, improved the linearity of sampling field effect transistor (i.e. the first field effect transistor MS), reduced the total harmonic distortion of ADC sample circuit, and improved sample rate, improved the sampling precision of adc circuit.

Abovely in conjunction with most preferred embodiment the utility model is described, but the utility model is not limited to the embodiment of above announcement, and should contains various modification, equivalent combinations of carrying out according to essence of the present utility model.

Claims (8)

1. ADC sample circuit, it is characterized in that, comprise an external input terminals, one sample circuit and the auxiliary circuit that links to each other with described external input terminals, one clock circuit that links to each other with described sample circuit and outside output, the one clock feedthrough circuit that links to each other with described auxiliary circuit, described clock feedthrough circuit also link to each other with outside output with described clock circuit respectively.

2. ADC sample circuit as claimed in claim 1 is characterized in that,

Described clock circuit has the first output and the second output, and the clock pulse of described the first output and the second output output complementation;

Described sample circuit is sampled to the signal of described external input terminals input under the control of the clock pulse of the first output output of described clock circuit, and the signal that obtains of will sampling exports described outside output to;

Described auxiliary circuit is sampled to the signal of described external input terminals input under the control of described sample circuit, and the signal that obtains of will sampling is preserved;

Described clock feedthrough compensated circuit is under the clock control of the second output output of described clock circuit, the signal that the auxiliary circuit sampling obtains is processed, and produce one with sample circuit in the transient state bucking voltage of dynamic electric voltage opposite direction, and export described transient state bucking voltage to outside output.

3. ADC sample circuit as claimed in claim 2 is characterized in that, also comprises the first electric capacity, and an end of described the first electric capacity is connected with the drain electrode of described the first field effect transistor, and other end ground connection is preserved with signal and voltage that described sample circuit sampling is obtained.

4. ADC sample circuit as claimed in claim 3, it is characterized in that, described sample circuit comprises the first Bootstrap unit and the first field effect transistor, two inputs of described the first Bootstrap unit are connected with the first output and the external input terminals of described clock circuit respectively, the output of described the first Bootstrap unit is connected with the grid of described the first field effect transistor, the source electrode of described the first field effect transistor is connected with external input terminals, the signal after the drain electrode output sampling of described the first field effect transistor.

5. ADC sample circuit as claimed in claim 4, it is characterized in that, described auxiliary circuit comprises the second field effect transistor and the second electric capacity, the grid of described the second field effect transistor is connected with the grid of described the first field effect transistor, its source electrode is connected with external input terminals, described the second field effect transistor is sampled to the signal of external input terminals input under the control of described sample circuit, described the second electric capacity one end is connected with the drain electrode of described the second field effect transistor, other end ground connection, the signal and the voltage thereof that obtain to preserve described the second field effect transistor sampling.

6. ADC sample circuit as claimed in claim 5, it is characterized in that, described clock feedthrough compensated circuit comprises the 3rd field effect transistor and the second Bootstrap unit, two inputs of described the second Bootstrap unit are connected with the second output of described clock circuit and an end of the second electric capacity respectively, described the second Bootstrap unit output is connected with the grid of described the 3rd field effect transistor, and the drain electrode of described the 3rd field effect transistor all is connected with output with source electrode.

7. ADC sample circuit as claimed in claim 6 is characterized in that, described the first field effect transistor has identical parameter with the second field effect transistor.

8. ADC sample circuit as claimed in claim 6 is characterized in that, the grid leak parasitic capacitance of described the 3rd field effect transistor equates with the grid leak parasitic capacitance of the first field effect transistor with the gate-source parasitic capacitance sum.

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