CN101562453B - Analog sampling switch and analog-to-digital converter - Google Patents
Analog sampling switch and analog-to-digital converter Download PDFInfo
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- CN101562453B CN101562453B CN2008102273949A CN200810227394A CN101562453B CN 101562453 B CN101562453 B CN 101562453B CN 2008102273949 A CN2008102273949 A CN 2008102273949A CN 200810227394 A CN200810227394 A CN 200810227394A CN 101562453 B CN101562453 B CN 101562453B
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Abstract
The invention discloses an analog sampling switch and an analog-to-digital converter using the same. The analog sampling switch comprises a sampling switch circuit which comprises a sampling switch tube, and is used for controlling conduction state of the sampling switch tube; and a comparator circuit for comparing input signal level and output signal level of the sampling switch tube, and taking a higher level terminal as a source electrode of the sampling switch tube. The analog sampling switch and the analog-to-digital converter can track the source electrode of the switch tube, eliminate nonlinear relation between the switch conduction resistance and input signals, enhance linearity of the whole sampling switch, and meet high-speed and high-precision requirements of a sampling holding circuit.
Description
Technical field
The present invention relates generally to field of analog integrated circuit, relates in particular to a kind of analog sampling switch and analog to digital converter.
Background technology
Along with DSP (Digital Signal Processing, Digital Signal Processing) development of technology and dsp processor, increasing analog signal need change into digital signal and handle, this just feasible interface-ADC (Analog-to-Digital Converter, analog to digital converter) to analog signal and digital signal has higher requirement.SHA (Sample and Hold Amplifiers, sampling hold circuit) is as vital unit in the analog to digital converter, and the quality of its performance is the performance of decision whole system directly.Raising along with the sampling clock frequency, conventional MOS (metal oxide semiconductor, metal-oxide semiconductor (MOS)) sampling switch is subject to non-ideal effects, non-linear such as conducting resistance, electric charge injects, clock feedthrough etc., its linearity constantly descends, and has seriously restricted the dynamic range of sampling hold circuit; Simultaneously, because the decline of supply voltage, applied clock voltage lift technique will run into certain difficulty, and can bring the decline of device reliability.Therefore traditional MOS sampling switch structure can't satisfy at a high speed, high-precision adc is to the requirement of sampled signal dynamic property.
At this nonlinear distortion characteristics of conventional switch, the researcher has proposed multiple solution both at home and abroad.A kind of is the analog sampling switch that adopts the grid voltage bootstrapping, and constant by maintained switch pipe gate source voltage reduces the non-linear of switch conduction resistance; A kind of is to adopt complementary CMOS (complementarymetal-oxide semiconductor, complementary metal oxide semiconductors (CMOS)) passgate structures, utilize PMOS transistor (P-channel metal oxide semiconductor FET, the P-channel metal-oxide-semiconductor field-effect transistor) to eliminate switch non-linear with the accurate coupling of nmos pass transistor (N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor) size; A kind of is the reproduction switch Manifold technology, realizes the metal-oxide-semiconductor that duplicates that is in linear working state by adopting resistor voltage divider circuit, makes it have identical threshold voltage with the sampling metal-oxide-semiconductor; Also having a kind of is exactly on the basis of grid voltage bootstrapping, adopts stable switch pipe lining source voltage, eliminates transistor back of the body matrix effect and improves switch performance.
The inventor finds in realizing process of the present invention, there is following shortcoming at least in prior art: these solutions are not all considered the characteristic that the tracking of switching tube source electrode changes, in the PMOS of reality transistor, source electrode is always followed the high potential in input and the output signal, the situation of nmos pass transistor is then just the opposite, so the fixing design of source electrode will unavoidably produce nonlinear distortion.Simultaneously, the maintenance error that electric charge injects and clock feed-through effect causes also be can not ignore.
Summary of the invention
The present invention proposes a kind of analog sampling switch and analog to digital converter, can follow the tracks of the source electrode of switching tube, eliminate the non-linear relation of switch conduction resistance and input signal, improved the linearity of whole sampling switch, satisfied the needs of high speed, high-precision sampling hold circuit.
The technical scheme of the embodiment of the invention is achieved in that
A kind of analog sampling switch comprises:
Sampling switch circuit, described sampling switch circuit comprises the sampling switch pipe, described sampling switch circuit is used to control the conducting state of described sampling switch pipe;
Comparator circuit is used for the height of more described sampling switch pipe input signal current potential and output signal current potential, with the source electrode of hot end as described sampling switch pipe.
Preferably, described sampling switch circuit comprises:
The one PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor;
A described PMOS transistor is as the sampling switch pipe, and the transistorized source electrode of a described PMOS links to each other with the input signal port, and a described PMOS transistor drain is connected with output signal end;
Described the 2nd PMOS transistor drain is connected with the transistorized grid of a described PMOS, the transistorized source electrode of described the 2nd PMOS is connected with described the 3rd PMOS transistor drain, the transistorized grid of described the 2nd PMOS connects with reference to ground, described the 2nd PMOS transistor avoids described the 3rd PMOS transistor to puncture because source-drain voltage is higher than supply voltage as permanent conduction pipe;
The transistorized source electrode of described the 3rd PMOS is connected with supply voltage, and the transistorized grid of described the 3rd PMOS is connected with clock control signal, and described the 3rd PMOS transistor is controlled the transistorized on off state of a described PMOS as the clock control pipe.
Preferably, described sampling switch circuit also comprises:
The first floating battery structure when being used for the clock high potential, reduces the grid potential of described sampling switch pipe.
Preferably, the described first floating battery structure comprises:
The 4th PMOS transistor and first electric capacity;
The transistorized grid of described the 4th PMOS connects power supply, and the transistorized source electrode of described the 4th PMOS connects the external signal that is produced by the clock boostrap circuit;
The negative pole of described first electric capacity connects described the 2nd PMOS transistor drain, and the positive pole of described first electric capacity links to each other with described the 4th PMOS transistor drain, as floating battery.
Preferably, described sampling switch circuit also comprises:
The source voltage control circuit is used for the true source pole tension signal of described sampling switch pipe is connected to its grid, realizes the constant of described sampling switch pipe gate source voltage.
Preferably, described source voltage control circuit comprises:
The 5th nmos pass transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th nmos pass transistor, the 9th nmos pass transistor and second electric capacity;
The transistorized source electrode of described the 6th PMOS connects power supply, the transistorized grid of described the 6th PMOS connects clock signal, the positive pole of described second electric capacity is connected with described the 6th PMOS transistor drain, the negative pole of described second electric capacity links to each other with the drain electrode of described the 9th nmos pass transistor, the grid of described the 9th nmos pass transistor connects the clock inverted signal, the source electrode of described the 9th nmos pass transistor connects with reference to ground, constitutes the second floating battery structure;
The transistorized source electrode of described the 7th PMOS links to each other with the drain electrode of described the 8th nmos pass transistor, described the 7th PMOS transistor drain links to each other with the source electrode of described the 8th nmos pass transistor, the transistorized grid of described the 7th PMOS connects clock signal, the grid of described the 8th nmos pass transistor connects the clock inverted signal, constitutes passgate structures;
The source electrode of described the 5th nmos pass transistor links to each other with the positive pole of described first electric capacity, the grid of described the 5th nmos pass transistor links to each other with the positive pole of described second electric capacity, the transistorized substrate terminal of a described PMOS is connected with the drain electrode of described the 5th nmos pass transistor, source signal is transferred to the grid of described sampling switch pipe when the clock high potential.
Preferably, described comparator circuit comprises:
The tenth PMOS transistor, the 11 PMOS transistor, the 12 PMOS transistor, the 13 PMOS transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 4th electric capacity;
Transistorized source electrode of described the tenth PMOS and the transistorized source electrode of described the 11 PMOS connect power supply, transistorized grid of described the tenth PMOS and the transistorized grid short circuit of described the 11 PMOS, described the tenth PMOS transistor drain and described the 11 PMOS transistor drain short circuit;
The transistorized source electrode of described the 12 PMOS is connected with described the tenth PMOS transistor drain, the transistorized source electrode of described the 13 PMOS is connected with described the 11 PMOS transistor drain, the transistorized grid of described the 12 PMOS is connected with the grid of described the 14 nmos pass transistor, the positive input of device as a comparison, the transistorized grid of described the 13 PMOS is connected with the grid of described the 15 nmos pass transistor, as a comparison the reverse input end of device;
Described the 12 PMOS transistor drain is connected with the drain electrode of described the 14 nmos pass transistor, be shorted to the grid of transistorized grid of described the tenth PMOS and described the 16 nmos pass transistor simultaneously, for it provides bias voltage, described the 13 PMOS transistor drain is connected with the drain electrode of described the 15 nmos pass transistor, as a comparison the output of device;
The source electrode of described the 14 nmos pass transistor connects the drain electrode of described the 16 nmos pass transistor, the source electrode of described the 15 nmos pass transistor connects the drain electrode of described the 17 nmos pass transistor, the source electrode of described the 16 nmos pass transistor and the source ground of described the 17 nmos pass transistor, the grid of described the 16 nmos pass transistor and the grid short circuit of described the 17 nmos pass transistor, the drain electrode of described the 16 nmos pass transistor and the drain electrode short circuit of described the 17 nmos pass transistor;
The positive pole of described the 4th electric capacity is connected with comparator output terminal, and the minus earth of described the 4th electric capacity is as filter capacitor.
Preferably, also comprise:
The 18 nmos pass transistor, the 19 PMOS transistor, the 20 PMOS transistor, the 21 nmos pass transistor and the 3rd electric capacity;
The source electrode of described the 18 nmos pass transistor and described the 19 PMOS transistor drain connect input signal, the drain electrode of described the 18 nmos pass transistor and the transistorized source electrode of described the 19 PMOS connect the transistorized substrate terminal of a described PMOS, the drain electrode of described the 20 nmos pass transistor and the transistorized source electrode of described the 21 PMOS connect output signal end, the drain electrode of transistorized source electrode of described the 20 PMOS and described the 21 nmos pass transistor connects the transistorized substrate terminal of a described PMOS, the grid of described the 18 nmos pass transistor and the transistorized grid of described the 20 PMOS connect comparator output signal, transistorized grid of described the 19 PMOS and described the 21 nmos pass transistor grid connect comparator output inverted signal, device trigger switch as a comparison;
The positive pole of described the 3rd electric capacity is connected with output, and the minus earth of described the 3rd electric capacity as sampling capacitance, is sampled to output signal.
A kind of analog to digital converter comprises the analog sampling switch, and described analog sampling switch comprises:
Sampling switch circuit, described sampling switch circuit comprises the sampling switch pipe, described sampling switch circuit is used to control the conducting state of described sampling switch pipe;
Comparator circuit is used for the height of more described sampling switch pipe input signal current potential and output signal current potential, with the source electrode of hot end as described sampling switch pipe.
Preferably, described sampling switch circuit comprises:
The one PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor;
A described PMOS transistor is as the sampling switch pipe, and the transistorized source electrode of a described PMOS links to each other with the input signal port, and a described PMOS transistor drain is connected with output signal end;
Described the 2nd PMOS transistor drain is connected with the transistorized grid of a described PMOS, the transistorized source electrode of described the 2nd PMOS is connected with described the 3rd PMOS transistor drain, the transistorized grid of described the 2nd PMOS connects with reference to ground, described the 2nd PMOS transistor avoids described the 3rd PMOS transistor to puncture because source-drain voltage is higher than supply voltage as permanent conduction pipe;
The transistorized source electrode of described the 3rd PMOS is connected with supply voltage, and the transistorized grid of described the 3rd PMOS is connected with clock control signal, and described the 3rd PMOS transistor is controlled the transistorized on off state of a described PMOS as the clock control pipe.
Preferably, described sampling switch circuit also comprises:
The first floating battery structure when being used for the clock high potential, reduces the grid potential of described sampling switch pipe.
Preferably, the described first floating battery structure comprises:
The 4th PMOS transistor and first electric capacity;
The transistorized grid of described the 4th PMOS connects power supply, and the transistorized source electrode of described the 4th PMOS connects the external signal that is produced by the clock boostrap circuit;
The negative pole of described first electric capacity connects described the 2nd PMOS transistor drain, and the positive pole of described first electric capacity links to each other with described the 4th PMOS transistor drain, as floating battery.
Preferably, described sampling switch circuit also comprises:
The source voltage control circuit is used for the true source pole tension signal of described sampling switch pipe is connected to its grid, realizes the constant of described sampling switch pipe gate source voltage.
Preferably, described source voltage control circuit comprises:
The 5th nmos pass transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th nmos pass transistor, the 9th nmos pass transistor and second electric capacity;
The transistorized source electrode of described the 6th PMOS connects power supply, the transistorized grid of described the 6th PMOS connects clock signal, the positive pole of described second electric capacity is connected with described the 6th PMOS transistor drain, the negative pole of described second electric capacity links to each other with the drain electrode of described the 9th nmos pass transistor, the grid of described the 9th nmos pass transistor connects the clock inverted signal, the source electrode of described the 9th nmos pass transistor connects with reference to ground, constitutes the second floating battery structure;
The transistorized source electrode of described the 7th PMOS links to each other with the drain electrode of described the 8th nmos pass transistor, described the 7th PMOS transistor drain links to each other with the source electrode of described the 8th nmos pass transistor, the transistorized grid of described the 7th PMOS connects clock signal, the grid of described the 8th nmos pass transistor connects the clock inverted signal, constitutes passgate structures;
The source electrode of described the 5th nmos pass transistor links to each other with the positive pole of described first electric capacity, the grid of described the 5th nmos pass transistor links to each other with the positive pole of described second electric capacity, the transistorized substrate terminal of a described PMOS is connected with the drain electrode of described the 5th nmos pass transistor, source signal is transferred to the grid of described sampling switch pipe when the clock high potential.
Preferably, described comparator circuit comprises:
The tenth PMOS transistor, the 11 PMOS transistor, the 12 PMOS transistor, the 13 PMOS transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 4th electric capacity;
Transistorized source electrode of described the tenth PMOS and the transistorized source electrode of described the 11 PMOS connect power supply, transistorized grid of described the tenth PMOS and the transistorized grid short circuit of described the 11 PMOS, described the tenth PMOS transistor drain and described the 11 PMOS transistor drain short circuit;
The transistorized source electrode of described the 12 PMOS is connected with described the tenth PMOS transistor drain, the transistorized source electrode of described the 13 PMOS is connected with described the 11 PMOS transistor drain, the transistorized grid of described the 12 PMOS is connected with the grid of described the 14 nmos pass transistor, the positive input of device as a comparison, the transistorized grid of described the 13 PMOS is connected with the grid of described the 15 nmos pass transistor, as a comparison the reverse input end of device;
Described the 12 PMOS transistor drain is connected with the drain electrode of described the 14 nmos pass transistor, be shorted to the grid of transistorized grid of described the tenth PMOS and described the 16 nmos pass transistor simultaneously, for it provides bias voltage, described the 13 PMOS transistor drain is connected with the drain electrode of described the 15 nmos pass transistor, as a comparison the output of device;
The source electrode of described the 14 nmos pass transistor connects the drain electrode of described the 16 nmos pass transistor, the source electrode of described the 15 nmos pass transistor connects the drain electrode of described the 17 nmos pass transistor, the source electrode of described the 16 nmos pass transistor and the source ground of described the 17 nmos pass transistor, the grid of described the 16 nmos pass transistor and the grid short circuit of described the 17 nmos pass transistor, the drain electrode of described the 16 nmos pass transistor and the drain electrode short circuit of described the 17 nmos pass transistor;
The positive pole of described the 4th electric capacity is connected with comparator output terminal, and the minus earth of described the 4th electric capacity is as filter capacitor.
Preferably, also comprise:
The 18 nmos pass transistor, the 19 PMOS transistor, the 20 PMOS transistor, the 21 nmos pass transistor and the 3rd electric capacity;
The source electrode of described the 18 nmos pass transistor and described the 19 PMOS transistor drain connect input signal, the drain electrode of described the 18 nmos pass transistor and the transistorized source electrode of described the 19 PMOS connect the transistorized substrate terminal of a described PMOS, the drain electrode of described the 20 nmos pass transistor and the transistorized source electrode of described the 21 PMOS connect output signal end, the drain electrode of transistorized source electrode of described the 20 PMOS and described the 21 nmos pass transistor connects the transistorized substrate terminal of a described PMOS, the grid of described the 18 nmos pass transistor and the transistorized grid of described the 20 PMOS connect comparator output signal, transistorized grid of described the 19 PMOS and described the 21 nmos pass transistor grid connect comparator output inverted signal, device trigger switch as a comparison;
The positive pole of described the 3rd electric capacity is connected with output, and the minus earth of described the 3rd electric capacity as sampling capacitance, is sampled to output signal.
Analog sampling switch of the present invention and analog to digital converter, utilize comparator circuit that the height of sampling switch pipe input signal current potential and output signal current potential is compared, with hot end wherein as the source electrode of sampling switch pipe, its signal is connected respectively to the substrate and the grid of switching tube, realized the really constant of sampling switch pipe gate source voltage and threshold voltage, conducting resistance and input signal are irrelevant, have reduced the switch nonlinear distortion, have improved the linearity of analog sampling switch.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the composition structure chart of a kind of analog sampling switch of the present invention preferred embodiment;
Fig. 2 is the physical circuit schematic diagram of sampling switch circuit 10 described in Fig. 1;
Fig. 3 is the physical circuit schematic diagram of comparator circuit 20 described in Fig. 1;
Fig. 4 is the physical circuit schematic diagram of analog sampling switch preferred embodiment of the present invention;
Fig. 5 is the signal relation schematic diagram.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
With reference to Fig. 1, show the composition structure chart of a kind of analog sampling switch of the present invention preferred embodiment, described analog sampling switch comprises:
Described sampling switch circuit 10 adopts the grid voltage bootstrap technique, is used for the State Control of sampling switch, and the gate source voltage of described sampling switch pipe equals supply voltage all the time.
Described comparator circuit 20 adopts complementary bias circuit construction, by PMOS differential pair and nmos differential to being formed by stacking, its bias voltage provides according to the amplifier internal node, keeps stable by negative feedback loop, the influence that not changed by technological parameter or calculation condition.
With reference to Fig. 2, show the physical circuit schematic diagram of sampling switch circuit described in Fig. 1 10.
Described sampling switch circuit 10 comprises: a PMOS transistor 101, the 2nd PMOS transistor 102, the 3rd PMOS transistor 103, the 4th PMOS transistor 104, the 5th nmos pass transistor 105, the 6th PMOS transistor 106, the 7th PMOS transistor 107, the 8th nmos pass transistor 108, the 9th nmos pass transistor 109, first capacitor C 1, second capacitor C 2 and the 3rd capacitor C 3.
Wherein, the source electrode of a described PMOS transistor 101 links to each other with the input signal port, and the drain electrode of a described PMOS transistor 101 is connected with output signal end; A described PMOS transistor 101 is as the sampling switch pipe.The drain electrode of described the 2nd PMOS transistor 102 is connected with the grid of a described PMOS transistor 101, and the source electrode of described the 2nd PMOS transistor 102 is connected with the drain electrode of described the 3rd PMOS transistor 103, and the grid of described the 2nd PMOS transistor 102 connects with reference to ground; Described the 2nd PMOS transistor 102 is as permanent conduction pipe, avoids described the 3rd PMOS transistor 103 to puncture because source-drain voltage is higher than supply voltage.The source electrode of described the 3rd PMOS transistor 103 is connected with supply voltage, the grid of described the 3rd PMOS transistor 103 is connected with clock control signal, described the 3rd PMOS transistor 103 is controlled the on off state of a described PMOS transistor 101 as the clock control pipe.
The grid of described the 4th PMOS transistor 104 connects power supply, and the source electrode of described the 4th PMOS transistor 104 meets external signal V, and described signal V is produced by the clock boostrap circuit in the external world.The negative pole of described first capacitor C 1 connects the drain electrode of described the 2nd PMOS transistor 102, and the positive pole of described first capacitor C 1 links to each other with the drain electrode of described the 4th PMOS transistor 104, as floating battery.The source electrode of described the 6th PMOS transistor 106 connects power supply, the grid of described the 6th PMOS transistor 106 connects clock signal, the positive pole of described second capacitor C 2 is connected with the drain electrode of described the 6th PMOS transistor 106, the negative pole of described second capacitor C 2 links to each other with the drain electrode of described the 9th nmos pass transistor 109, the grid of described the 9th nmos pass transistor 109 connects the clock inverted signal, the source electrode of described the 9th nmos pass transistor 109 connects with reference to ground, constitutes the second floating battery structure; The source electrode of described the 7th PMOS transistor 107 links to each other with the drain electrode of described the 8th nmos pass transistor 108, the drain electrode of described the 7th PMOS transistor 107 is connected with the source electrode of the 8th nmos pass transistor 108, the grid of described the 7th PMOS transistor 107 connects clock signal, the grid of described the 8th nmos pass transistor 108 connects the clock inverted signal, constitutes passgate structures (construction of switch); The source electrode of described the 5th nmos pass transistor 105 and 1 anodal connection of first capacitor C, the grid of described the 5th nmos pass transistor 105 is connected with the positive pole of second capacitor C 2, the substrate terminal of a described PMOS transistor 101 is connected with the drain electrode of described the 5th nmos pass transistor 105, source signal is transferred to the grid of sampling switch pipe when the clock high potential, described the 3rd capacitor C 3 is as the sampling capacitance sampled output signal simultaneously.
First capacitor C 1 in the described sampling switch circuit 10 and second capacitor C 2 are shared effect as floating battery for dealing with electric charge, and described first capacitor C 1 and described second capacitor C 2 all require enough big, and preferred value is 0.5p-1.8p.Simultaneously by dwindling switching tube, described the 2nd PMOS transistor 102, described the 4th PMOS transistor 104, the size of described the 5th nmos pass transistor 105 reduces parasitic capacitance, but the switching tube size reduces and will directly cause conducting resistance to increase, switching speed reduces, influence signals sampling, therefore, the compromise of precision and speed also is that emphasis is considered among the present invention.
In various embodiments of the present invention and accompanying drawing, described input signal is represented with Vin, output signal represents that with Vout clock signal represents that with clk the clock inverted signal is represented with clk, power supply is represented with Vdd, comparator output signal represents that with Vtri comparator output inverted signal represents that with Vtri positive input is represented with Vin+, reverse input end represents that with Vin-earthy Gnd represents.
With reference to Fig. 3, show the physical circuit schematic diagram of comparator circuit described in Fig. 1 20.
Described comparator circuit 20 comprises the tenth PMOS transistor the 110, the 11 PMOS transistor the 111, the 12 PMOS transistor the 112, the 13 PMOS transistor the 113, the 14 nmos pass transistor the 114, the 15 nmos pass transistor the 115, the 16 nmos pass transistor the 116, the 17 nmos pass transistor 117 and the 4th capacitor C 4.
Wherein, the source electrode of described the tenth PMOS transistor 110 and the source electrode of described the 11 PMOS transistor 111 connect power supply, the grid short circuit of the grid of described the tenth PMOS transistor 110 and described the 11 PMOS transistor 111, the drain electrode short circuit of the drain electrode of described the tenth PMOS transistor 110 and the 11 PMOS transistor 111; The source electrode of described the 12 PMOS transistor 112 is connected with the drain electrode of described the tenth PMOS transistor 110, the source electrode of described the 13 PMOS transistor 113 is connected with the drain electrode of described the 11 PMOS transistor 111, the grid of described the 12 PMOS transistor 112 is connected with the grid of the 14 nmos pass transistor 114, as a comparison the positive input of device; The grid of described the 13 PMOS transistor 113 is connected with the grid of described the 15 nmos pass transistor 115, as a comparison the reverse input end of device; The drain electrode of described the 12 PMOS transistor 112 is connected with the drain electrode of described the 14 nmos pass transistor 114, is shorted to the grid of described the tenth PMOS transistor 110 and the grid of the 16 nmos pass transistor 116 simultaneously, for it provides biasing; The drain electrode of described the 13 PMOS transistor 113 is connected with the drain electrode of described the 15 nmos pass transistor 115, as a comparison the output of device.The source electrode of described the 14 nmos pass transistor 114 connects the drain electrode of described the 16 nmos pass transistor 116, and the source electrode of described the 15 nmos pass transistor 115 connects the drain electrode of described the 17 nmos pass transistor 117; The source electrode of described the 16 nmos pass transistor 116 and the source ground of described the 17 nmos pass transistor 117, the grid short circuit of the grid of described the 16 nmos pass transistor 116 and described the 17 nmos pass transistor 117, the drain electrode short circuit of the drain electrode of described the 16 nmos pass transistor 116 and described the 17 nmos pass transistor 117.The positive pole of described the 4th capacitor C 4 is connected with comparator output terminal, and the minus earth of described the 4th capacitor C 4 is as filter capacitor.
Further, also comprise, also comprise the 18 nmos pass transistor the 118, the 19 PMOS transistor the 119, the 20 PMOS transistor the 120, the 21 nmos pass transistor 121.
The source electrode of described the 18 nmos pass transistor 118 and 119 drain electrodes of the 19 PMOS transistor connect the sampling switch input signal, the drain electrode of described the 18 nmos pass transistor 118 and the 19 PMOS transistor 119 source electrodes connect the substrate terminal of a described PMOS transistor 101, the drain electrode of described the 20 nmos pass transistor and the 21 PMOS transistor source connect the sampling switch output signal end, and the source electrode of described the 20 PMOS transistor 120 and 121 drain electrodes of the 21 nmos pass transistor connect the substrate terminal of a described PMOS transistor 101; The grid of described the 18 nmos pass transistor 118 and the 20 PMOS transistor 120 grids connect comparator output signal, the grid of described the 19 PMOS transistor 119 and the 21 nmos pass transistor 121 grids connect comparator output inverted signal, device trigger switch as a comparison.
With reference to Fig. 4, show the physical circuit schematic diagram of analog sampling switch preferred embodiment of the present invention.The concrete composition of described analog sampling switch and circuit are connected among Fig. 2, Fig. 3 and are described in detail, and no longer repeat at this, and the description that reaches Fig. 2, Fig. 3 with reference to Fig. 4 gets final product.
With reference to Fig. 5, the present invention utilizes 20 pairs of sampling inputs of high-speed comparator circuit to compare with output signal, with hot end wherein as the source electrode of sampling switch pipe, its signal is connected respectively to the substrate and the grid of switching tube, realized the really constant of sampling switch pipe gate source voltage and threshold voltage, conducting resistance and input signal are irrelevant.When the clock signal was low level, described the 2nd PMOS crystal and 103 conductings of described the 3rd PMOS transistor were moved a described PMOS sampling pipe grid voltage to V
Dd, this moment, the sampling switch pipe ended, and circuit is in hold mode.Meanwhile, the source voltage of described the 4th PMOS transistor 104 is booted to 2V
DdMake 104 conductings of described the 4th PMOS transistor, described the 11 PMOS transistor 111 is also opened with described the 13 PMOS transistor 113, and described first capacitor C 1 and described second capacitor C, 2 bulk charges are to V
Dd, as floating battery.This moment, though the grid voltage of described the 5th nmos pass transistor 105 is charged to V
Dd, but 2V
DdSource voltage it is in end.When the clock signal jumps to high potential, described the 2nd PMOS transistor 102 and described the 3rd PMOS transistor 103 turn-off, opened with the transmission gate that described the 8th nmos pass transistor 108 constitutes by described the 7th PMOS transistor 107, the grid voltage of described the 5th nmos pass transistor 105 is from V
DdBe charged to V
Dd+ V
In, real source voltage is sent to the sampling switch tube grid by described the 5th nmos pass transistor 105, makes the grid voltage of switching tube can be all the time to be lower than V of source voltage
DdForm follow the tracks of to change a described PMOS transistor 101 conductings this moment, described the 3rd capacitor C 3 sampled output signals.Comparator main effect herein is the size of input signal and previous moment output signal more this moment, with the higher end of signal potential as the real source electrode of sampling switch pipe, trigger the transmission gate of forming by described the 18 nmos pass transistor 118 and described the 19 PMOS transistor 119 or described the 20 PMOS transistor 120 and described the 21 nmos pass transistor 121 simultaneously, the voltage transmission of real source electrode to sampling pipe grid and substrate terminal, is realized the constant of sampling switch pipe overdrive voltage and threshold voltage.The specific implementation process is as follows, if V
InV
Out, V then
s=V
In, V
g=V
In-V
Dd, V
Sg=V
Dd, V
Thp=V
Th0If V
OutV
In, V then
s=V
Out, V
g=V
Out-V
Dd, V
Sg=V
Dd, V
Thp=V
Th0This moment conducting resistance R
OnIrrelevant with the input signal variation, as shown in the formula:
Wherein, R
OnThe expression conducting resistance, u
pThe expression hole mobility, C
OxThe expression gate oxide thickness,
Represent transistorized breadth length ratio, V
sExpression source voltage, V
gThe expression gate voltage, V
SgThe expression gate source voltage, V
ThThe expression threshold voltage.
The present invention utilizes comparator circuit that the height of sampling switch pipe input signal current potential and output signal current potential is compared, with hot end wherein as the source electrode of sampling switch pipe, its signal is connected respectively to the substrate and the grid of switching tube, realized the really constant of sampling switch pipe gate source voltage and threshold voltage, conducting resistance and input signal are irrelevant, reduce the switch nonlinear distortion, improved the linearity of analog sampling switch.
The embodiment of the invention also discloses a kind of analog to digital converter, described analog to digital converter comprises the analog sampling switch, and described analog sampling switch comprises:
Sampling switch circuit, described sampling switch circuit comprises the sampling switch pipe, described sampling switch circuit is used to control the conducting state of described sampling switch pipe;
Comparator circuit is used for the height of more described sampling switch pipe input signal current potential and output signal current potential, with the source electrode of hot end as described sampling switch pipe.
The physical circuit schematic diagram of described analog sampling switch and the course of work and the operation principle of described analog sampling switch are described in detail in front, consider for length, do not repeat them here.Description with reference to appropriate section among Fig. 1, Fig. 2, Fig. 3, Fig. 4 gets final product.
The above only is preferred embodiment of the present invention, and is in order to restriction the present invention, within the spirit and principles in the present invention not all, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (16)
1. an analog sampling switch is characterized in that, comprising:
Sampling switch circuit, described sampling switch circuit comprises the sampling switch pipe, described sampling switch circuit is used to control the conducting state of described sampling switch pipe;
Comparator circuit is used for the height of more described sampling switch pipe input signal current potential and output signal current potential, with the source electrode of hot end as described sampling switch pipe, and the signal of hot end is connected respectively to the substrate and the grid of described sampling switch pipe.
2. analog sampling switch according to claim 1 is characterized in that, described sampling switch circuit comprises:
The one PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor;
A described PMOS transistor is as the sampling switch pipe, and the transistorized source electrode of a described PMOS links to each other with the input signal port, and a described PMOS transistor drain is connected with output signal end;
Described the 2nd PMOS transistor drain is connected with the transistorized grid of a described PMOS, the transistorized source electrode of described the 2nd PMOS is connected with described the 3rd PMOS transistor drain, the transistorized grid of described the 2nd PMOS connects with reference to ground, described the 2nd PMOS transistor avoids described the 3rd PMOS transistor to puncture because source-drain voltage is higher than supply voltage as permanent conduction pipe;
The transistorized source electrode of described the 3rd PMOS is connected with supply voltage, and the transistorized grid of described the 3rd PMOS is connected with clock control signal, and described the 3rd PMOS transistor is controlled the transistorized on off state of a described PMOS as the clock control pipe.
3. analog sampling switch according to claim 2 is characterized in that, described sampling switch circuit also comprises:
The first floating battery structure when being used for the clock high potential, reduces the grid potential of described sampling switch pipe.
4. analog sampling switch according to claim 3 is characterized in that, the described first floating battery structure comprises:
The 4th PMOS transistor and first electric capacity;
The transistorized grid of described the 4th PMOS connects power supply, and the transistorized source electrode of described the 4th PMOS connects the external signal that is produced by the clock boostrap circuit;
The negative pole of described first electric capacity connects described the 2nd PMOS transistor drain, and the positive pole of described first electric capacity links to each other with described the 4th PMOS transistor drain, as floating battery.
5. analog sampling switch according to claim 4 is characterized in that, described sampling switch circuit also comprises:
The source voltage control circuit is used for the source voltage signal of described sampling switch pipe is connected to its grid, realizes the constant of described sampling switch pipe gate source voltage.
6. analog sampling switch according to claim 5 is characterized in that, described source voltage control circuit comprises:
The 5th nmos pass transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th nmos pass transistor, the 9th nmos pass transistor and second electric capacity;
The transistorized source electrode of described the 6th PMOS connects power supply, the transistorized grid of described the 6th PMOS connects clock signal, the positive pole of described second electric capacity is connected with described the 6th PMOS transistor drain, the negative pole of described second electric capacity links to each other with the drain electrode of described the 9th nmos pass transistor, the grid of described the 9th nmos pass transistor connects the clock inverted signal, the source electrode of described the 9th nmos pass transistor connects with reference to ground, constitutes the second floating battery structure;
The transistorized source electrode of described the 7th PMOS links to each other with the drain electrode of described the 8th nmos pass transistor, described the 7th PMOS transistor drain links to each other with the source electrode of described the 8th nmos pass transistor, the transistorized grid of described the 7th PMOS connects clock signal, the grid of described the 8th nmos pass transistor connects the clock inverted signal, constitutes passgate structures;
The source electrode of described the 5th nmos pass transistor links to each other with the positive pole of described first electric capacity, the grid of described the 5th nmos pass transistor links to each other with the positive pole of described second electric capacity, the transistorized substrate terminal of a described PMOS is connected with the drain electrode of described the 5th nmos pass transistor, source signal is transferred to the grid of described sampling switch pipe when the clock high potential.
7. analog sampling switch according to claim 6 is characterized in that, described comparator circuit comprises:
The tenth PMOS transistor, the 11 PMOS transistor, the 12 PMOS transistor, the 13 PMOS transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 4th electric capacity;
Transistorized source electrode of described the tenth PMOS and the transistorized source electrode of described the 11 PMOS connect power supply, transistorized grid of described the tenth PMOS and the transistorized grid short circuit of described the 11 PMOS, described the tenth PMOS transistor drain and described the 11 PMOS transistor drain short circuit;
The transistorized source electrode of described the 12 PMOS is connected with described the tenth PMOS transistor drain, the transistorized source electrode of described the 13 PMOS is connected with described the 11 PMOS transistor drain, the transistorized grid of described the 12 PMOS is connected with the grid of described the 14 nmos pass transistor, the positive input of device as a comparison, the transistorized grid of described the 13 PMOS is connected with the grid of described the 15 nmos pass transistor, as a comparison the reverse input end of device;
Described the 12 PMOS transistor drain is connected with the drain electrode of described the 14 nmos pass transistor, be shorted to the grid of transistorized grid of described the tenth PMOS and described the 16 nmos pass transistor simultaneously, for it provides bias voltage, described the 13 PMOS transistor drain is connected with the drain electrode of described the 15 nmos pass transistor, as a comparison the output of device;
The source electrode of described the 14 nmos pass transistor connects the drain electrode of described the 16 nmos pass transistor, the source electrode of described the 15 nmos pass transistor connects the drain electrode of described the 17 nmos pass transistor, the source electrode of described the 16 nmos pass transistor and the source ground of described the 17 nmos pass transistor, the grid of described the 16 nmos pass transistor and the grid short circuit of described the 17 nmos pass transistor, the drain electrode of described the 16 nmos pass transistor and the drain electrode short circuit of described the 17 nmos pass transistor;
The positive pole of described the 4th electric capacity is connected with comparator output terminal, and the minus earth of described the 4th electric capacity is as filter capacitor.
8. analog sampling switch according to claim 7 is characterized in that, also comprises:
The 18 nmos pass transistor, the 19 PMOS transistor, the 20 PMOS transistor, the 21 nmos pass transistor and the 3rd electric capacity;
The source electrode of described the 18 nmos pass transistor and described the 19 PMOS transistor drain connect input signal, the drain electrode of described the 18 nmos pass transistor and the transistorized source electrode of described the 19 PMOS connect the transistorized substrate terminal of a described PMOS, the drain electrode of described the 20 nmos pass transistor and the transistorized source electrode of described the 21 PMOS connect output signal end, the drain electrode of transistorized source electrode of described the 20 PMOS and described the 21 nmos pass transistor connects the transistorized substrate terminal of a described PMOS, the grid of described the 18 nmos pass transistor and the transistorized grid of described the 20 PMOS connect comparator output signal, transistorized grid of described the 19 PMOS and described the 21 nmos pass transistor grid connect comparator output inverted signal, device trigger switch as a comparison;
The positive pole of described the 3rd electric capacity is connected with output, and the minus earth of described the 3rd electric capacity as sampling capacitance, is sampled to output signal.
9. an analog to digital converter is characterized in that, comprises the analog sampling switch, and described analog sampling switch comprises:
Sampling switch circuit, described sampling switch circuit comprises the sampling switch pipe, described sampling switch circuit is used to control the conducting state of described sampling switch pipe;
Comparator circuit is used for the height of more described sampling switch pipe input signal current potential and output signal current potential, with the source electrode of hot end as described sampling switch pipe, and the signal of hot end is connected respectively to the substrate and the grid of described sampling switch pipe.
10. analog to digital converter according to claim 9 is characterized in that, described sampling switch circuit comprises:
The one PMOS transistor, the 2nd PMOS transistor and the 3rd PMOS transistor;
A described PMOS transistor is as the sampling switch pipe, and the transistorized source electrode of a described PMOS links to each other with the input signal port, and a described PMOS transistor drain is connected with output signal end;
Described the 2nd PMOS transistor drain is connected with the transistorized grid of a described PMOS, the transistorized source electrode of described the 2nd PMOS is connected with described the 3rd PMOS transistor drain, the transistorized grid of described the 2nd PMOS connects with reference to ground, described the 2nd PMOS transistor avoids described the 3rd PMOS transistor to puncture because source-drain voltage is higher than supply voltage as permanent conduction pipe;
The transistorized source electrode of described the 3rd PMOS is connected with supply voltage, and the transistorized grid of described the 3rd PMOS is connected with clock control signal, and described the 3rd PMOS transistor is controlled the transistorized on off state of a described PMOS as the clock control pipe.
11. analog to digital converter according to claim 10 is characterized in that, described sampling switch circuit also comprises:
The first floating battery structure when being used for the clock high potential, reduces the grid potential of described sampling switch pipe.
12. analog to digital converter according to claim 11 is characterized in that, the described first floating battery structure comprises:
The 4th PMOS transistor and first electric capacity;
The transistorized grid of described the 4th PMOS connects power supply, and the transistorized source electrode of described the 4th PMOS connects the external signal that is produced by the clock boostrap circuit;
The negative pole of described first electric capacity connects described the 2nd PMOS transistor drain, and the positive pole of described first electric capacity links to each other with described the 4th PMOS transistor drain, as floating battery.
13. analog to digital converter according to claim 12 is characterized in that, described sampling switch circuit also comprises:
The source voltage control circuit is used for the source voltage signal of described sampling switch pipe is connected to its grid, realizes the constant of described sampling switch pipe gate source voltage.
14. analog to digital converter according to claim 13 is characterized in that, described source voltage control circuit comprises:
The 5th nmos pass transistor, the 6th PMOS transistor, the 7th PMOS transistor, the 8th nmos pass transistor, the 9th nmos pass transistor and second electric capacity;
The transistorized source electrode of described the 6th PMOS connects power supply, the transistorized grid of described the 6th PMOS connects clock signal, the positive pole of described second electric capacity is connected with described the 6th PMOS transistor drain, the negative pole of described second electric capacity links to each other with the drain electrode of described the 9th nmos pass transistor, the grid of described the 9th nmos pass transistor connects the clock inverted signal, the source electrode of described the 9th nmos pass transistor connects with reference to ground, constitutes the second floating battery structure;
The transistorized source electrode of described the 7th PMOS links to each other with the drain electrode of described the 8th nmos pass transistor, described the 7th PMOS transistor drain links to each other with the source electrode of described the 8th nmos pass transistor, the transistorized grid of described the 7th PMOS connects clock signal, the grid of described the 8th nmos pass transistor connects the clock inverted signal, constitutes passgate structures;
The source electrode of described the 5th nmos pass transistor links to each other with the positive pole of described first electric capacity, the grid of described the 5th nmos pass transistor links to each other with the positive pole of described second electric capacity, the transistorized substrate terminal of a described PMOS is connected with the drain electrode of described the 5th nmos pass transistor, source signal is transferred to the grid of described sampling switch pipe when the clock high potential.
15. analog to digital converter according to claim 14 is characterized in that, described comparator circuit comprises:
The tenth PMOS transistor, the 11 PMOS transistor, the 12 PMOS transistor, the 13 PMOS transistor, the 14 nmos pass transistor, the 15 nmos pass transistor, the 16 nmos pass transistor, the 17 nmos pass transistor, the 4th electric capacity;
Transistorized source electrode of described the tenth PMOS and the transistorized source electrode of described the 11 PMOS connect power supply, transistorized grid of described the tenth PMOS and the transistorized grid short circuit of described the 11 PMOS, described the tenth PMOS transistor drain and described the 11 PMOS transistor drain short circuit;
The transistorized source electrode of described the 12 PMOS is connected with described the tenth PMOS transistor drain, the transistorized source electrode of described the 13 PMOS is connected with described the 11 PMOS transistor drain, the transistorized grid of described the 12 PMOS is connected with the grid of described the 14 nmos pass transistor, the positive input of device as a comparison, the transistorized grid of described the 13 PMOS is connected with the grid of described the 15 nmos pass transistor, as a comparison the reverse input end of device;
Described the 12 PMOS transistor drain is connected with the drain electrode of described the 14 nmos pass transistor, be shorted to the grid of transistorized grid of described the tenth PMOS and described the 16 nmos pass transistor simultaneously, for it provides bias voltage, described the 13 PMOS transistor drain is connected with the drain electrode of described the 15 nmos pass transistor, as a comparison the output of device;
The source electrode of described the 14 nmos pass transistor connects the drain electrode of described the 16 nmos pass transistor, the source electrode of described the 15 nmos pass transistor connects the drain electrode of described the 17 nmos pass transistor, the source electrode of described the 16 nmos pass transistor and the source ground of described the 17 nmos pass transistor, the grid of described the 16 nmos pass transistor and the grid short circuit of described the 17 nmos pass transistor, the drain electrode of described the 16 nmos pass transistor and the drain electrode short circuit of described the 17 nmos pass transistor;
The positive pole of described the 4th electric capacity is connected with comparator output terminal, and the minus earth of described the 4th electric capacity is as filter capacitor.
16. analog to digital converter according to claim 15 is characterized in that, also comprises:
The 18 nmos pass transistor, the 19 PMOS transistor, the 20 PMOS transistor, the 21 nmos pass transistor and the 3rd electric capacity;
The source electrode of described the 18 nmos pass transistor and described the 19 PMOS transistor drain connect input signal, the drain electrode of described the 18 nmos pass transistor and the transistorized source electrode of described the 19 PMOS connect the transistorized substrate terminal of a described PMOS, the drain electrode of described the 20 nmos pass transistor and the transistorized source electrode of described the 21 PMOS connect output signal end, the drain electrode of transistorized source electrode of described the 20 PMOS and described the 21 nmos pass transistor connects the transistorized substrate terminal of a described PMOS, the grid of described the 18 nmos pass transistor and the transistorized grid of described the 20 PMOS connect comparator output signal, transistorized grid of described the 19 PMOS and described the 21 nmos pass transistor grid connect comparator output inverted signal, device trigger switch as a comparison;
The positive pole of described the 3rd electric capacity is connected with output, and the minus earth of described the 3rd electric capacity as sampling capacitance, is sampled to output signal.
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| CN101977056B (en) * | 2010-09-21 | 2013-07-03 | 中国电子科技集团公司第五十八研究所 | Charge transfer circuit suitable for common CMOS process and charge transfer control switch thereof |
| CN101986570B (en) * | 2010-11-02 | 2013-07-24 | 西安电子科技大学 | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof |
| US8816887B2 (en) * | 2012-09-21 | 2014-08-26 | Analog Devices, Inc. | Sampling circuit, a method of reducing distortion in a sampling circuit, and an analog to digital converter including such a sampling circuit |
| CN104158537B (en) * | 2014-08-28 | 2017-04-05 | 杭州士兰微电子股份有限公司 | Transmission gate line construction |
| CN109361393A (en) | 2014-12-26 | 2019-02-19 | 华为技术有限公司 | A kind of analog-digital converter and D conversion method |
| US9407276B1 (en) * | 2015-06-23 | 2016-08-02 | Silicon Laboratories Inc. | Reducing distortion in an analog-to-digital converter |
| CN106130555B (en) * | 2016-07-06 | 2019-11-05 | 中国电子科技集团公司第二十四研究所 | The bootstrap voltage mode generation circuit of bootstrapped switch |
| CN107094013B (en) * | 2017-04-17 | 2019-02-12 | 电子科技大学 | A kind of transmission gate circuit |
| CN107888192B (en) * | 2017-11-23 | 2021-06-08 | 北京时代民芯科技有限公司 | Circuit for improving linearity of dynamic switch in analog-to-digital converter |
| CN109787631B (en) * | 2018-12-19 | 2020-07-17 | 西安电子科技大学 | Millimeter wave analog sampling front-end circuit |
| CN113225055B (en) * | 2021-04-21 | 2024-02-13 | 深圳市国微电子有限公司 | Charge injection cancellation circuit, analog switch circuit, and sampling device |
| CN113536060B (en) * | 2021-06-23 | 2024-04-16 | 上海市计算技术研究所有限公司 | Data acquisition device and method, electronic device and computer storage medium |
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