CN102571091B - Analog-to-digital converter and electronic equipment - Google Patents
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Abstract
The invention provides an analog-to-digital converter and electronic equipment and belongs to the field of analog circuit design. According to a gate-voltage bootstrapped switch circuit in the analog-to-digital converter, two transistors are connected with each other through a transmission gate (TG) and connected with an input signal Vin. By connecting the two transistors through the TG, influence of charge injection and clock feed-through on the input signal Vin can be effectively eliminated, and sampling accuracy is improved.
Description
Technical field
The present invention relates to Analog Circuit Design field, particularly a kind of analog to digital converter and electronic equipment.
Background technology
Along with the high speed development of integrated circuit technique, communication system is more and more higher to the demand of high-performance analog to digital converter (ADC), the sampling of ADC front end keeps (S/H) circuit will meet high speed, high linearity, high-precision requirement, and the performance quality of sampling switch has determined that S/H circuit receives the precision of signal conventionally.High linear sampling switch at a high speed can effectively reduce the impact of the non-linear factor such as charge injection and clock feedthrough on sampling input, thereby improves sampling accuracy.
As shown in Figure 1 and Figure 2, they have comprised respectively an electric capacity and a switches set to Bootstrap switching circuit.Wherein Fig. 1 is switches set off-state, and Fig. 2 is switches set conducting state, and Vin is sampled input signal, and Vout is sampling output, and Cbat is charge and discharge capacitance, and VDD is supply voltage high level, and GND is supply voltage low level.
Shown in Fig. 1 is Bootstrap switching circuit switches set off-state, nmos switch pipe ground connection, and Cbat is charged to supply voltage VDD simultaneously; Bootstrapped switch switches set conducting under the control of next clock phase, as shown in Figure 2, Cbat two ends are connected with the grid source of nmos switch pipe, and the gate source voltage Vgs that makes NMOS pipe is that Vg-Vin equals VDD.
The conducting resistance expression formula of MOS sampling switch is:
Wherein, μ is electronics or hole mobility, C
oxgate oxide electric capacity, V
thbe threshold voltage, W/L is metal-oxide-semiconductor breadth length ratio.
Visible, conducting resistance Ron is a nonlinear resistance relevant to input signal.
In the situation that technique is certain, reducing conducting resistance has two kinds of approach: the one, and increase the size of pipe, but increased ghost effect and limited space; The 2nd, by increasing overdrive voltage (Vg-Vin-Vth), in the situation that Vg is fixing, Vgs can change along with Vin, and the linearity reduces.
Can keep Vgs constant by Bootstrap switching circuit for this reason, thereby make conducting resistance irrelevant with input wire size, reduce the impact of the dynamic property on circuit.
It is VDD that Bootstrap switching circuit shown in Fig. 1, Fig. 2 keeps the Vgs of nmos switch pipe under conducting state, thereby ensure the linearity of conducting resistance, can well realize sampling switch function, that the while size of charge pump electric capacity also can have a huge impact entire area because being directly connected with input of clock can introducing charge injection and clock feed-through effect.In prior art, in various concrete boostrap circuits, charge injection and clock feedthrough can exert an influence to input signal Vin, and sampling precision is lower.
In prior art, exist as can be seen here: the problem that boostrap circuit sampling precision is lower.
Summary of the invention
In order to address the above problem, the object of the embodiment of the present invention is to provide a kind of analog to digital converter and electronic equipment, and analog to digital converter comprises:
Transistor seconds, the 4th transistor, the 5th transistor, the 6th transistor, the tenth transistor, the 11 transistor, the tenth two-transistor and charge and discharge capacitance, wherein,
Transistor seconds, its drain electrode connects supply voltage VDD, grid connects second clock signal, source electrode connects the top crown of the 6th transistorized source electrode and charge and discharge capacitance, second clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 4th transistor, its source electrode connects sampled input signal Vin, grid connects the 4th clock signal, drain electrode connects the bottom crown of charge and discharge capacitance, the 6th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 4th transistor is N-type transistor;
The 5th transistor, its drain electrode connects sampled input signal Vin, grid connects the 5th clock signal, source electrode connects the bottom crown of charge and discharge capacitance, the 5th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 5th transistor is P transistor npn npn;
The 6th transistor, its grid is with source shorted and be connected the 6th clock signal, drain electrode connects the source electrode of the tenth two-transistor, the 6th clock signal is in the time that clock input signal is the first level state, drain electrode and source electrode are disconnected, in the time that clock input signal is second electrical level state, make the level signal of drain electrode and source electrode conducting;
The tenth transistor, its grid connects the tenth clock signal, the tenth transistorized source electrode connects ground GND, the tenth transistorized drain electrode connects the bottom crown of charge and discharge capacitance, the tenth clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 11 transistor, its source electrode, drain electrode connect respectively sampled input signal Vin and sampled output signal Vout, and grid connects the 6th transistor drain;
The tenth two-transistor, its grid connects the 12 clock signal, the drain electrode of the tenth two-transistor connects ground GND, the 12 clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected.
Further, transistor seconds, the 4th transistor, the tenth transistor, the 11 transistor and the tenth two-transistor are nmos pass transistor, and the 5th transistor and the 6th transistor are PMOS transistor.
Further, the first level state is supply voltage VDD, and second electrical level state is ground GND.
Further, also comprise:
The 13 transistor, its grid connects the 13 clock signal, and source electrode connects supply voltage VDD, and drain electrode connects the source electrode of the tenth two-transistor, and 13 clock signals and the 12 clock signal are same clock signal, the 13 transistor is PMOS transistor.
Further, also comprise:
The first electric capacity, its top crown connects the grid of transistor seconds, and bottom crown connects clock input signal;
The first transistor, its grid, drain electrode connect supply voltage VDD, and source electrode connects the grid of transistor seconds, and the first transistor is nmos pass transistor.
Further, also comprise:
The 9th transistor, its grid connects the 11 transistorized grid, and drain electrode connects the 4th transistor source, and source electrode connects the bottom crown of charge and discharge capacitance, and the 9th transistor is nmos pass transistor.
Further, also comprise:
The 3rd transistor, its grid connects the 3rd clock signal, source electrode connects supply voltage VDD, drain electrode connects the 6th transistor gate, the 3rd clock signal, in the time that clock input signal is the first level state, makes drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected, the 3rd transistor is PMOS transistor.
Further, also comprise:
The 7th transistor, its grid connects the 6th transistor drain, and drain electrode connects the 6th transistor gate, and source electrode connects sampled input signal Vin, and the 7th transistor is nmos pass transistor.
Further, also comprise:
The 8th transistor, its grid connects supply voltage VDD, and drain electrode connects the tenth two-transistor source electrode, and source electrode connects the 6th transistor drain, and the 8th transistor is nmos pass transistor.
The embodiment of the present invention also provides a kind of electronic equipment, comprises analog to digital converter as the aforementioned on body.
Due to the 4th nmos pass transistor and the 5th nmos pass transistor employing TG connected mode, can effectively suppress charge injection and the impact of clock feedthrough on input signal Vin, improve the precision of sampling.
Brief description of the drawings
Fig. 1 represents that in prior art, the Bootstrap switching circuit switches set off-state in analog to digital converter realizes basic circuit diagram;
Fig. 2 represents that in prior art, the Bootstrap switching circuit switches set conducting state in analog to digital converter realizes basic circuit diagram;
Fig. 3 represents CMOS Bootstrap switching circuit schematic diagram of the present invention;
Fig. 4 represents CMOS Bootstrap switching circuit Transient oscillogram of the present invention;
Fig. 5 represents CMOS Bootstrap switching circuit sampled result spectrogram of the present invention.
Embodiment
Be described in detail below in conjunction with drawings and Examples.
In the embodiment of the present invention, preferably adopting CMOS transistor to realize other transistor of CMOS Bootstrap switching circuit in analog to digital converter realizes Bootstrap switching circuit and is suitable for too, the present embodiment CMOS Bootstrap switching circuit as shown in Figure 3, is the specific implementation to the Bootstrap switching circuit shown in Fig. 1,2.
This analog to digital converter, comprise 12 transistors and 2 electric capacity, in order better to describe in the present embodiment, what the first nmos pass transistor and the first transistor were described is same device, adopt the first nmos pass transistor to be described just for the reader that is more convenient for understands this transistorized type, remaining each transistor-like seemingly.Transistor seconds, the 4th transistor, the 5th transistor, the 6th transistor, the tenth transistor, the 11 transistor, the tenth two-transistor and charge and discharge capacitance C2 i.e. the second capacitor C 2 are the most basic devices of CMOS Bootstrap switching circuit in analog to digital converter, wherein
Transistor seconds, its drain electrode connects supply voltage VDD, grid connects second clock signal, source electrode connects the top crown of the 6th transistorized source electrode and charge and discharge capacitance, second clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 4th transistor, its source electrode connects sampled input signal Vin, grid connects the 4th clock signal, drain electrode connects the bottom crown of charge and discharge capacitance, the 6th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 4th transistor is N-type transistor;
The 5th transistor, its drain electrode connects sampled input signal Vin, grid connects the 5th clock signal, source electrode connects the bottom crown of charge and discharge capacitance, the 5th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 5th transistor is P transistor npn npn;
The 6th transistor, its grid is with source shorted and be connected the 6th clock signal, drain electrode connects the source electrode of the tenth two-transistor, the 6th clock signal is in the time that clock input signal is the first level state, drain electrode and source electrode are disconnected, in the time that clock input signal is second electrical level state, make the level signal of drain electrode and source electrode conducting;
The tenth transistor, its grid connects the tenth clock signal, the tenth transistorized source electrode connects ground GND, the tenth transistorized drain electrode connects the bottom crown of charge and discharge capacitance, the tenth clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 11 transistor, its source electrode, drain electrode connect respectively sampled input signal Vin and sampled output signal Vout, and grid connects the 6th transistor drain;
The tenth two-transistor, its grid connects the 12 clock signal, the drain electrode of the tenth two-transistor connects ground GND, the 12 clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected.
Keep Fig. 1,2 basic structure constant, the concrete implementing circuit of the embodiment of the present invention uses two electric capacity, reduces area compared with using three electric capacity with the concrete implementing circuit of prior art; The electric charge that simultaneously uses supply voltage VDD to provide in the time of sampling conducting, improves sample rate; The clock sampling transmission gate TG connected mode being connected with input Vs (being sampled input signal Vin) in order to suppress the non-linear factors such as clock charge injection and clock feed-through effect.
Annexation in the embodiment of the present invention shown in Fig. 3 when the specific implementation of the CMOS Bootstrap switching circuit of analog to digital converter is as follows:
The grid of the first nmos pass transistor M1 is all connected supply voltage VDD with drain electrode, and the drain electrode of the second nmos pass transistor M2 connects supply voltage VDD, and the source electrode of the first nmos pass transistor M1 is connected with the grid of the second nmos pass transistor M2.
The source electrode of the 6th PMOS transistor M6 is connected the source electrode of the second nmos pass transistor M2 with substrate, the drain electrode of the 6th PMOS transistor M6 is connected with the source electrode of the 8th nmos pass transistor M8, and the grid of the 8th nmos pass transistor M8 connects supply voltage VDD.
The source electrode of the 13 PMOS transistor M13, grid connect respectively supply voltage VDD and clock input signal CLK2, the source electrode of the tenth bi-NMOS transistor M12 connects the drain electrode of the 13 PMOS transistor M13, and grid, the drain electrode of the tenth bi-NMOS transistor M12 connect respectively clock input signal CLK2 and GND.
Charge pump capacitor C 1 i.e. the first capacitor C 1 top crown connects respectively the source electrode of the first nmos pass transistor M1 and the grid of the second nmos pass transistor M2, the first capacitor C 1 bottom crown connects clock input signal CLK2, and the grid of the tenth nmos pass transistor connects clock input signal CLK2.
Charge and discharge capacitance C2 top crown connects respectively the source electrode of the second nmos pass transistor M2 and the source electrode of the 6th PMOS transistor M6, and the second capacitor C 2 bottom crowns connect respectively the drain electrode of source electrode and the tenth nmos pass transistor M10 of the 9th nmos pass transistor M9.
Grid, the source electrode of the 3rd PMOS transistor M3 connect clock input signal CLK1 and supply voltage VDD, the drain electrode of the 3rd PMOS transistor M3 connects respectively the drain electrode of the 4th nmos pass transistor M4 and the source electrode of the 5th nmos pass transistor M5, clock input signal CLK1 is the reverse signal of clock input signal CLK2, in the time that CLK2 is VDD, CLK1 is GND, and in the time that CLK1 is VDD, CLK2 is GND.
The drain electrode of the 7th nmos pass transistor M7 connects respectively the drain electrode of grid and the 3rd PMOS transistor M3 of the 6th PMOS transistor M6, and the source electrode of the 7th nmos pass transistor M7 connects the source electrode of the 4th nmos pass transistor M4 and the drain electrode of the 5th nmos pass transistor M5.
The drain electrode of the 9th nmos pass transistor M9 connects respectively the 7th source electrode of nmos pass transistor M7 and the source electrode of the 11 nmos pass transistor M11.
The grid of the 11 nmos pass transistor M11 connects the grid of difference the 7th nmos pass transistor M7, source electrode and the 9th nmos pass transistor M9 grid of the 8th nmos pass transistor M8, and source electrode, the drain electrode of the 11 nmos pass transistor M11 connect respectively sampled input signal Vs and sampled output signal Vout.
The embodiment of the present invention has solved the specific implementation problem of sampling switch in sampling hold circuit (S/H), a kind of Bootstrap switching circuit that improves switch conduction sample rate and switched linear degree is provided, effectively reduce the area of conducting resistance and reduction circuit, realize high-speed, high precision sampling.
The conducting resistance expression formula of this practical CMOS Bootstrap switch is:
Wherein, μ is electronics or hole mobility, C
oxgate oxide electric capacity, V
thbe threshold voltage, W/L is metal-oxide-semiconductor breadth length ratio.
Visible, the gate source voltage Vgs (Vg-Vin) of the 11 nmos pass transistor equals supply voltage VDD, conducting resistance Ron is a nonlinear resistance relevant to input signal, thereby makes conducting resistance irrelevant with input wire size, reduces the impact of the dynamic property on circuit.
The embodiment of the present invention adopts two phase clock control signal CLK1 and CLK2.
CLK1 is that low level GND, CLK2 are while being high level VDD, the grid of the 11 nmos pass transistor is discharged to low level GND by the 8th nmos pass transistor, the tenth bi-NMOS transistor, and meanwhile supply voltage VDD charges in the second capacitor C 2 by the second nmos pass transistor, the tenth nmos pass transistor.
CLK1 is that high level VDD, CLK2 are while being low level GND, the 13 PMOS transistor turns the 8th nmos pass transistor works in dark linear zone, as switch conduction, the transistorized grid of the 6th PMOS is pulled to GND by the TG of the 4th nmos pass transistor and the 5th nmos pass transistor composition, the second capacitor C 2 top crowns are connected on the grid of the 11 nmos pass transistor, the bottom crown of the second capacitor C 2 is connected with the input signal Vs of the 11 nmos pass transistor by the 9th nmos pass transistor, thereby ensures that Vgs equals VDD.
Switch is in the time of sampling conducting state, under the control of clock signal, the 13 PMOS transistor, the 9th nmos pass transistor can be brought up to (2VDD-Vtp-2Vtn) by the transistorized source potential of the 6th PMOS, ensure that the transistorized gate source voltage of the 6th PMOS can beyond supply voltage VDD can effectively not improve the input amplitude of oscillation (Vtp, Vtn are respectively the threshold voltage of PMOS transistor and nmos pass transistor) of switching tube while making sampling input Vs very high.
The transistorized substrate of the 6th PMOS is connected with source electrode, can suppress breech lock (latch-up) effect of substrate, and meanwhile the buffer action of the 8th nmos pass transistor, the 9th nmos pass transistor also can effectively improve the reliability of circuit.
CMOS Bootstrap switching circuit of the present invention, under the control of clock signal, periodically to charge and discharge capacitance charging, and is added to the voltage on charge and discharge capacitance on the input signal of sampling switch pipe, to realize the function of Bootstrap.
CMOS Bootstrap switching circuit of the present invention is carried out to emulation, shown in Fig. 4 is CMOS Bootstrap switching circuit Transient oscillogram of the present invention, visible, under the control of clock signal, charge and discharge capacitance periodically charges, and has met Vgs=VDD; Shown in Fig. 5 is the difference output spectrum of 8192 sampled points of CMOS Bootstrap switching circuit sampled result of the present invention, visible, the Spurious Free Dynamic Range (SFDR) of CMOS Bootstrap switch of the present invention is 103.964349dB, the precision that can effectively meet 16 of ADC, realizes the better linearity and precision.
The embodiment of the present invention also provides a kind of electronic equipment, comprises analog to digital converter as the aforementioned on body.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; can also do some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. an analog to digital converter, is characterized in that, comprises, and transistor seconds, the 4th transistor, the 5th transistor, the 6th transistor, the tenth transistor, the 11 transistor, the tenth two-transistor and charge and discharge capacitance, wherein,
Transistor seconds, its drain electrode connects supply voltage VDD, grid connects second clock signal, source electrode connects the top crown of the 6th transistorized source electrode and charge and discharge capacitance, second clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 4th transistor, its source electrode connects sampled input signal Vin, grid connects the 4th clock signal, drain electrode connects the bottom crown of charge and discharge capacitance, the 4th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 4th transistor is N-type transistor;
The 5th transistor, its drain electrode connects sampled input signal Vin, grid connects the 5th clock signal, source electrode connects the bottom crown of charge and discharge capacitance, the 5th clock signal, in the time that clock input signal is the first level state, disconnects drain electrode and source electrode, in the time that clock input signal is second electrical level state, the level signal that makes drain electrode and source electrode conducting, the 5th transistor is P transistor npn npn;
The 6th transistor, its grid is with source shorted and be connected the 6th clock signal, drain electrode connects the source electrode of the tenth two-transistor, the 6th clock signal is in the time that clock input signal is the first level state, drain electrode and source electrode are disconnected, in the time that clock input signal is second electrical level state, make the level signal of drain electrode and source electrode conducting;
The tenth transistor, its grid connects the tenth clock signal, the tenth transistorized source electrode connects ground GND, the tenth transistorized drain electrode connects the bottom crown of charge and discharge capacitance, the tenth clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected;
The 11 transistor, its source electrode, drain electrode connect respectively sampled input signal Vin and sampled output signal Vout, and grid connects the 6th transistor drain;
The tenth two-transistor, its grid connects the 12 clock signal, the drain electrode of the tenth two-transistor connects ground GND, the 12 clock signal is in the time that clock input signal is the first level state, make drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected.
2. analog to digital converter according to claim 1, is characterized in that, transistor seconds, the 4th transistor, the tenth transistor, the 11 transistor and the tenth two-transistor are nmos pass transistor, and the 5th transistor and the 6th transistor are PMOS transistor.
3. analog to digital converter according to claim 2, is characterized in that, the first level state is supply voltage VDD, and second electrical level state is ground GND.
4. analog to digital converter according to claim 3, is characterized in that, also comprises:
The 13 transistor, its grid connects the 13 clock signal, and source electrode connects supply voltage VDD, and drain electrode connects the source electrode of the tenth two-transistor, and 13 clock signals and the 12 clock signal are same clock signal, the 13 transistor is PMOS transistor.
5. analog to digital converter according to claim 4, is characterized in that, also comprises:
The first electric capacity, its top crown connects the grid of transistor seconds, and bottom crown connects clock input signal;
The first transistor, its grid, drain electrode connect supply voltage VDD, and source electrode connects the grid of transistor seconds, and the first transistor is nmos pass transistor.
6. analog to digital converter according to claim 5, is characterized in that, also comprises:
The 9th transistor, its grid connects the 11 transistorized grid, and drain electrode connects the 4th transistor source, and source electrode connects the bottom crown of charge and discharge capacitance, and the 9th transistor is nmos pass transistor.
7. analog to digital converter according to claim 6, is characterized in that, also comprises:
The 3rd transistor, its grid connects the 3rd clock signal, source electrode connects supply voltage VDD, drain electrode connects the 6th transistor gate, the 3rd clock signal, in the time that clock input signal is the first level state, makes drain electrode and source electrode conducting, in the time that clock input signal is second electrical level state, the level signal that drain electrode and source electrode are disconnected, the 3rd transistor is PMOS transistor.
8. analog to digital converter according to claim 7, is characterized in that, also comprises:
The 7th transistor, its grid connects the 6th transistor drain, and drain electrode connects the 6th transistor gate, and source electrode connects sampled input signal Vin, and the 7th transistor is nmos pass transistor.
9. analog to digital converter according to claim 8, is characterized in that, also comprises:
The 8th transistor, its grid connects supply voltage VDD, and drain electrode connects the tenth two-transistor source electrode, and source electrode connects the 6th transistor drain, and the 8th transistor is nmos pass transistor.
10. an electronic equipment, is characterized in that, comprises the analog to digital converter as described in claim as arbitrary in claim 1 to 9 on body.
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| CN103825616B (en) * | 2014-01-15 | 2017-05-31 | 厦门优迅高速芯片有限公司 | A kind of clock feedthrough compensated circuit of bootstrapped clock sampling switch |
| CN104124968B (en) * | 2014-08-06 | 2017-12-29 | 西安电子科技大学 | A kind of clock duty cycle calibration circuit for flow-line modulus converter |
| CN107104663B (en) * | 2016-02-22 | 2023-09-15 | 成都锐成芯微科技股份有限公司 | Bootstrap circuit for channel selection switch |
| CN112671382B (en) * | 2020-12-16 | 2023-08-08 | 东南大学 | Grid voltage bootstrapping switch circuit |
| CN113225055B (en) * | 2021-04-21 | 2024-02-13 | 深圳市国微电子有限公司 | Charge injection cancellation circuit, analog switch circuit, and sampling device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101546998A (en) * | 2009-04-15 | 2009-09-30 | 东南大学 | High-precision sampling switch adopting grate source tracking technology |
| CN101783580A (en) * | 2009-12-24 | 2010-07-21 | 浙江大学 | High frequency switch circuit for inhibiting substrate bias effect in sampling hold circuit |
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| WO2002005053A2 (en) * | 2000-07-10 | 2002-01-17 | Koninklijke Philips Electronics N.V. | Circuit for providing a constant current |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101546998A (en) * | 2009-04-15 | 2009-09-30 | 东南大学 | High-precision sampling switch adopting grate source tracking technology |
| CN101783580A (en) * | 2009-12-24 | 2010-07-21 | 浙江大学 | High frequency switch circuit for inhibiting substrate bias effect in sampling hold circuit |
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