CN220325608U - Grid voltage bootstrapping switch circuit, sampling module and electronic device - Google Patents
Grid voltage bootstrapping switch circuit, sampling module and electronic device Download PDFInfo
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Abstract
The utility model relates to a gate voltage bootstrap switch circuit, a sampling module and an electronic device. The circuit comprises a charge pump, a sampling switch tube, a sampling capacitor and a feed-through elimination circuit, wherein the input end of the charge pump is respectively connected with a sampling clock signal, an external power signal and an input signal, the output end of the charge pump is commonly connected with the control end of the sampling switch tube and the control end of the feed-through elimination circuit, the input end of the sampling switch tube is connected with the input signal, the output end of the sampling switch tube is commonly connected with the input end of the feed-through elimination circuit and the first end of the sampling capacitor, and the second end of the sampling capacitor is grounded; according to the sampling switching tube, the feed-through eliminating circuit is arranged, the coupling voltage which is the same as the transmission error voltage caused by parasitic capacitance after the sampling switching tube enters the holding stage from the sampling stage and has opposite directions is generated, and the coupling voltage are mutually offset, so that the transmission error caused by the clock feed-through effect is avoided or reduced, and the linearity performance of the sampling switching tube is improved.
Description
Technical Field
The present disclosure relates to integrated circuit manufacturing technologies, and in particular, to a gate voltage bootstrap switch circuit, a sampling module, and an electronic device.
Background
The analog-to-digital converter ADC converts a continuous analog signal into a discrete digital signal, which is an important component of the micro control unit MCU. With the high-speed development of modern integrated circuit technology, higher requirements are placed on the speed, precision, power consumption and other performances of the ADC. The dynamic performance of the sampling circuit determines the performance of the ADC, and the grid voltage bootstrap switch is a current common sampling circuit structure due to the low on-resistance and good linearity.
The current gate voltage bootstrapped switch uses the input signal V in The charged capacitor is bootstrapped to start the sampling MOS switch tube, so that the on-resistance of the sampling MOS switch tube and an input signal V in Is irrelevant; however, in the actual working process, when the sampling MOS switch tube is used for switching, the grid electrode is connected with a clock signal, and when the source electrode and the drain electrode pass through the signal, the grid-source capacitor C is arranged GS And gate-drain capacitance C GD The clock signal may couple to the source and drain terminals to affect the signal, resulting in an input signal V in And transmission errors occur after the sampling MOS switch tube passes through the sampling MOS switch tube, so that the linearity performance of the sampling MOS switch tube is reduced.
In the above-mentioned existing gate voltage bootstrapping sampling switch circuit, the inventor finds that at least the following problems exist in the conventional technical scheme: in the actual sampling process, the transmission performance of the sampling MOS switch tube is affected by the clock feed-through effect, the source electrode end of the sampling MOS switch tube generates output voltage change to cause transmission errors, and the linearity performance of the sampling tube is reduced.
Disclosure of Invention
In view of the above, it is necessary to provide a gate voltage bootstrap switch circuit, a sampling module, and an electronic device capable of improving an output error due to a clock feedthrough effect and having high linearity performance, in order to solve the problems of the conventional gate voltage bootstrap switch circuit.
In a first aspect, the present application provides a gate voltage bootstrapped switch circuit, comprising:
the charge pump, sampling switch tube, sampling capacitor and feed-through eliminating circuit, the input end of the charge pump is respectively connected with sampling clock signal, external power supply signal VDD and input signal V in The output end of the charge pump is connected with the control end of the sampling switch tube and the control end of the feed-through elimination circuit, and the input end of the sampling switch tube is connected with the input signal V in The output end of the sampling switch tube is connected with the input end of the feed-through elimination circuit and the first end of the sampling capacitor, and the second end of the sampling capacitor is grounded;
the charge pump is configured to control on and off of the sampling switch tube according to the sampling clock signal; the feed-through cancellation circuit is configured to drive the sampling capacitive coupling to generate a coupling voltage that cancels out a transmission error voltage of the sampling switch tube; the transmission error voltage is the same as the coupling voltage in magnitude and opposite in direction.
Optionally, the charge pump includes a gate voltage control circuit, a first switch circuit, a second switch circuit, a bootstrap capacitor, and a capacitor charging circuit, one end of the bootstrap capacitor is connected to the gate voltage control circuit, the other end is connected to the capacitor charging circuit, and the bootstrap capacitor is configured to raise the voltage of the control end of the sampling switch tube to the external power supply signal VDD and the input signal V when the sampling switch tube is turned on in The capacitor charging circuit is also connected with an external power supply signal VDD and a first switch circuit, the capacitor charging circuit is configured to charge the bootstrap capacitor according to the voltage of the control end of the sampling switch tube, the first switch circuit is configured to connect or disconnect the charging channels of the bootstrap capacitor and the control end of the sampling switch tube according to the sampling clock signal, and the second switch circuit is respectively connected with the input signal V in The bootstrap capacitor is connected with the first switch circuit, and the second switch circuit is configured to turn on or off the input signal V according to the control end voltage of the sampling switch tube in And a charging channel of the bootstrap capacitor.
Optionally, the gate voltage control circuit includes a first switching tube, a second switching tube, a third switching tube, a fourth switching tube, a fifth switching tube, and the sampling clock signal includes a first clock signal CLKN and a second clock signal CLKP, a gate of the first switching tube is connected to the first clock signal CLKN, a gate of the second switching tube, a gate of the third switching tube is connected to the second clock signal CLKP, a source of the first switching tube is connected to a ground terminal, a source of the second switching tube is connected to the external power signal VDD, a drain of the first switching tube is commonly connected to a first terminal of the bootstrap capacitor, a drain of the third switching tube, a source of the fourth switching tube, and an output terminal of the second switching circuit, a drain of the second switching tube is commonly connected to a source of the third switching tube, a drain of the fourth switching tube, and a gate of the fifth switching tube, a drain of the fourth switching tube is commonly connected to a drain of the fourth switching tube, and a drain of the fifth switching tube is commonly connected to a drain of the bootstrap capacitor, and a drain of the sampling tube is commonly connected to the output terminal of the fifth switching tube; the first clock signal CLKN and the second clock signal CLKP are a pair of inverted clock control signals.
Optionally, the capacitor charging circuit includes a sixth switching tube, a drain electrode of the sixth switching tube is connected with the external power supply signal VDD, a source electrode of the sixth switching tube is commonly connected with the second end of the bootstrap capacitor and a source electrode of the fifth switching tube, and a gate electrode of the sixth switching tube is commonly connected with the output end of the first switching circuit and a control end of the sampling switching tube.
Optionally, the first switching circuit includes an eighth switching tube and a ninth switching tube, a source electrode of the ninth switching tube is connected with a ground end, a gate electrode of the ninth switching tube is connected with the first clock signal CLKN, a drain electrode of the ninth switching tube is connected with a source electrode of the eighth switching tube, a gate electrode of the eighth switching tube is connected with the external power signal VDD, and a drain electrode of the eighth switching tube is connected with a control end of the sampling switching tube.
Optionally, the second switching circuit includes a seventh switching tube, a gate of the seventh switching tube is connected to the control end of the sampling switching tube, and a drain of the seventh switching tube is connected to the first end of the sampling switching tube and the input signal V in And (5) joint connection.
Optionally, the feed-through cancellation circuit includes a tenth switch tube, an eleventh switch tube and a second capacitor, where a gate of the tenth switch tube and a gate of the eleventh switch tube are connected to form a control end of the feed-through cancellation circuit and are connected to a control end of the sampling switch tube, a source of the tenth switch tube is connected to the external power supply signal VDD, a drain of the eleventh switch tube is connected to a ground end, a drain of the tenth switch tube, a drain of the eleventh switch tube and a first end of the second capacitor are connected together, and a second end of the second capacitor is connected together with a first end of the sampling capacitor and a second end of the sampling switch tube.
Optionally, the second capacitor is an N-type MOS capacitor.
Optionally, the sampling switch tube is an N-type MOS tube.
In a second aspect, the present application provides a sampling module, including the gate voltage bootstrap switching circuit described above.
In a third aspect, the present application provides an electronic device, including the sampling module described above.
One of the above technical solutions has the following advantages and beneficial effects:
the gate voltage bootstrap switch circuit of the utility model comprises a charge pump, a sampling switch tube, a sampling capacitor and a feed-through elimination circuit, wherein the input end of the charge pump is respectively connected with a sampling clock signal, an external power supply signal VDD and an input signal V in The output end of the charge pump is connected with the control end of the sampling switch tube and the control end of the feed-through eliminating circuit, and the input end of the sampling switch tube is connected with the input signal V in The output end of the sampling switch tube is connected with the input end of the feed-through eliminating circuit and the first end of the sampling capacitor, and the second end of the sampling capacitor is grounded; the charge pump is configured to control the on and off of the sampling switch tube according to the sampling clock signal; the feed-through cancellation circuit is configured to drive the sampling capacitive coupling to generate a coupling voltage that cancels out the transmission error voltage of the sampling switch tube; the transmission error voltage is the same as the coupling voltage in the opposite direction. According to the grid voltage bootstrap switch circuit, the feed-through elimination circuit is arranged, so that a coupling voltage which is the same as the transmission error voltage caused by parasitic capacitance after the sampling switch tube enters the holding stage from the sampling stage and opposite in direction is generated, and the coupling voltage cancel each other, and therefore the transmission error caused by a clock feed-through effect is avoided or reduced, and the linearity performance of the sampling switch tube is improved.
Drawings
FIG. 1 is a schematic diagram of a conventional gate voltage bootstrapped switch circuit;
FIG. 2 is a schematic diagram of a conventional gate voltage bootstrapped switch circuit with non-ideal effects;
FIG. 3 is a schematic diagram of a gate voltage bootstrapped switch circuit in one embodiment;
FIG. 4 is a schematic diagram of a charge pump in one embodiment;
fig. 5 is a schematic diagram of a gate voltage bootstrapped switch circuit in one embodiment.
Reference numerals:
10. a charge pump; 11. a gate voltage control circuit; 12. a first switching circuit; 13. a second switching circuit; 14. a capacitor charging circuit; 20. a feed-through cancellation circuit;
M S a sampling switch tube; c (C) H A sampling capacitor; c (C) 1 A bootstrap capacitor; c (C) 2 A second capacitor; VDD, an external power supply signal; CLKN, a first clock signal; CLKP, a second clock signal;
m1, a first switching tube; m2, a second switching tube; m3, a third switching tube; m4, a fourth switching tube; m5, a fifth switching tube; m6, a sixth switching tube; m7, a seventh switching tube; m8, an eighth switching tube; m9, a ninth switching tube; m10, a tenth switching tube; m11, eleventh switching tube.
Detailed Description
In order to make the present application solution better understood by those skilled in the art, the following description will be made in detail and with reference to the accompanying drawings in the embodiments of the present application, it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the present application described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In addition, the term "plurality" shall mean two as well as more than two.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As shown in FIG. 1, the conventional gate bootstrap switch circuit has a pair of inverted clock control signals including a first clock signal CLKN and a second clock signal CLKP, and when CLKN is high, CLKP is low, the sampling switch is in hold stage, and the switches S1 and S4 are closed to bootstrap capacitor C 1 The voltage difference between the upper polar plate and the lower polar plate is VDD, at this time, the switch S3 is closed, and the switch tube M is sampled S The gate electrode is grounded and the gate electrode is connected to ground,sampling switch tube M S Is in an off state; when CLKP is high and CLKN is low, the sampling switch is in sampling stage, switch S5 is closed, and signal V is input in Through the switch S5 and the capacitor C 1 The lower electrode plate is connected, and the upper electrode plate of the capacitor C1 is bootstrapped to VDD+V due to conservation of charge in And through switch S2 and sampling tube M S Is connected with the grid electrode of the sampling tube M S Turn on and operate in the linear region to input signal V in Transferred to sampling capacitor C H . When sampling tube M S When turned on, the gate-source voltage V GS The method comprises the following steps:
V GS ＝VDD+V in -V in ＝VDD
at this time, sampling tube M S On-resistance R of (2) on The secondary effects are not considered and can be expressed as:
from the above, it can be seen that the sampling tube M S On-resistance R of (2) on Is a sum input signal V in An irrelevant constant ensures that the sampling switch has good linearity and is connected with the capacitor C through the bootstrap capacitor 1 Sampling tube M S To raise the gate-source voltage to VDD to make the sampling tube M S With a small on-resistance R on 。
In practice, the transmission performance of the gate voltage bootstrap switch circuit is affected by the clock feedthrough effect, and when the gate voltage bootstrap switch enters the hold phase from the sampling phase, the gate voltage of the sampling tube MS is from vdd+v in Jump to zero, the voltage change will pass through the sampling tube M S Gate-source parasitic capacitance C of (2) GS Parasitic capacitance C of gate and drain GD Coupled to the sampling tube M S Is input with a signal V by a voltage change coupled to the drain in Absorb without producing a pair of collecting pipes M S The resulting change in output voltage coupled to the source terminal can be expressed as:
from the above, it can be seen that the clock feedthrough effect introduces a transmission error to the sampling switch, and that such error follows the input signal V in The increase in amplitude increases non-linearly, which reduces the linearity performance of the sampling switch.
Meanwhile, the on-resistance of the gate voltage bootstrap sampling switch is ideally a constant independent of the input voltage, as shown in FIG. 2, due to the NMOS sampling tube M S Is grounded under the influence of body effect, and has a threshold voltage V thn Is no longer a constant and contains V affected by body effect thn Can be expressed as:
from the above, it can be seen that the actual V thn Is expressed as a sum V in Related functions, i.e. sampling tubes M S The on-resistance of (a) will follow the input signal V in Is changed by a change in (a).
In order to solve the problems of the existing motor control method, in one embodiment, as shown in fig. 3, a gate voltage bootstrap switch circuit is provided, which comprises a charge pump 10 and a sampling switch tube M S Sampling capacitor C H And a feed-through cancellation circuit 20, the input terminal of the charge pump 10 is connected with the sampling clock signal, the external power supply signal VDD and the input signal V respectively in Is connected with the output end of the charge pump 10 and the sampling switch tube M S Is commonly connected with the control terminal of the feed-through cancellation circuit 20, and is provided with a sampling switch tube M S Input terminal of (2) and input signal V in Connected with sampling switch tube M S And the input of feed-through cancellation circuit 20 and sampling capacitor C H Is connected with the first end of the sampling capacitor C H Is grounded; wherein the charge pump 10 is configured to control the sampling switch tube M according to the sampling clock signal S Is turned on and off; the feed-through cancellation circuit 20 is configured to drive the sampling capacitance C H Coupling generating and sampling switch tubeM S A coupling voltage that cancels out the transmission error voltage of the first power supply; the transmission error voltage is the same as the coupling voltage in the opposite direction.
In the above embodiment, by providing the feed-through cancellation circuit 20, one and sampling switch tube M is generated S Coupling voltages with the same magnitude and opposite directions of transmission error voltages caused by parasitic capacitance are adopted after the sampling phase enters the holding phase, and the coupling voltages are mutually offset, so that the transmission error caused by clock feed-through effect is avoided or reduced, and the sampling switch tube M is improved S Is a linear property of the (c).
In one embodiment, as shown in FIG. 4, the charge pump 10 includes a gate voltage control circuit 11, a first switch circuit 12, a second switch circuit 13, and a bootstrap capacitor C 1 And a capacitor charging circuit 14 for bootstrap capacitor C 1 One end of the capacitor is connected with the grid voltage control circuit 11, the other end is connected with the capacitor charging circuit 14, and the capacitor C is bootstrapped 1 Configured as a sampling switch tube M S When conducting, the sampling switch tube M S The control terminal voltage of (2) is raised to the external power supply signal VDD and the input signal V in The capacitor charging circuit 14 is also connected with the external power supply signal VDD and the first switch circuit 12, and the capacitor charging circuit 14 is configured according to the sampling switch tube M S The control terminal voltage of (2) vs. bootstrap capacitor C 1 The first switch circuit 12 is configured to switch on or off the bootstrap capacitor C1 and the sampling switch tube M according to the sampling clock signal S The charging channel of the control end, the second switch circuit 13 and the input signal V respectively in The bootstrap capacitor C1 and the first switching circuit 12 are connected, and the second switching circuit 13 is configured to switch the tube M according to the sampling S The voltage of the control terminal of (2) turns on or off the input signal V in And bootstrap capacitor C 1 Is provided.
In one embodiment, as shown in FIG. 5, the gate voltage control circuit 11 includes a first switch tube M1, a second switch tube M2, a third switch tube M3, a fourth switch tube M4, a fifth switch tube M5, and a sampling clock signal including a first clock signal CLKN and a second clock signal CLKP, wherein the gate of the first switch tube M1 is connected with the first clock signal CLKN, and the gates of the second switch tube M2 and the third switch tube M3The source of the first switch tube M1 is connected with the grounding end, the source of the second switch tube M2 is connected with the external power supply signal VDD, the drain of the first switch tube M1 is connected with the bootstrap capacitor C 1 The drain of the second switch tube M2 is commonly connected with the source of the third switch tube M3, the drain of the fourth switch tube M4 and the grid of the fifth switch tube M5, the grid of the fourth switch tube M4 is commonly connected with the sampling switch tube M S The control end of the fifth switch tube M5 is connected with the drain of the fifth switch tube M5, and the source of the fifth switch tube M5 is connected with the bootstrap capacitor C 1 The second end of the capacitor charging circuit 14 is commonly connected with the output end of the capacitor charging circuit; the first clock signal CLKN and the second clock signal CLKP are a pair of inverted clock control signals.
The first switching tube M1, the third switching tube M3 and the fourth switching tube M4 are N-type MOS tubes, and the second switching tube M2 and the fifth switching tube M5 are P-type MOS tubes.
Specifically, when the first clock signal CLKN is at a high level and the second clock signal CLKP is at a low level, the switching transistor M is sampled S In the holding phase, the first switching tube M1 is conducted to lead the bootstrap capacitor C 1 The first switching circuit 12 causes the sampling switch tube M to have a first terminal voltage of zero S The voltage between the control terminal and the ground terminal is zero, so that the capacitor charging circuit 14 is turned on to enable the external power supply signal VDD to bootstrap capacitor C 1 Charging and bootstrap capacitor C 1 The voltage difference is an external power supply signal VDD, the second switching tube M2 is conducted to enable the fifth switching tube M5 to keep an off state, meanwhile, the third switching tube M3 and the fourth switching tube M4 are also in an off state to block the bootstrap capacitor C 1 And conducting channels at two ends and the grid electrode of the sampling switch tube. When the first clock signal CLKN is low and the second clock signal CLKP is high, the switch tube M is sampled S In the sampling stage, the second switching tube M2 is turned off, the third switching tube M3 is turned on, so that the fifth switching tube M5 is turned on, the conduction condition of the second switching tube M2 is met, and the signal V is input in To the bootstrap capacitor C via the second switching circuit 13 1 Thereby bootstrapping the capacitor C 1 Is a second terminal voltage of (2)Raised to the external power supply signal VDD and the input signal V in The sum is conducted through a fifth switching tube M5 to lead the sampling switching tube M S The control terminal voltage of (2) is set as the external power supply signal VDD and the input signal V in The sum of the sampling switch tubes is conducted to finish the input signal V in Is a sample of the sample.
In one embodiment, as shown in fig. 5, the capacitor charging circuit 14 includes a sixth switching tube M6, the drain of the sixth switching tube M6 is connected to the external power signal VDD, and the source of the sixth switching tube M6 is connected to the bootstrap capacitor C 1 The second end of the fifth switch tube M5 is connected with the source electrode of the fifth switch tube M5, the grid electrode of the sixth switch tube M6 is connected with the output end of the first switch circuit 12 and the sampling switch tube M S Is commonly connected with the control end of the control circuit.
The sixth switching tube M6 is a P-type MOS tube.
Specifically, when the first clock signal CLKN is at a high level and the second clock signal CLKP is at a low level, the first switching tube M1 is turned on to bootstrap capacitor C 1 The first end voltage of (2) is zero, the first switch circuit 12 is turned on to drive the sixth switch tube M6 to be turned on, the external power supply signal VDD is connected with the bootstrap capacitor C through the sixth switch tube M6 1 A charging channel is formed at the second end of the capacitor to further enable the bootstrap capacitor C 1 The voltage difference between the two ends is the external power supply signal VDD, thus realizing the bootstrap capacitor C 1 Is provided.
In one embodiment, as shown in FIG. 5, the first switching circuit 12 comprises an eighth switching tube M8 and a ninth switching tube M9, the source electrode of the ninth switching tube M9 is connected with the ground terminal, the gate electrode of the ninth switching tube M9 is connected with the first clock signal CLKN, the drain electrode of the ninth switching tube M9 is connected with the source electrode of the eighth switching tube M8, the gate electrode of the eighth switching tube M8 is connected with the external power signal VDD, and the drain electrode of the eighth switching tube M8 is connected with the sampling switching tube M S Is connected with the control end of the control circuit.
The eighth switching tube M8 and the ninth switching tube M9 are N-type MOS tubes.
Specifically, when the first clock signal CLKN is at a high level and the second clock signal CLKP is at a low level, the eighth switching transistor M8 and the ninth switching transistor M9 are in a conductive state and the output voltage of the eighth switching transistor M8 is zero, so that the sixth switchSwitch tube M6 is conducted to bootstrap capacitor C 1 Charging is carried out, and meanwhile, the fifth switching tube M5 and the second switching circuit 13 are kept to be turned off, so that the bootstrap capacitor C is turned off 1 And the voltage at two ends and the channel at the control end of the sampling switch tube.
In one embodiment, as shown in FIG. 5, the second switching circuit 13 includes a seventh switching tube M7, and a gate of the seventh switching tube M7 and a sampling switching tube M S The drain electrode of the seventh switching tube M7 is connected with the sampling switching tube M S Is input with signal V in And (5) joint connection.
The seventh switching tube M7 is an N-type MOS tube.
Specifically, when the first clock signal CLKN is at low level and the second clock signal CLKP is at high level, the switching transistor M is sampled S In the sampling stage, the second switching tube M2 is turned off and the third switching tube M3 is turned on to turn on the fifth switching tube M5, the gate voltage of the seventh switching tube M7 is raised and meets the conduction condition, and the signal V is input in Transmitted to the bootstrap capacitor C through the seventh switching tube M7 1 Thereby bootstrapping the capacitor C 1 The second terminal voltage of (2) rises to the external power supply signal VDD and the input signal V in Sum, bootstrap capacitance C 1 The gate voltage of the sampling switch tube is set to be an external power supply signal VDD and an input signal V through a fifth switch tube M5 in The sum of the two power supply signals is that the voltage difference between the control end and the first end of the sampling switch tube is the external power supply signal VDD, so that the sampling switch tube is conducted to finish the input signal V in Is a sample of the sample.
In one embodiment, as shown in FIG. 5, the feed-through cancellation circuit 20 includes a tenth switching tube M10, an eleventh switching tube M11, and a second capacitance C 2 The gate of the tenth switch tube M10 and the gate of the eleventh switch tube M11 are connected to form a control end of the feed-through eliminating circuit 20 and are connected with the sampling switch tube M S The source of the tenth switch tube M10 is connected with the external power supply signal VDD, the drain of the eleventh switch tube M11 is connected with the ground, the drain of the tenth switch tube M10, the drain of the eleventh switch tube M11 and the second capacitor C 2 Is connected together with the first end of the second electricCapacitor C 2 And a sampling capacitor C H Is a first end of a sampling switch tube M S Is commonly connected with the second end of the first connecting piece.
Wherein the tenth switching tube M10 is a P-type MOS tube, the eleventh switching tube M11 is an N-type MOS tube, and the second capacitor C 2 Is an N-type MOS capacitor.
Specifically, the gates of the tenth switching tube M10 and the eleventh switching tube M11 are connected with the control end of the sampling switching tube, and in the sampling stage, the eleventh switching tube M11 is turned on, and the second capacitor C 2 When the sampling switch tube enters the holding stage from the sampling stage, the tenth switch tube M10 is turned on, the second capacitor C 2 Is set to the external power supply signal VDD, the voltage change is transmitted through the second capacitor C 2 Coupled to sampling capacitance C H In this way, the output voltage is caused to change in the forward direction, and the voltage change at the output terminal can be expressed as:
selecting a second capacitor C with proper size 2 Order-making
|ΔV out1 |＝|ΔV out |
By adding the feedthrough cancellation circuit 20, the output error introduced by the clock feedthrough can be theoretically cancelled. Simultaneously the substrate of the sampling switch tube and the bootstrap capacitor C 1 Is connected together, and when in the sampling phase, the substrate voltage of the sampling switch tube is approximately equal to the input signal V in The threshold voltage of the sampling switch tube is approximately a constant, and the influence of the body effect is eliminated.
In one embodiment, as shown in FIG. 5, a second capacitance C 2 Is an N-type MOS capacitor.
It should be noted that the MOS capacitor can be divided into three layers, an upper layer is a gate electrode made of metal, a lower layer is a base made of semiconductor, and a middle layer is filled with oxide, typically SiO 2 . The MOS capacitor has only two ports of a leading-out gate electrode and a base electrode, and the second capacitor C in the application 2 Is NThe first end of the MOS tube is a gate electrode, and the second end of the MOS tube is a base electrode.
In one embodiment, as shown in FIG. 5, a switching tube M is sampled S Is an NMOS tube.
Wherein, sampling switch tube M S The control terminal of (a) is a grid, the first terminal is a source electrode, and the second terminal is a drain electrode. When the first clock signal CLKN is at low level and the second clock signal CLKP is at high level, the second switching tube M2 is turned off and the third switching tube M3 is turned on, so that the fifth switching tube M5 is turned on to bootstrap the capacitor C 1 The second end of the (B) is communicated with the grid electrode of the sampling switch tube MS through a fifth switch tube M5, a seventh switch tube M7 is conducted, and a signal V is input in Is connected with the first end of the bootstrap capacitor C1 through a seventh switching tube M7 and the bootstrap capacitor C 1 The voltage of the second terminal of (2) rises to the input signal V in Sum with the external power supply signal VDD to further sample the switching tube M S Is set as the input signal V in And the sum of the external power supply signal VDD, and the source of the sampling switch tube and the input signal V in Connected, thus sampling switch tube M S The voltage difference between the gate and the source of the transistor is the external power supply signal VDD, and the switch tube M is sampled at this time S Conducting to finish inputting signal V in Is a collection of (1).
In one embodiment, a sampling module is provided, including the gate voltage bootstrap switch circuit described above.
In one embodiment, an electronic device is provided, including the sampling module described above.
Because the sampling module and the electronic device both adopt the grid voltage bootstrap switch circuit, transmission errors caused by clock feed-through effect can be avoided or reduced, and linearity performance is improved.
In summary, the utility model provides a gate voltage bootstrap switch circuit, a sampling module and an electronic device, which are suitable for various applications of high-precision and high-speed sampling.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples represent only a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present application, which are all within the scope of the present utility model. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. A gate voltage bootstrapped switch circuit, comprising:
charge pump (10), sampling switch tube (M) S ) Sampling capacitor (C) H ) And a feed-through cancellation circuit (20) having an input terminal connected to the sampling clock signal, the external power supply signal VDD and the input signal V, respectively, of the charge pump (10) in Is connected with the output end of the charge pump (10) and the sampling switch tube (M) S ) And the control end of the feed-through cancellation circuit (20), the sampling switch tube (M S ) Is connected with the input end of the input signal V in Is connected with the sampling switch tube (M S ) And the input of the feed-through cancellation circuit (20) and the sampling capacitance (C H ) Is connected to the first terminal of the sampling capacitor (C H ) Is grounded;
wherein the charge pump (10) is configured to control the sampling switch tube (M) according to the sampling clock signal S ) Is turned on and off; the feed-through cancellation circuit (20) is configured to drive the sampling capacitance (C H ) Coupling generation is connected with the sampling switch tube (M S ) A coupling voltage that cancels out the transmission error voltage of the first power supply; the transmission error voltage is the same as the coupling voltage in magnitude and opposite in direction.
2. The gate voltage bootstrapped switch circuit of claim 1, wherein the charge pump (10) includes a gate voltage control circuit (11), a firstA switching circuit (12), a second switching circuit (13), a bootstrap capacitor (C 1 ) And a capacitor charging circuit (14), the bootstrap capacitor (C 1 ) Is connected to the gate voltage control circuit (11) at one end and to the capacitor charging circuit (14) at the other end, the bootstrap capacitor (C 1 ) Is configured as the sampling switch tube (M S ) When conducting, the sampling switch tube (M S ) The control terminal voltage of the voltage regulator is raised to the external power supply signal VDD and the input signal V in And the capacitor charging circuit (14) is also connected with an external power supply signal VDD and the first switching circuit (12), the capacitor charging circuit (14) being configured to switch the switching circuit (M) according to the sampling S ) To the bootstrap capacitance (C 1 ) Charging is performed, the first switching circuit (12) is configured to switch on or off the bootstrap capacitor (C 1 ) And the sampling switch tube (M S ) A charging channel at the control end, the second switch circuit (13) is respectively connected with the input signal V in Said bootstrap capacitor (C 1 ) And the first switching circuit (12) is connected, the second switching circuit (13) being configured to switch the transistor (M) according to the sampling S ) The control terminal voltage of (2) turns on or off the input signal V in Is connected with the bootstrap capacitor (C 1 ) Is provided.
3. The gate voltage bootstrapping switch circuit according to claim 2, wherein the gate voltage control circuit (11) comprises a first switch tube (M1), a second switch tube (M2), a third switch tube (M3), a fourth switch tube (M4), a fifth switch tube (M5), the sampling clock signal comprising a first clock signal CLKN and a second clock signal CLKP, a gate of the first switch tube (M1) being connected to the first clock signal CLKN, a gate of the second switch tube (M2), the third switch tube (M3) being connected to the second clock signal CLKP, a source of the first switch tube (M1) being connected to a ground terminal, a source of the second switch tube (M2) being connected to the external power supply signal VDD, a drain of the first switch tube (M1) being connected to the bootstrap capacitor (C) 1 ) A drain of the third switching tube (M3), a first end ofThe source electrode of the fourth switching tube (M4) and the output end of the second switching circuit (13) are connected together, the drain electrode of the second switching tube (M2) is connected together with the source electrode of the third switching tube (M3), the drain electrode of the fourth switching tube (M4) and the grid electrode of the fifth switching tube (M5), the grid electrode of the fourth switching tube (M4) is connected together with the control end of the sampling switching tube (MS) and the drain electrode of the fifth switching tube (M5), and the source electrode of the fifth switching tube (M5) is connected together with the bootstrap capacitor (C) 1 ) The second end of the capacitor charging circuit (14) is commonly connected with the output end of the capacitor charging circuit;
the first clock signal CLKN and the second clock signal CLKP are a pair of inverted clock control signals.
4. A gate voltage bootstrapped switch circuit as in claim 3, wherein the capacitor charging circuit (14) comprises a sixth switch tube (M6), a drain of the sixth switch tube (M6) being connected to the external power supply signal VDD, a source of the sixth switch tube (M6) being connected to the bootstrap capacitor (C 1 ) The second end of the fifth switching tube (M5) is connected with the source electrode of the fifth switching tube (M5), the grid electrode of the sixth switching tube (M6) is connected with the output end of the first switching circuit (12) and the sampling switching tube (M) S ) Is commonly connected with the control end of the control circuit.
5. The gate voltage bootstrapped switch circuit of claim 4, wherein the first switch circuit (12) includes an eighth switch tube (M8) and a ninth switch tube (M9), a source of the ninth switch tube (M9) is connected to a ground, a gate of the ninth switch tube (M9) is connected to the first clock signal CLKN, a drain of the ninth switch tube (M9) is connected to a source of the eighth switch tube (M8), a gate of the eighth switch tube (M8) is connected to the external power signal VDD, and a drain of the eighth switch tube (M8) is connected to the sampling switch tube (M) S ) Is connected with the control end of the control circuit.
6. The gate voltage bootstrapped switch circuit as in claim 5, wherein the second switch circuit (13) includes a seventh switch tube (M7), a gate of the seventh switch tube (M7) being connected toThe sampling switch tube (M) S ) Is connected with the drain electrode of the seventh switching tube (M7) and the sampling switching tube (M S ) Is the first end of the input signal V in And (5) joint connection.
7. The gate voltage bootstrapped switch circuit according to any one of claims 1 to 6, wherein the feed-through cancellation circuit (20) comprises a tenth switch tube (M10), an eleventh switch tube (M11), and a second capacitor (C 2 ) The grid of the tenth switching tube (M10) and the grid of the eleventh switching tube (M11) are connected to form a control end of the feed-through eliminating circuit (20) and are connected with the sampling switching tube (M) S ) The source of the tenth switch tube (M10) is connected with the external power supply signal VDD, the drain of the eleventh switch tube (M11) is connected with the grounding end, the drain of the tenth switch tube (M10), the drain of the eleventh switch tube (M11) and the second capacitor (C 2 ) Is connected to the first end of the second capacitor (C 2 ) And the second end of the sampling capacitor (C H ) Is connected to the first end of the sampling switch tube (M S ) Is commonly connected with the second end of the first connecting piece.
8. The gate voltage bootstrapped switch circuit of claim 7, wherein the second capacitor (C 2 ) Is an N-type MOS capacitor; and/or
The sampling switch tube (M) S ) Is an NMOS tube.
9. A sampling module comprising a gate voltage bootstrapped switch circuit as claimed in any one of claims 1 to 8.
10. An electronic device comprising the sampling module of claim 9.
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| CN202321851828.9U CN220325608U (en) | 2023-07-14 | 2023-07-14 | Grid voltage bootstrapping switch circuit, sampling module and electronic device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321851828.9U CN220325608U (en) | 2023-07-14 | 2023-07-14 | Grid voltage bootstrapping switch circuit, sampling module and electronic device |
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