CN108777579B - Grid voltage bootstrapping switch - Google Patents
Grid voltage bootstrapping switch Download PDFInfo
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- CN108777579B CN108777579B CN201811042575.4A CN201811042575A CN108777579B CN 108777579 B CN108777579 B CN 108777579B CN 201811042575 A CN201811042575 A CN 201811042575A CN 108777579 B CN108777579 B CN 108777579B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
- H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/0614—Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses a gate voltage bootstrap switch, which relates to the technical field of analog circuits and comprises a first capacitor and a plurality of MOS (metal oxide semiconductor) tubes, wherein each MOS tube comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS tube, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a bootstrap switch and a substrate switch, and the substrate switch is connected with the bootstrap switch. According to the invention, the substrate switch, namely the seventh NMOS tube and the eighth NMOS tube, is connected to the bootstrap switch, so that the grid potential of the bootstrap switch is consistent with the substrate potential during sampling, the second-order effect intermediate effect of the MOS tube can be reduced, the harmonic distortion is reduced, the linearity of the sampling switch SW is ensured, the precision of a sampling switch circuit is improved, and the influence of the switch linearity on the ADC precision is greatly reduced.
Description
Technical Field
The invention relates to the technical field of analog circuits, in particular to a gate voltage bootstrap switch.
Background
With the progress of integrated circuit technology and the rapid growth of communication and multimedia markets, digital signal processing technology has also been rapidly developed and widely used in various fields. Digital signals have the comprehensive advantages of strong anti-interference capability, easy integration, low power consumption and low cost, so that more and more analog signal processing is gradually replaced by digital signal technology. However, in nature, optical, thermal, acoustic, electrical, magnetic, etc. signals are analog, so that in order for these analog signals to be processed by a digital system, these analog signals that are continuous in time need to be converted into discrete digital signals, and an analog-to-digital converter (Analog to Digital Converter, ADC) is a module that performs this function. As a key interface to analog and digital circuits, ADC is critical to the performance of the overall mixed signal system. In the SAR ADC, sampling and holding of the ADC on an input signal are realized by controlling the on and off of a switch, non-ideal factors exist in the switch, added error, direct current offset and nonlinear error can be introduced, the precision and speed of a sampling circuit are influenced, and the precision of the sampling circuit is directly influenced by the reduction of the sampling precision, so that in the design process of the SAR ADC, the sampling switch with smaller influence on the precision of the sampling circuit is selected, and the design requirement of an SAR ADC system is met.
The structure of a traditional grid voltage bootstrapping switch circuit is shown in fig. 1, and the traditional grid voltage bootstrapping switch circuit is composed of a sampling switch SW and a grid voltage bootstrapping circuit, wherein the grid voltage bootstrapping switch comprises a capacitor C1 and MOS tubes M1-M9, and the working principle is as follows:
(1) When the circuit is in the sampling stage, CLK is high, M2 is on, the gate of M5 is grounded, thus M5 is on, the gate voltages of M6 and SW are raised, M3 and M4 are off, M9 is on, the sampling switch SW is closed, C1 is connected to the gate source of SW, the gate of SW is raised to VDD+vin, and the gate source voltage of SW is VDD due to the unchanged total charge stored in C1.
(2) When the circuit is in the hold phase, CLK is low level, M1, M3 and M4 are on, M5 gate is connected to VDD, M5 is off, M9 is off, sampling switch SW is off, capacitor C1 is charged to VDD through M3 and M4, and the charge of C1 x VDD is stored in capacitor C1. The capacitor C1 is separated from the sampling switch SW, and the drain and source of SW are grounded through M3, M7, and M8, respectively, thereby discharging.
The on-resistance of the sampling switch is
Wherein mu n For carrier mobility, C ox The unit area gate capacitance of the sampling switch tube is W/L is the sampling switch width-to-length ratio, V GS To sample the gate-source voltage of the switch, V TH0 For switching on threshold voltage of switch tube, V SB For the switching tube source lining potential difference, γ is the body effect coefficient.
By utilizing the grid voltage bootstrap switch circuit, the voltage V of the switch Guan Shanyuan is improved GS Nonlinear distortion due to variation but ignores V due to body effect TH0 Is a linear problem due to the variation of (a).
Disclosure of Invention
It is therefore an object of the present invention to provide a gate voltage bootstrap switch that reduces the body effect by connecting the substrate switch at the gate of the sampling switch.
The invention solves the technical problems by the following technical means: the grid voltage bootstrap switch comprises a first capacitor and a plurality of MOS (metal oxide semiconductor) tubes, wherein each MOS tube comprises a first PMOS tube, a first NMOS tube, a second PMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a bootstrap switch and a substrate switch, the sources of the first PMOS tube and the second PMOS tube are both connected with a working voltage VDD, the drain of the first PMOS tube is connected with the drain of the first NMOS tube, the grid electrodes of the first PMOS tube and the first NMOS tube are both connected with a first clock signal CLK, the source of the first NMOS tube is connected with the drain of the second NMOS tube, the grid electrode of the second NMOS tube is connected with a second clock signal CLK-, the second clock signal CLK-is an inverted signal of the first clock signal CLK, and the source of the second NMOS tube is grounded;
the drain electrode of the second PMOS tube is connected with the upper polar plate of the first capacitor, the lower polar plate of the first capacitor is connected with the source electrode of the first NMOS tube, the grid electrode of the second PMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the fourth NMOS tube is connected with the working voltage VDD, the source electrode of the fourth NMOS tube is connected with the drain electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is grounded, and the grid electrode of the fifth NMOS tube is connected with the second clock signal CLK-;
the drain electrode of the second PMOS tube is also connected with the source electrode of the third PMOS tube, the drain electrode of the third PMOS tube is connected with the drain electrode of the fourth NMOS tube, the grid electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube, and the grid electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube;
the source electrode of the third NMOS tube is connected with the source electrode of the first NMOS tube, and the grid electrode of the third NMOS tube is connected with the grid electrode of the sixth NMOS tube;
the grid electrode of the sixth NMOS tube is also connected with the drain electrode of the fourth NMOS tube, the source electrode of the sixth NMOS tube is connected with the source electrode of the third NMOS tube, and the drain electrode of the sixth NMOS tube is connected with the source electrode of the bootstrap switch;
the source electrode of the bootstrap switch is connected with the input voltage Vin, the drain electrode of the bootstrap switch is connected with the power supply output VOUT, and the grid electrode of the bootstrap switch is connected with the grid electrode of the sixth NMOS tube;
the substrate switch comprises a seventh NMOS tube and an eighth NMOS tube, the gate of the bootstrap switch is connected with the gate of the eighth NMOS tube, the substrate of the bootstrap switch is connected with the source of the eighth NMOS tube, the drain of the eighth NMOS tube is connected with the source of the bootstrap switch, and the source of the eighth NMOS tube is connected with the drain of the seventh NMOS tube;
the grid electrode of the seventh NMOS tube is connected with a second clock signal CLK-, and the source electrode of the seventh NMOS tube is grounded.
The working process of the invention is as follows:
1) When the first clock signal CLK is at a high level, the CMOS gate voltage bootstrap switch circuit is in a sampling stage, the first NMOS tube is turned on, the gate of the third PMOS tube is grounded, so that the third PMOS tube is turned on, the gate voltages of the third NMOS tube, the sixth NMOS tube, the eighth NMOS tube and the bootstrap switch are raised, the second NMOS tube and the second PMOS tube are turned off, the sixth NMOS tube is turned on, the sampling switch is turned on, the eighth NMOS tube is turned on, the first capacitor is connected to the gate source of the bootstrap switch, and since the total charge stored in the first capacitor is unchanged, the gate voltage of the bootstrap switch is raised to vdd+vin, and the gate source voltage of the bootstrap switch is VDD.
2) When the first clock signal CLK is at a low level, the CMOS gate voltage bootstrap switch circuit is in a holding stage, the first PMOS tube, the second NMOS tube and the second PMOS tube are conducted, the grid electrode of the third PMOS tube is cut off, the sixth NMOS tube is cut off, the sampling switch is disconnected, the first capacitor is charged to the working voltage VDD through the second NMOS tube and the second PMOS tube, the capacitance value of the first capacitor is F, the electric quantity of F-shaped VDD is stored in the first capacitor, and because the third PMOS tube is cut off, the first capacitor is separated from the sampling switch, and the source electrode of the sampling switch is grounded through the second NMOS tube and the grid electrode of the sampling switch is grounded through the fourth NMOS tube and the fifth NMOS tube, so that the electric quantity is discharged.
The invention has the beneficial effects that: according to the invention, the substrate switch, namely the seventh NMOS tube and the eighth NMOS tube, is connected to the bootstrap switch, so that the grid potential of the bootstrap switch is consistent with the substrate potential during sampling, the second-order effect intermediate effect of the MOS tube can be reduced, the harmonic distortion is reduced, the linearity of the sampling switch SW is ensured, the precision of a sampling switch circuit is improved, and the influence of the switch linearity on the ADC precision is greatly reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional gate voltage bootstrapped switch circuit;
FIG. 2 is a diagram of a gate voltage bootstrapped switch according to an embodiment of the present invention;
fig. 3 is a waveform diagram of clock signals and input/output signals in the gate voltage bootstrap switch according to an embodiment of the present invention.
Detailed Description
The invention will be described in detail below with reference to the attached drawings and specific examples:
as shown in fig. 2-3, the gate voltage bootstrap switch comprises a first capacitor C1 and a plurality of MOS transistors, the MOS transistors comprise a first PMOS transistor M1, a first NMOS transistor M2, a second NMOS transistor M3, a second PMOS transistor M4, a third PMOS transistor M5, a third NMOS transistor M6, a fourth NMOS transistor M7, a fifth NMOS transistor M8, a sixth NMOS transistor M9, a bootstrap switch SW and a substrate switch, sources of the first PMOS transistor M1 and the second PMOS transistor M4 are all connected with an operating voltage VDD, a drain of the first PMOS transistor M1 is connected with a drain of the first NMOS transistor M2, gates of the first PMOS transistor M1 and the first NMOS transistor M2 are all connected with a first clock signal CLK, a source of the first NMOS transistor M2 is connected with a drain of the second NMOS transistor M3, a gate of the second NMOS transistor M3 is connected with a second clock signal CLK-, the second clock signal CLK-is an inverted signal of the first clock signal CLK, and a source of the second NMOS transistor M3 is grounded;
the drain electrode of the second PMOS tube M4 is connected with the upper polar plate of the first capacitor C1, the lower polar plate of the first capacitor C1 is connected with the source electrode of the first NMOS tube M2, the grid electrode of the second PMOS tube M4 is connected with the drain electrode of the fourth NMOS tube M7, the grid electrode of the fourth NMOS tube M7 is connected with the working voltage VDD, the source electrode of the fourth NMOS tube M7 is connected with the drain electrode of the fifth NMOS tube M8, the source electrode of the fifth NMOS tube M8 is grounded, and the grid electrode of the fifth NMOS tube M8 is connected with the second clock signal CLK-;
the drain electrode of the second PMOS tube M4 is also connected with the source electrode of the third PMOS tube M5, the drain electrode of the third PMOS tube M5 is connected with the drain electrode of the fourth NMOS tube M7, the grid electrode of the third PMOS tube M5 is connected with the drain electrode of the first PMOS tube M1, and the grid electrode of the third PMOS tube M5 is connected with the drain electrode of the third NMOS tube M6;
the source electrode of the third NMOS tube M6 is connected with the source electrode of the first NMOS tube M2, and the grid electrode of the third NMOS tube M6 is connected with the grid electrode of the sixth NMOS tube M9;
the grid electrode of the sixth NMOS tube M9 is also connected with the drain electrode of the fourth NMOS tube M7, the source electrode of the sixth NMOS tube M9 is connected with the source electrode of the third NMOS tube M6, and the drain electrode of the sixth NMOS tube M9 is connected with the source electrode of the bootstrap switch SW;
the source electrode of the bootstrap switch SW is connected with the input voltage Vin, the drain electrode of the bootstrap switch SW is connected with the power supply output VOUT, and the grid electrode of the bootstrap switch SW is connected with the grid electrode of the sixth NMOS tube M9;
the substrate switch is connected to the grid of the bootstrap switch SW, the substrate switch comprises a seventh NMOS tube M10 and an eighth NMOS tube M11, the grid of the bootstrap switch SW is connected to the grid of the eighth NMOS tube M11, the substrate of the bootstrap switch SW is connected to the source of the eighth NMOS tube M11, the drain of the eighth NMOS tube M11 is connected to the source of the bootstrap switch SW, and the source of the eighth NMOS tube M11 is connected to the drain of the seventh NMOS tube M10;
the gate of the seventh NMOS transistor M10 is connected to the second clock signal CLK-, and the source of the seventh NMOS transistor M10 is grounded.
The working process of the invention is as follows:
1) When the first clock signal CLK is at a high level, the CMOS gate voltage bootstrap switch circuit is in a sampling stage, the first NMOS transistor M2 is turned on, the gate of the third PMOS transistor M5 is grounded, so that the third PMOS transistor M5 is turned on, the gate voltages of the third NMOS transistor M6, the sixth NMOS transistor M9, the eighth NMOS transistor M11 and the bootstrap switch SW are raised, the second NMOS transistor M3 and the second PMOS transistor M4 are turned off, the sixth NMOS transistor M9 is turned on, the sampling switch SW is turned on, the eighth NMOS transistor M11 is turned on, the first capacitor C1 is connected to the gate source of the bootstrap switch SW, and since the total charge stored in the first capacitor C1 is unchanged, the gate voltage of the bootstrap switch SW is raised to vdd+vin, and the gate source voltage of the bootstrap switch SW is VDD.
2) When the first clock signal CLK is at a low level, the CMOS gate bootstrap switch circuit is in a hold stage, the first PMOS transistor M1, the second NMOS transistor M3 and the second PMOS transistor M4 are turned on, the gate of the third PMOS transistor M5 is connected to the working voltage VDD, the third PMOS transistor M5 is turned off, the sixth NMOS transistor M9 is turned off, the sampling switch SW is turned off, the first capacitor C1 is charged to the working voltage VDD through the second NMOS transistor M3 and the second PMOS transistor M4, the capacitance value of the first capacitor C1 is F, and then the electric quantity of f×vdd is stored in the first capacitor C1, and since the third PMOS transistor M5 is turned off, the first capacitor C1 is separated from the sampling switch SW, the source of the sampling switch SW is grounded through the second NMOS transistor M3, and the gate is grounded through the fourth NMOS transistor M7 and the fifth NMOS transistor M8, thereby discharging.
According to the invention, the substrate switch, namely the seventh NMOS tube and the eighth NMOS tube, is connected to the bootstrap switch, so that the grid potential of the bootstrap switch is consistent with the substrate potential during sampling, the second-order effect intermediate effect of the MOS tube can be reduced, the harmonic distortion is reduced, the linearity of the sampling switch SW is ensured, the precision of a sampling switch circuit is improved, and the influence of the switch linearity on the ADC precision is greatly reduced.
The above embodiments are only for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made thereto without departing from the spirit and scope of the technical solution of the present invention, which is intended to be covered by the scope of the claims of the present invention. The technology, shape, and construction parts of the present invention, which are not described in detail, are known in the art.
Claims (2)
1. The grid voltage bootstrap switch is characterized by comprising a first capacitor (C1) and a plurality of MOS tubes, wherein the MOS tubes comprise a first PMOS tube (M1), a first NMOS tube (M2), a second NMOS tube (M3), a second PMOS tube (M4), a third PMOS tube (M5), a third NMOS tube (M6), a fourth NMOS tube (M7), a fifth NMOS tube (M8), a sixth NMOS tube (M9), a bootstrap Switch (SW) and a substrate switch, the sources of the first PMOS tube (M1) and the second PMOS tube (M4) are connected with a working voltage VDD, the drain electrode of the first PMOS tube (M1) is connected with the drain electrode of the first NMOS tube (M2), the grid electrodes of the first PMOS tube (M1) and the first NMOS tube (M2) are both connected with a first clock signal CLK, the source electrode of the first NMOS tube (M2) is connected with the drain electrode of the second NMOS tube (M3), the grid electrode of the second NMOS tube (M3) is connected with a second clock signal CLK-, the second clock signal CLK-is an inversion signal of the first clock signal CLK, and the source electrode of the second NMOS tube (M3) is grounded;
the drain electrode of the second PMOS tube (M4) is connected with the upper polar plate of the first capacitor (C1), the lower polar plate of the first capacitor (C1) is connected with the source electrode of the first NMOS tube (M2), the grid electrode of the second PMOS tube (M4) is connected with the drain electrode of the fourth NMOS tube (M7), the grid electrode of the fourth NMOS tube (M7) is connected with the working voltage VDD, the source electrode of the fourth NMOS tube (M7) is connected with the drain electrode of the fifth NMOS tube (M8), the source electrode of the fifth NMOS tube (M8) is grounded, and the grid electrode of the fifth NMOS tube (M8) is connected with the second clock signal CLK-;
the drain electrode of the second PMOS tube (M4) is also connected with the source electrode of a third PMOS tube (M5), the drain electrode of the third PMOS tube (M5) is connected with the drain electrode of a fourth NMOS tube (M7), the grid electrode of the third PMOS tube (M5) is connected with the drain electrode of the first PMOS tube (M1), and the grid electrode of the third PMOS tube (M5) is connected with the drain electrode of a third NMOS tube (M6);
the source electrode of the third NMOS tube (M6) is connected with the source electrode of the first NMOS tube (M2), and the grid electrode of the third NMOS tube (M6) is connected with the grid electrode of the sixth NMOS tube (M9);
the grid electrode of the sixth NMOS tube (M9) is also connected with the drain electrode of the fourth NMOS tube (M7), the source electrode of the sixth NMOS tube (M9) is connected with the source electrode of the third NMOS tube (M6), and the drain electrode of the sixth NMOS tube (M9) is connected with the source electrode of the bootstrap Switch (SW);
the source electrode of the bootstrap Switch (SW) is connected with the input voltage Vin, the drain electrode of the bootstrap Switch (SW) is connected with the power supply output VOUT, and the grid electrode of the bootstrap Switch (SW) is connected with the grid electrode of the sixth NMOS tube (M9);
the substrate switch is connected to the grid electrode of the bootstrap Switch (SW), the substrate switch comprises a seventh NMOS tube (M10) and an eighth NMOS tube (M11), the grid electrode of the bootstrap Switch (SW) is connected to the grid electrode of the eighth NMOS tube (M11), the substrate of the bootstrap Switch (SW) is connected to the source electrode of the eighth NMOS tube (M11), the drain electrode of the eighth NMOS tube (M11) is connected to the source electrode of the bootstrap Switch (SW), and the source electrode of the eighth NMOS tube (M11) is connected to the drain electrode of the seventh NMOS tube (M10);
the grid electrode of the seventh NMOS tube (M10) is connected with a second clock signal CLK-, and the source electrode of the seventh NMOS tube (M10) is grounded;
when the first clock signal CLK is at a low level, the gate voltage bootstrap switch is in a holding stage, the first PMOS tube (M1), the second NMOS tube (M3) and the second PMOS tube (M4) are turned on, the gate electrode of the third PMOS tube (M5) is connected to the working voltage VDD, the third PMOS tube (M5) is turned off, the sixth NMOS tube (M9) is turned off, the bootstrap Switch (SW) is turned off, the second NMOS tube (M3) and the second PMOS tube (M4) charge the first capacitor (C1) to the working voltage VDD, and the capacitance value of the first capacitor (C1) is F, then the electric quantity of f×vdd is stored in the first capacitor (C1), and because the third PMOS tube (M5) is turned off, the first capacitor (C1) is separated from the bootstrap Switch (SW), and the source electrode of the Switch (SW) is grounded through the second NMOS tube (M3), and the gate electrode of the Switch (SW) is grounded through the fourth NMOS tube (M7) and the fifth NMOS tube (M8), thereby the bootstrap Switch (SW) is discharged.
2. The gate voltage bootstrapping switch of claim 1, wherein when the first clock signal CLK is at a high level, the gate voltage bootstrapping switch is in a sampling stage, the first NMOS (M2) is turned on, the third PMOS (M5) gate is grounded, so that the third PMOS (M5) is turned on, the gate voltage of the third NMOS (M6), sixth NMOS (M9), eighth NMOS (M11) and bootstrapping Switch (SW) is raised, the second NMOS (M3) and second PMOS (M4) are turned off, the sixth NMOS (M9) is turned on, the bootstrapping Switch (SW) is turned off, the eighth NMOS (M11) is turned on, the first capacitor (C1) is connected to the gate source of the bootstrapping Switch (SW), the gate voltage of the bootstrapping Switch (SW) is raised to vdd+vin, and the gate voltage of the bootstrapping Switch (SW) is VDD.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811042575.4A CN108777579B (en) | 2018-09-07 | 2018-09-07 | Grid voltage bootstrapping switch |
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| CN201811042575.4A CN108777579B (en) | 2018-09-07 | 2018-09-07 | Grid voltage bootstrapping switch |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110635791B (en) * | 2019-09-06 | 2023-03-31 | 重庆邮电大学 | Grid voltage bootstrap sampling switch circuit adopting mirror image structure |
| CN111245413B (en) * | 2020-01-20 | 2023-05-26 | 电子科技大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN113206659B (en) * | 2021-05-10 | 2022-05-10 | 西安电子科技大学重庆集成电路创新研究院 | High-speed high-linearity grid voltage bootstrap switch for pipeline ADC |
| CN113726321B (en) * | 2021-09-06 | 2023-09-22 | 联合微电子中心有限责任公司 | Bootstrap switch circuit and analog-to-digital converter |
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| CN108777579A (en) | 2018-11-09 |
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