CN106160743A - A kind of boot-strapped switch circuit for sampling hold circuit - Google Patents
A kind of boot-strapped switch circuit for sampling hold circuit Download PDFInfo
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- CN106160743A CN106160743A CN201610529376.0A CN201610529376A CN106160743A CN 106160743 A CN106160743 A CN 106160743A CN 201610529376 A CN201610529376 A CN 201610529376A CN 106160743 A CN106160743 A CN 106160743A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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Abstract
The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind of boot-strapped switch circuit for sampling hold circuit.Present configuration with the addition of bootstrap voltage mode increasing circuit on the basis of tradition Bootstrap circuit, thus increases sampling bootstrap voltage mode further, not only reduces the conducting resistance of sampling switch, accelerates response speed, and be more reduction of threshold voltage VTHIn due to VinThe non-linear distortion brought, improves the linearity and the sampling precision of switch.It is an object of the invention to provide a kind of novel boot-strapped switch circuit, it is adaptable to low supply voltage, in high precision, the application of high-speed sampling.
Description
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical field, be specifically related to a kind of Bootstrap for sampling hold circuit
On-off circuit.
Background technology
Sampling hold circuit (SHA) is the core cell of analog-digital converter (ADC), directly determines the performance of whole ADC.And
Sampling switch is again vital part in sampling hold circuit, no matter is also to apply to low to traditional closed-loop type SHA
For the SHA-less structure of power consumption, it have impact on precision and the linearity of sampling hold circuit the most to a great extent.
In general, high performance sampling switch is in order to reduce the sampling letter caused due to MOS switch conducting non-linear
Number distortion improves precision simultaneously, needs to use bootstrapped switch technology, is illustrated in figure 1 a kind of existing boot-strapped switch electricity
Road.In figure, MN0 realizes switching function, and remainder is Bootstrap circuit, in biphase non-overlapping clock (forward clock signal
PHN and reverse clock signal PHP) control under this circuit have two duties:
(1) when PHN is low level, and PHP is high level, circuit is in preliminary filling/discharge condition.Now, MN1 and MN6 breaks
Opening, MN5 turns on, and MP2 disconnects owing to grid voltage is pulled up to high level.Meanwhile, MN2, MN3 and MN4 turn on, MP1 due to
Grid voltage is pulled down to low level and turns on.The voltage at this state down-sampling electric capacity C1 two ends is VDD, sampling switch pipe MN0 grid
Pole tension ground connection, therefore switch OFF.
(2) when PHN is high level, and PHP is low level, circuit enters Bootstrap duty.MN2, MN3, MN4 and
MN5 turns off, MN1 and MN6 turns on, and MP2 turns on owing to grid voltage is pulled down to low level, and MP1 is drawn due to grid voltage
Being raised to high level and turn off, at this moment the voltage of electric capacity C1 top crown and bottom crown is respectively VinAnd VDD+Vin, so sampling switch
The gate source voltage of pipe MN0 is fixed on VDD。
In the switch closure phase stage, the conducting resistance expression formula of boot-strapped switch is:
Wherein, μ is electron mobility, CoxBeing gate oxide capacitance, W/L is metal-oxide-semiconductor breadth length ratio, VTHIt is threshold voltage, VSB
It is that source serves as a contrast electric potential difference.
Formula (1) shows that Bootstrap technology achieves gate source voltage VGSThe most not by input signal VinThe impact of change, changes
It is apt to non-linear distortion, but VTHMiddle source lining electric potential difference VSBDue to input voltage VinThe nonlinear problem that change causes is not
Effectively eliminated, and along with supply voltage V in modern craftsDDContinuous reduction, VSBThe non-linear distortion brought can more be come
Seriously.Therefore, design one is applicable to low supply voltage, has more low switch conducting resistance and more low nonlinearity distortion, simultaneously
The bootstrapped switch having quick response speed is necessary.
Summary of the invention
The deficiency of existing boot-strapped switch circuit, the present invention in order to solve above-mentioned to be applied at a high speed, in high-precision circuit
Provide a kind of novel Bootstrap grid source following sampling switch, increase sampling bootstrap voltage mode further, not only reduce sampling
The conducting resistance of switch, accelerates response speed, and is more reduction of threshold voltage VTHIn due to VinThat is brought is non-linear
Distortion, improves the linearity and the sampling precision of switch.It is an object of the invention to provide a kind of novel boot-strapped switch electricity
Road, it is adaptable to low supply voltage, in high precision, the application of high-speed sampling.
The technical solution used in the present invention is: a kind of boot-strapped switch circuit for sampling hold circuit, including
One PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS
Pipe MP6, sampling switch pipe MN0, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4,
5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3；
Wherein, the source electrode of the 5th PMOS MP5 connects power supply, and its grid connects forward clock signal；The source electrode of the 3rd PMOS MP3 connects the 5th
Missing of PMOS MP5, the grid of the 3rd PMOS MP3 connects forward clock signal；The source electrode of the 6th PMOS MP6 connects power supply,
Its grid connects forward clock signal；The source electrode of the 4th PMOS MP4 connects the drain electrode of the 6th PMOS MP6, the 4th PMOS MP4
Grid connects reverse clock signal, and the drain electrode of the 4th PMOS MP4 is followed by the drain electrode of the 5th PMOS MP5 by the second electric capacity C2；
The drain electrode of the 7th NMOS tube MN7 connects the drain electrode of the 4th PMOS MP4, the source ground of the 7th NMOS tube MN7；4th PMOS
The source electrode of MP4 is by ground connection after the 3rd electric capacity C3；The grid of the second NMOS tube MN2 connects forward clock signal, its source ground；The
The drain electrode of one NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2, and the grid of the first NMOS tube MN1 connects reverse clock signal, and first
The source electrode of NMOS tube MN1 connects external signal input terminals；The source electrode of the first PMOS MP1 connects the drain electrode of the 3rd PMOS MP3, and first
The grid of PMOS MP1 connects the drain electrode of the second PMOS MP2, and the drain electrode of the first PMOS MP1 is followed by by the first electric capacity C1
The drain electrode of two NMOS tube MN2；5th NMOS tube MN5 miss the drain electrode connecing the 3rd PMOS MP3, the grid of the 5th NMOS tube MN5
Pole connects forward clock signal；6th NMOS tube MN6 miss the source electrode connecing the 5th NMOS tube MN5, the grid of the 6th NMOS tube MN6
Connect reverse clock signal, the source ground of the 6th NMOS tube MN6；The source electrode of the second PMOS MP2 connects the leakage of the first PMOS MP1
Pole, the grid of the second PMOS MP2 connects the source electrode of the 5th NMOS tube MN5；The grid of sampling switch pipe MN0 connects the second PMOS
The drain electrode of MP2, the source electrode of sampling switch pipe MN0 connects external signal input terminals, and the drain electrode of sampling switch pipe MN0 is signal output
End；The drain electrode of the 3rd NMOS tube MN3 connects missing of the second PMOS MP2, and the grid of the 3rd NMOS tube MN3 connects power supply；4th
NMOS tube MN4 miss the source electrode connecing the 3rd NMOS tube MN3, the grid of the 4th NMOS tube MN4 connects forward clock signal, the 4th
The source ground of NMOS tube MN4.
Present configuration with the addition of bootstrap voltage mode increasing circuit on the basis of tradition Bootstrap circuit described in Fig. 1, bag
Include: sampling capacitance C2, C3, MN7, MP3, MP4, MP5 and MP6.Wherein, MP5 source meets supply voltage VDD, grid connect clock control
Signal PHP, drain terminal is connected with the bottom crown of sampling capacitance C2 and the source of MP3, and MP6 source meets supply voltage VDD, grid connects
Clock control signal PHP, drain terminal is connected with the bottom crown of sampling capacitance C3 and the source of MP4, sampling capacitance C2 top crown with
MP4 drain terminal is connected with MN7 drain terminal, and the grid of MP4 and MN7 connects clock signal PHN, and MN7 source connects sampling capacitance C3 top crown
And ground connection VSS.MP3 grid meets clock control signal PHN, and drain terminal is as bootstrap voltage mode VBOutfan is connected to Bootstrap circuit MP1
Source and the drain terminal of MN5.
The invention have the benefit that
(1) greatly reduce the conducting resistance of sampling switch, thus improve response speed.
(2) input voltage V is significantly reducedinThe non-linear distortion of sampling switch is affected, and then improves sampling switch
The linearity and precision.
(3) application scenarios of low supply voltage it is particularly suited for, hence it is evident that improve the linearity and the precision of sampling switch.
Accompanying drawing explanation
Fig. 1 is tradition Bootstrap circuit theory diagrams；
Fig. 2 is the novel grid voltage boostrap circuit schematic diagram of the present invention；
Fig. 3 is the novel grid voltage boostrap circuit fundamental diagram of the present invention；Wherein, (a) is when PHN is low level, and PHP is
High level, (b) is high level as PHN, the low high level of PHP；
Fig. 4 is the grid voltage V of tradition and Bootstrap circuit of the present inventionGTime domain waveform contrast schematic diagram；Wherein,
A () is traditional circuit, (b) is the circuit of the present invention；
Fig. 5 is the Simulation of Dynamic Performance result schematic diagram of tradition boot-strapped switch；
Fig. 6 is the Simulation of Dynamic Performance result schematic diagram of the novel grid voltage bootstrap switch circuit of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawings the present invention is described in detail:
As in figure 2 it is shown, a kind of boot-strapped switch circuit for sampling hold circuit of the present invention, including a PMOS
Pipe MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6,
Sampling switch pipe MN0, the first NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th
NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3；Wherein,
The source electrode of the 5th PMOS MP5 connects power supply, and its grid connects forward clock signal；The source electrode of the 3rd PMOS MP3 meets the 5th PMOS
Pipe MP5 misses, and the grid of the 3rd PMOS MP3 connects forward clock signal；The source electrode of the 6th PMOS MP6 connects power supply, its grid
Pole connects forward clock signal；The source electrode of the 4th PMOS MP4 connects the drain electrode of the 6th PMOS MP6, the grid of the 4th PMOS MP4
Connecing reverse clock signal, the drain electrode of the 4th PMOS MP4 is followed by the drain electrode of the 5th PMOS MP5 by the second electric capacity C2；7th
The drain electrode of NMOS tube MN7 connects the drain electrode of the 4th PMOS MP4, the source ground of the 7th NMOS tube MN7；4th PMOS MP4
Source electrode is by ground connection after the 3rd electric capacity C3；The grid of the second NMOS tube MN2 connects forward clock signal, its source ground；First
The drain electrode of NMOS tube MN1 connects the drain electrode of the second NMOS tube MN2, and the grid of the first NMOS tube MN1 connects reverse clock signal, and first
The source electrode of NMOS tube MN1 connects external signal input terminals；The source electrode of the first PMOS MP1 connects the drain electrode of the 3rd PMOS MP3, and first
The grid of PMOS MP1 connects the drain electrode of the second PMOS MP2, and the drain electrode of the first PMOS MP1 is followed by by the first electric capacity C1
The drain electrode of two NMOS tube MN2；5th NMOS tube MN5 miss the drain electrode connecing the 3rd PMOS MP3, the grid of the 5th NMOS tube MN5
Pole connects forward clock signal；6th NMOS tube MN6 miss the source electrode connecing the 5th NMOS tube MN5, the grid of the 6th NMOS tube MN6
Connect reverse clock signal, the source ground of the 6th NMOS tube MN6；The source electrode of the second PMOS MP2 connects the leakage of the first PMOS MP1
Pole, the grid of the second PMOS MP2 connects the source electrode of the 5th NMOS tube MN5；The grid of sampling switch pipe MN0 connects the second PMOS
The drain electrode of MP2, the source electrode of sampling switch pipe MN0 connects external signal input terminals, and the drain electrode of sampling switch pipe MN0 is signal output
End；The drain electrode of the 3rd NMOS tube MN3 connects missing of the second PMOS MP2, and the grid of the 3rd NMOS tube MN3 connects power supply；4th
NMOS tube MN4 miss the source electrode connecing the 3rd NMOS tube MN3, the grid of the 4th NMOS tube MN4 connects forward clock signal, the 4th
The source ground of NMOS tube MN4
The operation principle of the present invention is as follows:
(1) when PHN is high level, and PHP is low level, in Fig. 2, (a) partial circuit is in preliminary filling/discharge condition.This
Time, MP5, MP6 and MN7 conducting, MP3 and MP4 turns off, and therefore supply voltage is pre-charged to V to electric capacity C2 and C3 simultaneouslyDD,
Wherein bottom crown voltage is VDD, and top crown voltage is VSS.(b) part then entrance Bootstrap duty in Fig. 2, MN2,
MN3, MN4, MN5 and MP1 turn off, and MN1, MN6 and MP2 turn on；Sampling switch pipe MN0 turns on, and sampled input signal, on electric capacity C1
The voltage of pole plate and bottom crown is respectively VinAnd VS,P1+Vin.Shown in the working state schematic representation of whole circuit such as Fig. 3 (b).
(2) when PHN is low level, and PHP is high level, in Fig. 2, (a) partial circuit enters Bootstrap duty.
MP5, MP6 and MN7 turn off, MP3 and MP4 turns on.So for C2, due to principle of charge conservation, the bottom crown voltage of C2
VBIt is lifted to 2VDD, and (the V that is connected with the source of MP1S,P1=2VDD).In Fig. 2, (b) partial circuit is then in pre-discharge charge
Electricity condition, MN1, MN6 and MP2 disconnection, MN2, MN3, MN4, MN5 and MP1 conducting, sampling switch pipe MN0 turns off, now electric capacity C1
Top crown ground connection VSS, bottom crown and VBBeing connected, therefore the voltage on C1 is 2VDD, and unconventional VDD.The work of whole circuit
Shown in view such as Fig. 3 (a).
(3) being high level again as PHN, when PHP is low level again, sampling switch pipe MN0 turns on, and enters Bootstrap
Duty, starts to receive input signal, and such C1 both end voltage is respectively VinAnd 2VDD+Vin, so the gate source voltage quilt of MN0
It is fixed on 2VDD, and the V of non-traditional structureDD, it is doubled.
Novel grid voltage bootstrap switch circuit shown in Fig. 2 and the traditional boot-strapped switch circuit shown in Fig. 1 are imitated
Very, ensure that simulated conditions, input signal and sampled clock signal keep constant simultaneously.Wherein, supply voltage VDDFor 1.2V, adopt
Sample clock frequency is 200MHz.
Circuit is carried out Transient and obtains tradition (a) the Bootstrap circuit shown in Fig. 4 and novel (b) Bootstrap electricity
Switch MN0 grid voltage V under the application of roadGOutput voltage time domain beamformer, by time domain beamformer contrast, novel grid
The grid voltage V of pressure bootstrap switch circuitGReally than the V of traditional structureGWant height.Ideally, according to charge conservation theorem:
QΦ2=C2·(VDD-0)+C3·(VDD-0) (2)
QΦ1=CΦ12·(VS,P1-0)=Q (3)
VS,P1=2VDD (4)
Wherein, QΦ2Represent and be stored in the total charge dosage in electric capacity C2, C3, Q when PHP is low levelΦ1Represent when PHP is
The quantity of electric charge in electric capacity C1, therefore V it is stored in during high levelG=2VDD+Vin.But, lose owing to there is charge leakage and electric capacity
Problem, the switch MN0 grid voltage V that emulation obtains such as joinGIt is about 1.5VDD+Vin.Additionally, as input voltage VinTime less, because of
Input voltage VinAt grid voltage VGMiddle proportion is too small, and charge distributing is affected and causes grid voltage VGFollow input
Voltage VinChange is slowly.These problems, need to be optimized further.
Again to boot-strapped switch conducting resistance RonPerform an analysis, obtain tradition boot-strapped switch circuit and novel grid voltage from
Lift on-off circuit resistance value table, as shown in table 1:
Table 1 is tradition Bootstrap circuit and novel grid voltage boostrap circuit conduction resistance value RonContrast table
Conducting resistance R of tradition boot-strapped switchonMaximum is 45 Ω, and minima is 25 Ω, and meansigma methods is about 35 Ω；
And novel boot-strapped switch conducting resistance RonMaximum is 25 Ω, and minima is 20 Ω, and meansigma methods is about 22 Ω, by emulation
Comparative result finds, the conducting resistance resistance of novel boot-strapped switch is more stable, and resistance value significantly reduces, and compares conventional junction
Structure decreases 37%, therefore improves switch response speed.
Ultimate analysis tradition boot-strapped switch circuit and the dynamic property of novel grid voltage bootstrap switch circuit, respectively to adopting
The output result of sample holding circuit makees fast Fourier transform (FFT) spectrum analysis, obtains output spectrum such as Fig. 5 and Fig. 6.Novel
The SFDR (SFDR) of boot-strapped switch circuit is 78.66dB, higher than the 70.79dB of traditional boot-strapped switch
About 8dB, illustrates that novel boot-strapped switch has the more preferable linearity than traditional boot-strapped switch；Novel Bootstrap
The SINAD (signal is to noise and harmonic ratio value) of on-off circuit is 76.75dB, and corresponding ENOB (effective accuracy) is 12.46-
Bit, the effective accuracy than the 11.28-bit of traditional structure improves about 1.2-bit, hence it is evident that improve the precision of sampling switch.
By the novel boot-strapped switch of omnibearing contrast and tradition boot-strapped switch circuit, we can draw knot
Opinion, novel Bootstrap grid source following sampling switch really further increases bootstrap voltage mode, not only reduces sampling switch
Conducting resistance, accelerates response speed, and especially by VinCaused non-linear distortion, improves the linearity of switch and adopts
Sample precision, be therefore highly suitable for low supply voltage, in high precision, the application scenarios of high-speed sampling.
Claims (1)
1. for the boot-strapped switch circuit of sampling hold circuit, including the first PMOS MP1, the second PMOS MP2,
3rd PMOS MP3, the 4th PMOS MP4, the 5th PMOS MP5, the 6th PMOS MP6, sampling switch pipe MN0, first
NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube
MN6, the 7th NMOS tube MN7, the first electric capacity C1, the second electric capacity C2 and the 3rd electric capacity C3；Wherein, the source electrode of the 5th PMOS MP5
Connecing power supply, its grid connects forward clock signal；The source electrode of the 3rd PMOS MP3 connects missing of the 5th PMOS MP5, the 3rd PMOS
The grid of pipe MP3 connects forward clock signal；The source electrode of the 6th PMOS MP6 connects power supply, and its grid connects forward clock signal；4th
The source electrode of PMOS MP4 connects the drain electrode of the 6th PMOS MP6, and the grid of the 4th PMOS MP4 connects reverse clock signal, and the 4th
The drain electrode of PMOS MP4 is followed by the drain electrode of the 5th PMOS MP5 by the second electric capacity C2；The drain electrode of the 7th NMOS tube MN7 connects
The drain electrode of four PMOS MP4, the source ground of the 7th NMOS tube MN7；The source electrode of the 4th PMOS MP4 is by after the 3rd electric capacity C3
Ground connection；The grid of the second NMOS tube MN2 connects forward clock signal, its source ground；The drain electrode of the first NMOS tube MN1 connects second
The drain electrode of NMOS tube MN2, the grid of the first NMOS tube MN1 connects reverse clock signal, and the source electrode of the first NMOS tube MN1 connects outside letter
Number input；The source electrode of the first PMOS MP1 connects the drain electrode of the 3rd PMOS MP3, and the grid of the first PMOS MP1 connects second
The drain electrode of PMOS MP2, the drain electrode of the first PMOS MP1 is followed by the drain electrode of the second NMOS tube MN2 by the first electric capacity C1；5th
NMOS tube MN5 miss the drain electrode connecing the 3rd PMOS MP3, the grid of the 5th NMOS tube MN5 connects forward clock signal；6th
NMOS tube MN6 miss the source electrode connecing the 5th NMOS tube MN5, the grid of the 6th NMOS tube MN6 connects reverse clock signal, the 6th
The source ground of NMOS tube MN6；The source electrode of the second PMOS MP2 connects the drain electrode of the first PMOS MP1, the second PMOS MP2
Grid connects the source electrode of the 5th NMOS tube MN5；The grid of sampling switch pipe MN0 connects the drain electrode of the second PMOS MP2, sampling switch pipe
The source electrode of MN0 connects external signal input terminals, and the drain electrode of sampling switch pipe MN0 is signal output part；The drain electrode of the 3rd NMOS tube MN3
Connecing missing of the second PMOS MP2, the grid of the 3rd NMOS tube MN3 connects power supply；Missing of 4th NMOS tube MN4 meets the 3rd NMOS
The source electrode of pipe MN3, the grid of the 4th NMOS tube MN4 connects forward clock signal, the source ground of the 4th NMOS tube MN4.
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Cited By (13)
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| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN107465407A (en) * | 2017-09-19 | 2017-12-12 | 英特格灵芯片(天津)有限公司 | A kind of earth leakage protective type bootstrapping sampling switch circuit and equipment |
| CN107968642A (en) * | 2018-01-11 | 2018-04-27 | 厦门理工学院 | A kind of dual bootstrap sampling switch circuit of low voltage application |
| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN108777579A (en) * | 2018-09-07 | 2018-11-09 | 广西师范大学 | Boot-strapped switch |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
| CN110149111A (en) * | 2019-04-18 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of bootstrap switch circuit and its control method |
| CN111245413A (en) * | 2020-01-20 | 2020-06-05 | 电子科技大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN112383292A (en) * | 2020-12-18 | 2021-02-19 | 福州大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN113014259A (en) * | 2021-02-25 | 2021-06-22 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN114172518A (en) * | 2022-02-14 | 2022-03-11 | 山东兆通微电子有限公司 | Sampling hold circuit and analog-to-digital converter |
| CN115378433A (en) * | 2022-07-29 | 2022-11-22 | 北京时代民芯科技有限公司 | 1.25GHz broadband self-bias low-power-consumption sample hold circuit |
| CN116886094A (en) * | 2023-07-24 | 2023-10-13 | 同济大学 | Bootstrap switch sampling circuit |
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| CN108616279A (en) * | 2016-12-12 | 2018-10-02 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of low jitter multichannel intermediate-freuqncy signal acquisition clock circuit |
| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN107465407A (en) * | 2017-09-19 | 2017-12-12 | 英特格灵芯片(天津)有限公司 | A kind of earth leakage protective type bootstrapping sampling switch circuit and equipment |
| CN107465407B (en) * | 2017-09-19 | 2023-07-28 | 豪威模拟集成电路(北京)有限公司 | Leakage protection type bootstrap sampling switch circuit and equipment |
| CN107968642A (en) * | 2018-01-11 | 2018-04-27 | 厦门理工学院 | A kind of dual bootstrap sampling switch circuit of low voltage application |
| CN108806757A (en) * | 2018-06-19 | 2018-11-13 | 广州领知信息技术有限公司 | High-speed boosting type signal sampling transmitting switch |
| CN108777579A (en) * | 2018-09-07 | 2018-11-09 | 广西师范大学 | Boot-strapped switch |
| CN108777579B (en) * | 2018-09-07 | 2023-08-11 | 广西师范大学 | Grid voltage bootstrapping switch |
| CN110149111B (en) * | 2019-04-18 | 2023-05-02 | 珠海亿智电子科技有限公司 | Bootstrap switch circuit and control method thereof |
| CN110149111A (en) * | 2019-04-18 | 2019-08-20 | 珠海亿智电子科技有限公司 | A kind of bootstrap switch circuit and its control method |
| CN111245413B (en) * | 2020-01-20 | 2023-05-26 | 电子科技大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN111245413A (en) * | 2020-01-20 | 2020-06-05 | 电子科技大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN112383292B (en) * | 2020-12-18 | 2023-07-28 | 福州大学 | High-speed high-linearity grid voltage bootstrapping switch circuit |
| CN112383292A (en) * | 2020-12-18 | 2021-02-19 | 福州大学 | High-speed high-linearity grid voltage bootstrap switch circuit |
| CN113014259A (en) * | 2021-02-25 | 2021-06-22 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN113014259B (en) * | 2021-02-25 | 2024-07-05 | 中国科学院微电子研究所 | Sampling switch circuit and analog-to-digital converter |
| CN114172518A (en) * | 2022-02-14 | 2022-03-11 | 山东兆通微电子有限公司 | Sampling hold circuit and analog-to-digital converter |
| CN115378433A (en) * | 2022-07-29 | 2022-11-22 | 北京时代民芯科技有限公司 | 1.25GHz broadband self-bias low-power-consumption sample hold circuit |
| CN115378433B (en) * | 2022-07-29 | 2023-10-03 | 北京时代民芯科技有限公司 | 1.25GHz broadband self-bias low-power-consumption sample hold circuit |
| CN116886094A (en) * | 2023-07-24 | 2023-10-13 | 同济大学 | Bootstrap switch sampling circuit |
| CN116886094B (en) * | 2023-07-24 | 2024-03-29 | 同济大学 | Bootstrap switch sampling circuit |
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